Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 303990820 1 T1 259848 T6 15576 T7 3942
auto[1] 430388 1 T1 1786 T2 1446 T42 68


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304015758 1 T1 259922 T6 15576 T7 3942
auto[1] 405450 1 T1 1048 T2 1160 T4 2028


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 303934674 1 T1 259874 T6 15576 T7 3942
auto[1] 486534 1 T1 1526 T2 1558 T30 186


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 289097410 1 T1 259711 T6 15576 T7 3942
auto[1] 15323798 1 T1 3158 T2 5080 T30 2638


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 176413494 1 T1 901826 T6 15576 T7 3924
auto[1] 128007714 1 T1 169844 T7 18 T23 170


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 164548300 1 T1 898718 T6 15576 T7 3924
auto[0] auto[0] auto[0] auto[0] auto[1] 124207570 1 T1 169760 T7 18 T23 170
auto[0] auto[0] auto[0] auto[1] auto[0] 30364 1 T1 98 T2 12 T100 264
auto[0] auto[0] auto[0] auto[1] auto[1] 7144 1 T1 28 T2 12 T17 118
auto[0] auto[0] auto[1] auto[0] auto[0] 11264796 1 T1 1530 T2 3114 T30 2160
auto[0] auto[0] auto[1] auto[0] auto[1] 3684802 1 T1 328 T2 402 T30 308
auto[0] auto[0] auto[1] auto[1] auto[0] 52536 1 T1 156 T2 164 T100 154
auto[0] auto[0] auto[1] auto[1] auto[1] 13352 1 T1 60 T2 18 T101 14
auto[0] auto[1] auto[0] auto[0] auto[0] 70396 1 T1 6 T4 2028 T42 34
auto[0] auto[1] auto[0] auto[0] auto[1] 1544 1 T17 54 T147 16 T140 36
auto[0] auto[1] auto[0] auto[1] auto[0] 11734 1 T1 44 T100 72 T101 90
auto[0] auto[1] auto[0] auto[1] auto[1] 2428 1 T147 58 T148 44 T149 36
auto[0] auto[1] auto[1] auto[0] auto[0] 9412 1 T1 22 T2 56 T30 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2532 1 T30 8 T102 8 T17 94
auto[0] auto[1] auto[1] auto[1] auto[0] 22670 1 T1 150 T2 194 T100 70
auto[0] auto[1] auto[1] auto[1] auto[1] 5094 1 T17 156 T149 42 T150 44
auto[1] auto[0] auto[0] auto[0] auto[0] 54328 1 T1 24 T2 116 T30 16
auto[1] auto[0] auto[0] auto[0] auto[1] 3630 1 T1 10 T100 36 T101 8
auto[1] auto[0] auto[0] auto[1] auto[0] 34480 1 T1 186 T2 62 T101 98
auto[1] auto[0] auto[0] auto[1] auto[1] 8194 1 T1 114 T100 58 T17 182
auto[1] auto[0] auto[1] auto[0] auto[0] 27420 1 T1 24 T2 148 T30 8
auto[1] auto[0] auto[1] auto[0] auto[1] 7138 1 T1 42 T2 16 T30 16
auto[1] auto[0] auto[1] auto[1] auto[0] 57344 1 T1 198 T2 232 T42 68
auto[1] auto[0] auto[1] auto[1] auto[1] 14360 1 T1 102 T2 74 T101 126
auto[1] auto[1] auto[0] auto[0] auto[0] 49074 1 T1 78 T2 50 T30 16
auto[1] auto[1] auto[0] auto[0] auto[1] 5770 1 T2 22 T30 8 T42 42
auto[1] auto[1] auto[0] auto[1] auto[0] 51790 1 T1 202 T2 126 T99 62
auto[1] auto[1] auto[0] auto[1] auto[1] 10664 1 T2 50 T17 80 T141 126
auto[1] auto[1] auto[1] auto[0] auto[0] 42882 1 T1 90 T2 96 T30 92
auto[1] auto[1] auto[1] auto[0] auto[1] 11226 1 T1 8 T2 64 T30 30
auto[1] auto[1] auto[1] auto[1] auto[0] 85968 1 T1 300 T2 386 T100 322
auto[1] auto[1] auto[1] auto[1] auto[1] 22266 1 T1 148 T2 116 T101 92

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