SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
io_div2_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div2_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
shadow_update_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19137 | 1 | T1 | 104 | T6 | 1 | T7 | 1 | ||||
auto[1] | 786 | 1 | T1 | 5 | T2 | 8 | T19 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16324 | 1 | T1 | 91 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3599 | 1 | T1 | 18 | T5 | 1 | T2 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19152 | 1 | T1 | 103 | T6 | 1 | T7 | 1 | ||||
auto[1] | 771 | 1 | T1 | 6 | T2 | 10 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16345 | 1 | T1 | 93 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3578 | 1 | T1 | 16 | T5 | 1 | T2 | 18 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19103 | 1 | T1 | 102 | T6 | 1 | T7 | 1 | ||||
auto[1] | 820 | 1 | T1 | 7 | T2 | 8 | T11 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16328 | 1 | T1 | 91 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3595 | 1 | T1 | 18 | T5 | 1 | T2 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19143 | 1 | T1 | 102 | T6 | 1 | T7 | 1 | ||||
auto[1] | 780 | 1 | T1 | 7 | T2 | 8 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19058 | 1 | T1 | 106 | T6 | 1 | T7 | 1 | ||||
auto[1] | 865 | 1 | T1 | 3 | T2 | 5 | T15 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19755 | 1 | T1 | 109 | T6 | 1 | T7 | 1 | ||||
auto[1] | 168 | 1 | T25 | 2 | T28 | 6 | T60 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19183 | 1 | T1 | 104 | T6 | 1 | T7 | 1 | ||||
auto[1] | 740 | 1 | T1 | 5 | T2 | 7 | T11 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18982 | 1 | T1 | 105 | T6 | 1 | T7 | 1 | ||||
auto[1] | 941 | 1 | T1 | 4 | T5 | 1 | T2 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |