Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1781449452	15077	0	0
TransStop_A	1781449452	7540	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1781449452	15077	0	0
T1	538960	162	0	0
T2	3935024	16	0	0
T3	224216	0	0	0
T4	392204	0	0	0
T11	513544	0	0	0
T12	576304	0	0	0
T15	0	59	0	0
T18	12224	18	0	0
T19	140424	0	0	0
T20	22004	23	0	0
T21	35100	4	0	0
T105	0	20	0	0
T106	0	4	0	0
T107	0	4	0	0
T108	0	41	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1781449452	7540	0	0
T1	538960	95	0	0
T2	3935024	16	0	0
T3	224216	0	0	0
T4	392204	0	0	0
T11	513544	0	0	0
T12	576304	0	0	0
T15	0	20	0	0
T18	12224	12	0	0
T19	140424	0	0	0
T20	22004	14	0	0
T21	35100	4	0	0
T105	0	13	0	0
T106	0	4	0	0
T107	0	4	0	0
T108	0	20	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445362363	3786	0	0
TransStop_A	445362363	1868	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	3786	0	0
T1	134740	40	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	14	0	0
T18	3056	3	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8775	1	0	0
T105	0	6	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	1868	0	0
T1	134740	25	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	3	0	0
T18	3056	2	0	0
T19	35106	0	0	0
T20	5501	3	0	0
T21	8775	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445362363	3791	0	0
TransStop_A	445362363	1893	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	3791	0	0
T1	134740	39	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	15	0	0
T18	3056	4	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8775	1	0	0
T105	0	5	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	1893	0	0
T1	134740	22	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	7	0	0
T18	3056	3	0	0
T19	35106	0	0	0
T20	5501	3	0	0
T21	8775	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445362363	3730	0	0
TransStop_A	445362363	1855	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	3730	0	0
T1	134740	37	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	16	0	0
T18	3056	6	0	0
T19	35106	0	0	0
T20	5501	5	0	0
T21	8775	1	0	0
T105	0	5	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	1855	0	0
T1	134740	18	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	5	0	0
T18	3056	4	0	0
T19	35106	0	0	0
T20	5501	4	0	0
T21	8775	1	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	445362363	3770	0	0
TransStop_A	445362363	1924	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	3770	0	0
T1	134740	46	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	14	0	0
T18	3056	5	0	0
T19	35106	0	0	0
T20	5501	6	0	0
T21	8775	1	0	0
T105	0	4	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445362363	1924	0	0
T1	134740	30	0	0
T2	983756	4	0	0
T3	56054	0	0	0
T4	98051	0	0	0
T11	128386	0	0	0
T12	144076	0	0	0
T15	0	5	0	0
T18	3056	3	0	0
T19	35106	0	0	0
T20	5501	4	0	0
T21	8775	1	0	0
T105	0	2	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	6	0	0