Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327166548

1

T5

1790

T6

2136

T7

3428

auto[1]

381700

1

T21

272

T22

776

T23

328

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327179568

1

T5

1790

T6

2136

T7

3428

auto[1]

368680

1

T21

212

T22

840

T23

296

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327111352

1

T5

1790

T6

2136

T7

3428

auto[1]

436896

1

T21

328

T22

732

T23

448

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313714188

1

T5

1790

T6

2136

T7

3428

auto[1]

13834060

1

T21

2536

T22

3608

T23

2706

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

202081650

1

T5

1790

T6

2118

T7

1796

auto[1]

125466598

1

T6

18

T7

1632

T33

40

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

190504682

1

T5

1790

T6

2118

T7

1796

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

122911412

1

T6

18

T7

1632

T33

40

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

25900

1

T2

404

T18

70

T9

96

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6232

1

T2

68

T3

4

T9

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

11042198

1

T21

320

T22

780

T23

2274

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2450448

1

T21

1936

T22

1830

T23

152

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47254

1

T21

18

T22

56

T23

20

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13134

1

T22

36

T2

190

T18

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

56950

1

T2

28

T9

34

T144

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1230

1

T2

8

T3

2

T145

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11160

1

T2

46

T9

96

T144

68

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2768

1

T3

38

T13

70

T146

42

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9626

1

T22

30

T16

12

T2

94

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3046

1

T2

14

T9

32

T30

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19676

1

T22

160

T16

56

T2

422

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5636

1

T2

86

T9

102

T27

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42184

1

T21

10

T22

16

T23

42

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3230

1

T2

56

T3

22

T9

30

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

28468

1

T21

48

T23

42

T2

144

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7758

1

T2

92

T3

42

T9

158

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

26618

1

T21

2

T22

14

T23

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5474

1

T21

8

T2

38

T18

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52840

1

T21

48

T22

52

T23

66

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11736

1

T2

108

T18

52

T3

86

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53708

1

T21

8

T23

22

T2

72

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5614

1

T2

38

T3

16

T9

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

43230

1

T23

82

T2

548

T18

176

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9662

1

T3

62

T20

64

T28

58

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40420

1

T21

46

T22

144

T23

56

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9708

1

T22

34

T23

18

T16

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

76736

1

T21

158

T22

358

T23

54

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19510

1

T22

114

T23

64

T2

174