Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.53 99.15 95.79 100.00 100.00 98.81 97.01 98.97


Total test records in report: 984
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T753 /workspace/coverage/default/7.clkmgr_frequency.2954658759 Jan 24 04:23:11 PM PST 24 Jan 24 04:23:26 PM PST 24 1548369611 ps
T754 /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2956968531 Jan 24 04:13:16 PM PST 24 Jan 24 04:13:20 PM PST 24 15250663 ps
T755 /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3911871997 Jan 24 04:18:10 PM PST 24 Jan 24 04:18:18 PM PST 24 66161966 ps
T756 /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1811333590 Jan 24 04:18:34 PM PST 24 Jan 24 04:28:40 PM PST 24 68357423575 ps
T757 /workspace/coverage/default/45.clkmgr_regwen.2873388071 Jan 24 04:23:43 PM PST 24 Jan 24 04:23:46 PM PST 24 77010518 ps
T55 /workspace/coverage/default/4.clkmgr_sec_cm.2783415322 Jan 24 04:12:21 PM PST 24 Jan 24 04:12:29 PM PST 24 396674834 ps
T758 /workspace/coverage/default/11.clkmgr_clk_status.2553629277 Jan 24 04:14:11 PM PST 24 Jan 24 04:14:19 PM PST 24 41280473 ps
T759 /workspace/coverage/default/14.clkmgr_alert_test.2528873351 Jan 24 04:15:11 PM PST 24 Jan 24 04:15:13 PM PST 24 15218948 ps
T760 /workspace/coverage/default/17.clkmgr_frequency_timeout.2216053938 Jan 24 04:15:32 PM PST 24 Jan 24 04:15:43 PM PST 24 1113327064 ps
T761 /workspace/coverage/default/21.clkmgr_alert_test.128384991 Jan 24 04:17:01 PM PST 24 Jan 24 04:17:03 PM PST 24 25259362 ps
T762 /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.2250667498 Jan 24 04:15:29 PM PST 24 Jan 24 04:27:14 PM PST 24 107388948769 ps
T763 /workspace/coverage/default/6.clkmgr_trans.1714096029 Jan 24 04:12:38 PM PST 24 Jan 24 04:12:40 PM PST 24 28725366 ps
T764 /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.855549403 Jan 24 04:24:34 PM PST 24 Jan 24 04:24:36 PM PST 24 83392755 ps
T765 /workspace/coverage/default/22.clkmgr_trans.722618143 Jan 24 04:17:06 PM PST 24 Jan 24 04:17:08 PM PST 24 20427001 ps
T766 /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1841772475 Jan 24 04:19:56 PM PST 24 Jan 24 04:19:58 PM PST 24 108725000 ps
T767 /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.3374629139 Jan 24 04:24:33 PM PST 24 Jan 24 04:34:25 PM PST 24 34948002387 ps
T768 /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.454994756 Jan 24 05:49:01 PM PST 24 Jan 24 05:49:02 PM PST 24 29399737 ps
T769 /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3835965232 Jan 24 04:19:14 PM PST 24 Jan 24 04:19:16 PM PST 24 37730698 ps
T770 /workspace/coverage/default/33.clkmgr_stress_all.1008061081 Jan 24 04:19:57 PM PST 24 Jan 24 04:20:22 PM PST 24 4567685875 ps
T771 /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1876503608 Jan 24 04:14:22 PM PST 24 Jan 24 04:14:27 PM PST 24 23029867 ps
T772 /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1491887513 Jan 24 04:15:34 PM PST 24 Jan 24 04:15:41 PM PST 24 36930608 ps
T773 /workspace/coverage/default/6.clkmgr_smoke.1677547523 Jan 24 04:12:33 PM PST 24 Jan 24 04:12:35 PM PST 24 46656847 ps
T774 /workspace/coverage/default/28.clkmgr_alert_test.161986401 Jan 24 05:00:47 PM PST 24 Jan 24 05:00:50 PM PST 24 68309183 ps
T775 /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.2236616725 Jan 24 04:23:52 PM PST 24 Jan 24 04:23:54 PM PST 24 14855528 ps
T776 /workspace/coverage/default/11.clkmgr_frequency_timeout.1855753329 Jan 24 04:14:15 PM PST 24 Jan 24 04:14:31 PM PST 24 1575914621 ps
T777 /workspace/coverage/default/14.clkmgr_regwen.2559327182 Jan 24 04:15:12 PM PST 24 Jan 24 04:15:19 PM PST 24 903880387 ps
T778 /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2659392595 Jan 24 04:20:53 PM PST 24 Jan 24 04:20:55 PM PST 24 50252055 ps
T779 /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.3737742541 Jan 24 04:12:07 PM PST 24 Jan 24 04:12:17 PM PST 24 37085746 ps
T780 /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3083918338 Jan 24 04:13:03 PM PST 24 Jan 24 04:13:05 PM PST 24 71410944 ps
T781 /workspace/coverage/default/4.clkmgr_stress_all.2117108738 Jan 24 04:12:18 PM PST 24 Jan 24 04:12:48 PM PST 24 3205147920 ps
T782 /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2670135999 Jan 24 04:17:16 PM PST 24 Jan 24 04:17:18 PM PST 24 23909653 ps
T783 /workspace/coverage/default/34.clkmgr_stress_all.2582518723 Jan 24 04:20:20 PM PST 24 Jan 24 04:20:46 PM PST 24 5957967683 ps
T784 /workspace/coverage/default/44.clkmgr_frequency.1388207406 Jan 24 04:23:11 PM PST 24 Jan 24 04:23:24 PM PST 24 568868344 ps
T785 /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3883165117 Jan 24 04:15:48 PM PST 24 Jan 24 04:15:51 PM PST 24 28588459 ps
T786 /workspace/coverage/default/45.clkmgr_clk_status.1203767916 Jan 24 04:23:39 PM PST 24 Jan 24 04:23:41 PM PST 24 15286936 ps
T787 /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3730502354 Jan 24 04:20:33 PM PST 24 Jan 24 04:20:36 PM PST 24 91617065 ps
T788 /workspace/coverage/default/29.clkmgr_peri.2727235878 Jan 24 04:18:53 PM PST 24 Jan 24 04:19:00 PM PST 24 40746404 ps
T789 /workspace/coverage/default/33.clkmgr_smoke.452727126 Jan 24 04:19:56 PM PST 24 Jan 24 04:19:58 PM PST 24 23225626 ps
T790 /workspace/coverage/default/34.clkmgr_alert_test.1483652388 Jan 24 04:20:31 PM PST 24 Jan 24 04:20:33 PM PST 24 42590167 ps
T791 /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2063501998 Jan 24 04:12:10 PM PST 24 Jan 24 04:12:17 PM PST 24 27220472 ps
T792 /workspace/coverage/default/43.clkmgr_clk_status.1348007955 Jan 24 04:22:57 PM PST 24 Jan 24 04:23:01 PM PST 24 17721541 ps
T793 /workspace/coverage/default/14.clkmgr_trans.154147494 Jan 24 04:15:01 PM PST 24 Jan 24 04:15:04 PM PST 24 86733865 ps
T794 /workspace/coverage/default/23.clkmgr_frequency.3685773558 Jan 24 04:17:11 PM PST 24 Jan 24 04:17:23 PM PST 24 1645446666 ps
T795 /workspace/coverage/default/17.clkmgr_alert_test.1068272302 Jan 24 04:16:01 PM PST 24 Jan 24 04:16:03 PM PST 24 38420510 ps
T796 /workspace/coverage/default/47.clkmgr_smoke.104139695 Jan 24 04:24:13 PM PST 24 Jan 24 04:24:17 PM PST 24 21675386 ps
T797 /workspace/coverage/default/3.clkmgr_peri.3687790581 Jan 24 04:11:42 PM PST 24 Jan 24 04:11:46 PM PST 24 12746372 ps
T798 /workspace/coverage/default/19.clkmgr_peri.173074317 Jan 24 04:16:18 PM PST 24 Jan 24 04:16:21 PM PST 24 17808477 ps
T799 /workspace/coverage/default/24.clkmgr_alert_test.4188136853 Jan 24 04:17:41 PM PST 24 Jan 24 04:17:47 PM PST 24 15566977 ps
T800 /workspace/coverage/default/15.clkmgr_div_intersig_mubi.984491724 Jan 24 04:15:24 PM PST 24 Jan 24 04:15:27 PM PST 24 13137660 ps
T801 /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1727503806 Jan 24 04:32:52 PM PST 24 Jan 24 04:32:53 PM PST 24 41482573 ps
T802 /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.939973409 Jan 24 04:20:30 PM PST 24 Jan 24 04:20:33 PM PST 24 24111994 ps
T803 /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1244310395 Jan 24 06:28:08 PM PST 24 Jan 24 06:28:09 PM PST 24 57925918 ps
T804 /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.597903144 Jan 24 04:23:07 PM PST 24 Jan 24 04:23:16 PM PST 24 21272505 ps
T805 /workspace/coverage/default/13.clkmgr_peri.1364918701 Jan 24 04:14:36 PM PST 24 Jan 24 04:14:38 PM PST 24 14411708 ps
T806 /workspace/coverage/default/14.clkmgr_frequency.779108727 Jan 24 04:15:02 PM PST 24 Jan 24 04:15:12 PM PST 24 1774971055 ps
T807 /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3909473403 Jan 24 04:23:06 PM PST 24 Jan 24 04:23:15 PM PST 24 23982530 ps
T808 /workspace/coverage/default/36.clkmgr_peri.4196774085 Jan 24 04:20:54 PM PST 24 Jan 24 04:20:55 PM PST 24 26053382 ps
T809 /workspace/coverage/default/49.clkmgr_smoke.2627659911 Jan 24 04:24:36 PM PST 24 Jan 24 04:24:39 PM PST 24 15857199 ps
T810 /workspace/coverage/default/41.clkmgr_peri.3836671826 Jan 24 04:22:17 PM PST 24 Jan 24 04:22:21 PM PST 24 14121373 ps
T811 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.4043899202 Jan 24 04:21:13 PM PST 24 Jan 24 04:21:16 PM PST 24 20135512 ps
T812 /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.841179421 Jan 24 04:23:08 PM PST 24 Jan 24 04:23:17 PM PST 24 36867016 ps
T813 /workspace/coverage/default/34.clkmgr_smoke.1975832938 Jan 24 04:20:06 PM PST 24 Jan 24 04:20:09 PM PST 24 48803027 ps
T814 /workspace/coverage/default/8.clkmgr_smoke.2393635435 Jan 24 04:13:10 PM PST 24 Jan 24 04:13:13 PM PST 24 157715440 ps
T815 /workspace/coverage/default/2.clkmgr_regwen.491819021 Jan 24 04:11:38 PM PST 24 Jan 24 04:11:43 PM PST 24 660399224 ps
T816 /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3059235801 Jan 24 05:46:08 PM PST 24 Jan 24 05:46:09 PM PST 24 63012397 ps
T817 /workspace/coverage/default/45.clkmgr_trans.2609571737 Jan 24 04:23:39 PM PST 24 Jan 24 04:23:42 PM PST 24 28086985 ps
T818 /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1269910287 Jan 24 04:18:18 PM PST 24 Jan 24 04:18:23 PM PST 24 61103583 ps
T819 /workspace/coverage/default/45.clkmgr_frequency.3630435988 Jan 24 04:23:44 PM PST 24 Jan 24 04:23:55 PM PST 24 1275107347 ps
T820 /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2064492204 Jan 24 04:21:57 PM PST 24 Jan 24 04:22:10 PM PST 24 17395045 ps
T821 /workspace/coverage/default/9.clkmgr_stress_all.3961430893 Jan 24 06:42:38 PM PST 24 Jan 24 06:42:59 PM PST 24 4111197096 ps
T822 /workspace/coverage/default/16.clkmgr_alert_test.591114844 Jan 24 04:15:40 PM PST 24 Jan 24 04:15:43 PM PST 24 80198277 ps
T823 /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2055081719 Jan 24 04:20:21 PM PST 24 Jan 24 04:20:23 PM PST 24 55504466 ps
T824 /workspace/coverage/default/40.clkmgr_frequency.560803450 Jan 24 04:34:04 PM PST 24 Jan 24 04:34:25 PM PST 24 2129808214 ps
T825 /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1052177999 Jan 24 04:13:22 PM PST 24 Jan 24 04:13:24 PM PST 24 92513906 ps
T826 /workspace/coverage/default/1.clkmgr_frequency.2758861604 Jan 24 04:24:49 PM PST 24 Jan 24 04:25:00 PM PST 24 2157547047 ps
T827 /workspace/coverage/default/25.clkmgr_trans.4051292373 Jan 24 04:17:51 PM PST 24 Jan 24 04:17:56 PM PST 24 42582617 ps
T828 /workspace/coverage/default/8.clkmgr_alert_test.2763307622 Jan 24 04:13:21 PM PST 24 Jan 24 04:13:24 PM PST 24 50950372 ps
T829 /workspace/coverage/default/0.clkmgr_clk_status.1594635227 Jan 24 04:10:42 PM PST 24 Jan 24 04:10:49 PM PST 24 41806670 ps
T830 /workspace/coverage/default/37.clkmgr_smoke.2074751111 Jan 24 04:21:00 PM PST 24 Jan 24 04:21:02 PM PST 24 16325890 ps
T831 /workspace/coverage/default/41.clkmgr_regwen.1029018833 Jan 24 04:22:38 PM PST 24 Jan 24 04:22:48 PM PST 24 1059679310 ps
T832 /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.665221611 Jan 24 04:19:42 PM PST 24 Jan 24 04:19:44 PM PST 24 72313016 ps
T833 /workspace/coverage/default/42.clkmgr_alert_test.3731846063 Jan 24 04:22:47 PM PST 24 Jan 24 04:22:54 PM PST 24 23252744 ps
T834 /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3185356670 Jan 24 05:30:58 PM PST 24 Jan 24 05:30:59 PM PST 24 28298679 ps
T835 /workspace/coverage/default/8.clkmgr_clk_status.2692098751 Jan 24 04:13:13 PM PST 24 Jan 24 04:13:16 PM PST 24 17486228 ps
T836 /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.218407000 Jan 24 04:23:09 PM PST 24 Jan 24 04:23:19 PM PST 24 64867017 ps
T837 /workspace/coverage/default/30.clkmgr_extclk.3760992249 Jan 24 04:19:05 PM PST 24 Jan 24 04:19:09 PM PST 24 36037374 ps
T838 /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1436962526 Jan 24 04:18:54 PM PST 24 Jan 24 04:19:03 PM PST 24 41146050 ps
T839 /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.867467230 Jan 24 04:15:12 PM PST 24 Jan 24 04:15:15 PM PST 24 32589010 ps
T840 /workspace/coverage/default/40.clkmgr_extclk.446653827 Jan 24 04:21:45 PM PST 24 Jan 24 04:22:00 PM PST 24 24442085 ps
T841 /workspace/coverage/default/10.clkmgr_alert_test.332416843 Jan 24 04:24:41 PM PST 24 Jan 24 04:24:43 PM PST 24 31921451 ps
T842 /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.4159324262 Jan 24 04:12:10 PM PST 24 Jan 24 04:12:17 PM PST 24 55978296 ps
T843 /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.99386358 Jan 24 04:17:21 PM PST 24 Jan 24 04:17:23 PM PST 24 18633252 ps
T844 /workspace/coverage/default/15.clkmgr_alert_test.2332759962 Jan 24 04:15:24 PM PST 24 Jan 24 04:15:27 PM PST 24 15660094 ps
T845 /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2378673148 Jan 24 04:14:38 PM PST 24 Jan 24 04:14:42 PM PST 24 44372238 ps
T846 /workspace/coverage/default/37.clkmgr_extclk.2413952215 Jan 24 04:21:01 PM PST 24 Jan 24 04:21:04 PM PST 24 72808629 ps
T847 /workspace/coverage/default/41.clkmgr_extclk.140415281 Jan 24 04:22:02 PM PST 24 Jan 24 04:22:13 PM PST 24 48405070 ps
T848 /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.565678092 Jan 24 04:14:20 PM PST 24 Jan 24 04:14:26 PM PST 24 29352778 ps
T849 /workspace/coverage/default/48.clkmgr_alert_test.431320905 Jan 24 04:24:35 PM PST 24 Jan 24 04:24:37 PM PST 24 15124010 ps
T850 /workspace/coverage/default/26.clkmgr_frequency.3806126909 Jan 24 04:17:59 PM PST 24 Jan 24 04:18:12 PM PST 24 2015133685 ps
T851 /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.844807127 Jan 24 04:21:39 PM PST 24 Jan 24 04:21:56 PM PST 24 76796320 ps
T852 /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3953489728 Jan 24 04:21:16 PM PST 24 Jan 24 04:21:26 PM PST 24 25489184 ps
T853 /workspace/coverage/default/0.clkmgr_frequency.26177887 Jan 24 04:10:44 PM PST 24 Jan 24 04:10:52 PM PST 24 730275221 ps
T854 /workspace/coverage/default/40.clkmgr_div_intersig_mubi.3885488693 Jan 24 04:22:01 PM PST 24 Jan 24 04:22:12 PM PST 24 41163392 ps
T855 /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.636348358 Jan 24 04:16:45 PM PST 24 Jan 24 04:16:48 PM PST 24 80664277 ps
T856 /workspace/coverage/default/32.clkmgr_peri.213058317 Jan 24 05:53:55 PM PST 24 Jan 24 05:53:56 PM PST 24 14701876 ps
T857 /workspace/coverage/default/7.clkmgr_smoke.4164942073 Jan 24 04:13:00 PM PST 24 Jan 24 04:13:03 PM PST 24 182361543 ps
T858 /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2616664925 Jan 24 04:26:53 PM PST 24 Jan 24 04:41:30 PM PST 24 46841318903 ps
T859 /workspace/coverage/default/43.clkmgr_stress_all.2516372298 Jan 24 04:23:03 PM PST 24 Jan 24 04:23:28 PM PST 24 2616055239 ps
T860 /workspace/coverage/default/8.clkmgr_frequency.712645605 Jan 24 04:13:14 PM PST 24 Jan 24 04:13:18 PM PST 24 500436093 ps
T861 /workspace/coverage/default/4.clkmgr_trans.697135540 Jan 24 04:12:11 PM PST 24 Jan 24 04:12:17 PM PST 24 28311093 ps
T862 /workspace/coverage/default/47.clkmgr_regwen.1480308805 Jan 24 04:24:13 PM PST 24 Jan 24 04:24:18 PM PST 24 394640481 ps
T863 /workspace/coverage/default/36.clkmgr_extclk.3215926787 Jan 24 04:20:42 PM PST 24 Jan 24 04:20:44 PM PST 24 23535174 ps
T864 /workspace/coverage/default/22.clkmgr_extclk.1124073445 Jan 24 04:16:55 PM PST 24 Jan 24 04:16:57 PM PST 24 33551444 ps
T865 /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3910479783 Jan 24 05:30:17 PM PST 24 Jan 24 05:30:19 PM PST 24 51153099 ps
T866 /workspace/coverage/default/44.clkmgr_frequency_timeout.1642302855 Jan 24 04:23:08 PM PST 24 Jan 24 04:23:23 PM PST 24 1099728397 ps
T867 /workspace/coverage/default/6.clkmgr_frequency.289331844 Jan 24 05:21:17 PM PST 24 Jan 24 05:21:24 PM PST 24 1464599944 ps
T868 /workspace/coverage/default/1.clkmgr_frequency_timeout.822016412 Jan 24 04:11:02 PM PST 24 Jan 24 04:11:26 PM PST 24 1575576805 ps
T869 /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3359429763 Jan 24 04:29:09 PM PST 24 Jan 24 04:29:11 PM PST 24 19162804 ps
T870 /workspace/coverage/default/29.clkmgr_regwen.72289348 Jan 24 04:18:55 PM PST 24 Jan 24 04:19:04 PM PST 24 163905463 ps
T871 /workspace/coverage/default/11.clkmgr_alert_test.1826881454 Jan 24 04:14:10 PM PST 24 Jan 24 04:14:19 PM PST 24 15593390 ps
T872 /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2608037708 Jan 24 04:17:40 PM PST 24 Jan 24 04:17:47 PM PST 24 69464798 ps
T873 /workspace/coverage/default/37.clkmgr_frequency.241544277 Jan 24 04:21:00 PM PST 24 Jan 24 04:21:15 PM PST 24 1757363878 ps
T874 /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3834753679 Jan 24 04:20:02 PM PST 24 Jan 24 04:33:42 PM PST 24 94944813105 ps
T875 /workspace/coverage/default/30.clkmgr_peri.4066903874 Jan 24 04:19:06 PM PST 24 Jan 24 04:19:09 PM PST 24 18376112 ps
T876 /workspace/coverage/default/43.clkmgr_extclk.2955362829 Jan 24 04:22:58 PM PST 24 Jan 24 04:23:07 PM PST 24 130611465 ps
T877 /workspace/coverage/default/20.clkmgr_peri.2465115957 Jan 24 04:26:47 PM PST 24 Jan 24 04:26:53 PM PST 24 74598100 ps
T878 /workspace/coverage/default/10.clkmgr_stress_all.1998856282 Jan 24 04:14:00 PM PST 24 Jan 24 04:14:33 PM PST 24 3756815845 ps
T879 /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3578285299 Jan 24 04:15:25 PM PST 24 Jan 24 04:15:28 PM PST 24 60633110 ps
T880 /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3044390492 Jan 24 04:15:47 PM PST 24 Jan 24 04:15:50 PM PST 24 83726734 ps
T881 /workspace/coverage/default/48.clkmgr_frequency.1048383752 Jan 24 04:43:14 PM PST 24 Jan 24 04:43:30 PM PST 24 1874883782 ps
T882 /workspace/coverage/default/3.clkmgr_trans.2890217192 Jan 24 04:11:41 PM PST 24 Jan 24 04:11:45 PM PST 24 15949084 ps
T883 /workspace/coverage/default/5.clkmgr_regwen.2347475769 Jan 24 05:56:04 PM PST 24 Jan 24 05:56:09 PM PST 24 894139645 ps
T884 /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1142275096 Jan 24 04:19:31 PM PST 24 Jan 24 04:19:33 PM PST 24 25267351 ps
T885 /workspace/coverage/default/25.clkmgr_smoke.3355046126 Jan 24 04:59:28 PM PST 24 Jan 24 04:59:30 PM PST 24 32055492 ps
T886 /workspace/coverage/default/13.clkmgr_trans.773133833 Jan 24 04:14:30 PM PST 24 Jan 24 04:14:33 PM PST 24 80802086 ps
T887 /workspace/coverage/default/15.clkmgr_trans.2753844890 Jan 24 04:15:23 PM PST 24 Jan 24 04:15:25 PM PST 24 24497369 ps
T888 /workspace/coverage/default/0.clkmgr_frequency_timeout.1663080246 Jan 24 04:10:48 PM PST 24 Jan 24 04:11:10 PM PST 24 144097711 ps
T889 /workspace/coverage/default/35.clkmgr_clk_status.464395069 Jan 24 04:20:36 PM PST 24 Jan 24 04:20:38 PM PST 24 36547474 ps
T890 /workspace/coverage/default/5.clkmgr_smoke.1201663786 Jan 24 04:12:19 PM PST 24 Jan 24 04:12:26 PM PST 24 56600962 ps
T891 /workspace/coverage/default/45.clkmgr_smoke.1392531113 Jan 24 04:23:29 PM PST 24 Jan 24 04:23:32 PM PST 24 75428195 ps
T892 /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.1721139730 Jan 24 04:21:57 PM PST 24 Jan 24 04:25:15 PM PST 24 26663832204 ps
T893 /workspace/coverage/default/21.clkmgr_regwen.3715074645 Jan 24 04:16:49 PM PST 24 Jan 24 04:16:54 PM PST 24 505517722 ps
T894 /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.3753250827 Jan 24 04:15:53 PM PST 24 Jan 24 04:22:54 PM PST 24 31421275588 ps
T895 /workspace/coverage/default/44.clkmgr_stress_all.3202411338 Jan 24 04:23:15 PM PST 24 Jan 24 04:23:36 PM PST 24 2431232475 ps
T896 /workspace/coverage/default/9.clkmgr_regwen.3208061413 Jan 24 04:13:33 PM PST 24 Jan 24 04:13:38 PM PST 24 462218030 ps
T897 /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3178703017 Jan 24 04:17:15 PM PST 24 Jan 24 04:17:16 PM PST 24 16397007 ps
T898 /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2002686601 Jan 24 04:34:44 PM PST 24 Jan 24 04:34:50 PM PST 24 16100770 ps
T899 /workspace/coverage/default/18.clkmgr_peri.2194110989 Jan 24 04:15:58 PM PST 24 Jan 24 04:16:00 PM PST 24 14734968 ps
T900 /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.4293235141 Jan 24 04:15:21 PM PST 24 Jan 24 04:15:23 PM PST 24 16747611 ps
T901 /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3755428195 Jan 24 04:17:21 PM PST 24 Jan 24 04:17:23 PM PST 24 67125832 ps
T902 /workspace/coverage/default/4.clkmgr_regwen.2022696047 Jan 24 04:12:22 PM PST 24 Jan 24 04:12:30 PM PST 24 628041149 ps
T903 /workspace/coverage/default/43.clkmgr_peri.2679053795 Jan 24 04:22:57 PM PST 24 Jan 24 04:23:01 PM PST 24 39907823 ps
T904 /workspace/coverage/default/43.clkmgr_smoke.1690650322 Jan 24 04:22:52 PM PST 24 Jan 24 04:22:57 PM PST 24 19337641 ps
T905 /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1691688062 Jan 24 04:16:23 PM PST 24 Jan 24 04:16:25 PM PST 24 21876000 ps
T906 /workspace/coverage/default/34.clkmgr_frequency_timeout.2422665273 Jan 24 04:20:04 PM PST 24 Jan 24 04:20:08 PM PST 24 513370960 ps
T907 /workspace/coverage/default/39.clkmgr_div_intersig_mubi.4219336736 Jan 24 04:21:46 PM PST 24 Jan 24 04:22:02 PM PST 24 29539715 ps
T908 /workspace/coverage/default/17.clkmgr_regwen.3032396289 Jan 24 04:15:48 PM PST 24 Jan 24 04:15:54 PM PST 24 974438630 ps
T909 /workspace/coverage/default/15.clkmgr_clk_status.1853627342 Jan 24 04:15:23 PM PST 24 Jan 24 04:15:25 PM PST 24 18773088 ps
T910 /workspace/coverage/default/21.clkmgr_trans.974442752 Jan 24 04:16:42 PM PST 24 Jan 24 04:16:45 PM PST 24 57182727 ps
T911 /workspace/coverage/default/31.clkmgr_peri.763756077 Jan 24 04:19:32 PM PST 24 Jan 24 04:19:33 PM PST 24 14722884 ps
T912 /workspace/coverage/default/3.clkmgr_frequency.2505410991 Jan 24 04:20:45 PM PST 24 Jan 24 04:20:54 PM PST 24 1406954669 ps
T913 /workspace/coverage/default/4.clkmgr_frequency_timeout.907758315 Jan 24 04:12:11 PM PST 24 Jan 24 04:12:20 PM PST 24 1310457048 ps
T914 /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1443146500 Jan 24 04:14:15 PM PST 24 Jan 24 04:14:22 PM PST 24 36612277 ps
T915 /workspace/coverage/default/12.clkmgr_div_intersig_mubi.40624104 Jan 24 04:14:29 PM PST 24 Jan 24 04:14:32 PM PST 24 25273075 ps
T916 /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3016431769 Jan 24 04:23:09 PM PST 24 Jan 24 04:23:19 PM PST 24 43162125 ps
T917 /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.1945346616 Jan 24 04:38:01 PM PST 24 Jan 24 05:00:57 PM PST 24 201967567386 ps
T918 /workspace/coverage/default/37.clkmgr_regwen.2708679534 Jan 24 04:21:11 PM PST 24 Jan 24 04:21:15 PM PST 24 542329331 ps
T919 /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2661695599 Jan 24 04:24:43 PM PST 24 Jan 24 04:24:47 PM PST 24 63636053 ps
T920 /workspace/coverage/default/43.clkmgr_alert_test.3543694115 Jan 24 04:23:11 PM PST 24 Jan 24 04:23:21 PM PST 24 72051370 ps
T921 /workspace/coverage/default/18.clkmgr_frequency_timeout.1137489900 Jan 24 04:15:59 PM PST 24 Jan 24 04:16:10 PM PST 24 1937676423 ps
T922 /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.722779971 Jan 24 04:21:23 PM PST 24 Jan 24 04:21:38 PM PST 24 32527152 ps
T923 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2700474931 Jan 24 04:15:47 PM PST 24 Jan 24 04:15:49 PM PST 24 19694277 ps
T924 /workspace/coverage/default/11.clkmgr_peri.2912700334 Jan 24 04:14:15 PM PST 24 Jan 24 04:14:20 PM PST 24 25677414 ps
T925 /workspace/coverage/default/30.clkmgr_clk_status.3210348918 Jan 24 04:19:07 PM PST 24 Jan 24 04:19:10 PM PST 24 47975142 ps
T926 /workspace/coverage/default/5.clkmgr_extclk.2622528262 Jan 24 04:12:27 PM PST 24 Jan 24 04:12:30 PM PST 24 20469019 ps
T927 /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3627834622 Jan 24 04:12:33 PM PST 24 Jan 24 04:12:35 PM PST 24 26988313 ps
T928 /workspace/coverage/default/43.clkmgr_trans.698083570 Jan 24 04:22:57 PM PST 24 Jan 24 04:23:05 PM PST 24 59085463 ps
T929 /workspace/coverage/default/31.clkmgr_smoke.468179182 Jan 24 04:19:15 PM PST 24 Jan 24 04:19:17 PM PST 24 96880141 ps
T930 /workspace/coverage/default/14.clkmgr_peri.3549656357 Jan 24 04:14:57 PM PST 24 Jan 24 04:14:59 PM PST 24 30310586 ps
T931 /workspace/coverage/default/29.clkmgr_trans.3876148249 Jan 24 04:18:53 PM PST 24 Jan 24 04:19:00 PM PST 24 22723123 ps
T932 /workspace/coverage/default/34.clkmgr_clk_status.920465732 Jan 24 04:20:19 PM PST 24 Jan 24 04:20:21 PM PST 24 33858788 ps
T933 /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1516622074 Jan 24 04:22:26 PM PST 24 Jan 24 04:22:28 PM PST 24 27885582 ps
T934 /workspace/coverage/default/19.clkmgr_extclk.1599200240 Jan 24 04:16:10 PM PST 24 Jan 24 04:16:13 PM PST 24 30552174 ps
T935 /workspace/coverage/default/19.clkmgr_frequency.3440985914 Jan 24 04:16:18 PM PST 24 Jan 24 04:16:33 PM PST 24 2482212487 ps
T936 /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.720296139 Jan 24 04:19:56 PM PST 24 Jan 24 04:19:58 PM PST 24 23468760 ps
T937 /workspace/coverage/default/40.clkmgr_frequency_timeout.3867812336 Jan 24 04:21:57 PM PST 24 Jan 24 04:22:11 PM PST 24 259867495 ps
T938 /workspace/coverage/default/5.clkmgr_frequency.2273095348 Jan 24 04:12:19 PM PST 24 Jan 24 04:12:38 PM PST 24 2251337452 ps
T939 /workspace/coverage/default/30.clkmgr_smoke.253152435 Jan 24 04:19:06 PM PST 24 Jan 24 04:19:09 PM PST 24 21962567 ps
T940 /workspace/coverage/default/48.clkmgr_stress_all.1202260169 Jan 24 04:24:36 PM PST 24 Jan 24 04:24:58 PM PST 24 4749254149 ps
T941 /workspace/coverage/default/32.clkmgr_frequency_timeout.3092525319 Jan 24 04:19:40 PM PST 24 Jan 24 04:19:43 PM PST 24 257704703 ps
T942 /workspace/coverage/default/27.clkmgr_stress_all.1432144392 Jan 24 04:18:33 PM PST 24 Jan 24 04:19:11 PM PST 24 4777968682 ps
T943 /workspace/coverage/default/27.clkmgr_trans.336113665 Jan 24 04:18:15 PM PST 24 Jan 24 04:18:20 PM PST 24 22910355 ps
T944 /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3464083153 Jan 24 04:23:52 PM PST 24 Jan 24 04:23:54 PM PST 24 28947009 ps
T945 /workspace/coverage/default/39.clkmgr_extclk.1472201279 Jan 24 04:21:32 PM PST 24 Jan 24 04:21:48 PM PST 24 18906835 ps
T946 /workspace/coverage/default/20.clkmgr_alert_test.3130687442 Jan 24 04:16:42 PM PST 24 Jan 24 04:16:44 PM PST 24 12463630 ps
T947 /workspace/coverage/default/16.clkmgr_extclk.4108956347 Jan 24 04:15:25 PM PST 24 Jan 24 04:15:28 PM PST 24 13654721 ps
T948 /workspace/coverage/default/18.clkmgr_extclk.1075476793 Jan 24 04:16:00 PM PST 24 Jan 24 04:16:03 PM PST 24 23464525 ps
T949 /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1795965543 Jan 24 04:16:25 PM PST 24 Jan 24 04:16:27 PM PST 24 12925813 ps
T950 /workspace/coverage/default/35.clkmgr_regwen.3215823756 Jan 24 04:20:34 PM PST 24 Jan 24 04:20:39 PM PST 24 797148108 ps
T951 /workspace/coverage/default/28.clkmgr_trans.3817903582 Jan 24 05:16:11 PM PST 24 Jan 24 05:16:13 PM PST 24 23536314 ps
T952 /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1697040983 Jan 24 04:58:08 PM PST 24 Jan 24 04:58:13 PM PST 24 77668578 ps
T953 /workspace/coverage/default/27.clkmgr_clk_status.3221856364 Jan 24 04:32:47 PM PST 24 Jan 24 04:32:49 PM PST 24 43120617 ps
T954 /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.229326791 Jan 24 04:24:28 PM PST 24 Jan 24 04:24:31 PM PST 24 21194953 ps
T955 /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2098946279 Jan 24 04:14:19 PM PST 24 Jan 24 04:14:26 PM PST 24 67267811 ps
T956 /workspace/coverage/default/48.clkmgr_peri.1073003424 Jan 24 04:24:13 PM PST 24 Jan 24 04:24:16 PM PST 24 52271295 ps
T957 /workspace/coverage/default/46.clkmgr_stress_all.3130002409 Jan 24 04:24:12 PM PST 24 Jan 24 04:24:24 PM PST 24 1955067730 ps
T958 /workspace/coverage/default/1.clkmgr_stress_all.409334176 Jan 24 04:11:24 PM PST 24 Jan 24 04:11:49 PM PST 24 3079733818 ps
T959 /workspace/coverage/default/8.clkmgr_frequency_timeout.3682957559 Jan 24 04:13:15 PM PST 24 Jan 24 04:13:34 PM PST 24 2417385962 ps
T960 /workspace/coverage/default/13.clkmgr_frequency.673078904 Jan 24 04:14:34 PM PST 24 Jan 24 04:14:55 PM PST 24 2475071329 ps
T961 /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.845094439 Jan 24 04:35:03 PM PST 24 Jan 24 04:35:09 PM PST 24 17756848 ps
T962 /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1918352236 Jan 24 04:24:41 PM PST 24 Jan 24 04:24:44 PM PST 24 52329142 ps
T963 /workspace/coverage/default/38.clkmgr_extclk.3458787352 Jan 24 04:21:22 PM PST 24 Jan 24 04:21:38 PM PST 24 55393730 ps
T964 /workspace/coverage/default/19.clkmgr_clk_status.1510860218 Jan 24 04:16:23 PM PST 24 Jan 24 04:16:25 PM PST 24 15331229 ps
T965 /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.188068931 Jan 24 04:14:12 PM PST 24 Jan 24 04:37:29 PM PST 24 235200795307 ps
T966 /workspace/coverage/default/26.clkmgr_stress_all.279914818 Jan 24 04:18:10 PM PST 24 Jan 24 04:18:46 PM PST 24 7052774580 ps
T967 /workspace/coverage/default/33.clkmgr_regwen.2027455764 Jan 24 04:20:02 PM PST 24 Jan 24 04:20:07 PM PST 24 538450424 ps
T968 /workspace/coverage/default/10.clkmgr_regwen.3057671003 Jan 24 04:14:05 PM PST 24 Jan 24 04:14:18 PM PST 24 832363519 ps
T969 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3126244897 Jan 24 02:03:50 PM PST 24 Jan 24 02:04:34 PM PST 24 15547284 ps
T970 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2484219931 Jan 24 02:01:45 PM PST 24 Jan 24 02:01:58 PM PST 24 51866784 ps
T971 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1958547448 Jan 24 02:04:13 PM PST 24 Jan 24 02:05:02 PM PST 24 29069941 ps
T972 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3458505239 Jan 24 02:01:48 PM PST 24 Jan 24 02:02:02 PM PST 24 25338185 ps
T973 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.439008931 Jan 24 02:00:37 PM PST 24 Jan 24 02:00:44 PM PST 24 370444804 ps
T974 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2906301680 Jan 24 02:01:47 PM PST 24 Jan 24 02:01:57 PM PST 24 13741062 ps
T975 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3773513600 Jan 24 02:02:19 PM PST 24 Jan 24 02:02:37 PM PST 24 65605081 ps
T976 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1592538347 Jan 24 02:16:26 PM PST 24 Jan 24 02:17:00 PM PST 24 194250563 ps
T977 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1926648941 Jan 24 02:03:41 PM PST 24 Jan 24 02:04:44 PM PST 24 43193491 ps
T978 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2808918648 Jan 24 02:02:40 PM PST 24 Jan 24 02:02:54 PM PST 24 15580776 ps
T979 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2938260095 Jan 24 02:04:09 PM PST 24 Jan 24 02:04:59 PM PST 24 40360925 ps
T94 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1438151184 Jan 24 02:02:39 PM PST 24 Jan 24 02:02:58 PM PST 24 847786958 ps
T980 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.733099211 Jan 24 02:23:09 PM PST 24 Jan 24 02:23:33 PM PST 24 119450526 ps
T981 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1456602818 Jan 24 02:03:49 PM PST 24 Jan 24 02:04:31 PM PST 24 13847983 ps
T982 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3171689862 Jan 24 02:00:22 PM PST 24 Jan 24 02:00:28 PM PST 24 147720408 ps
T983 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2773408628 Jan 24 02:02:32 PM PST 24 Jan 24 02:02:47 PM PST 24 122396967 ps
T984 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2573561961 Jan 24 02:02:45 PM PST 24 Jan 24 02:02:58 PM PST 24 156165448 ps

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3538205333
Short name T5
Test name
Test status
Simulation time 28041612 ps
CPU time 0.85 seconds
Started Jan 24 02:01:25 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 201016 kb
Host smart-45046397-9991-44bd-ac22-72f25daa3bbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538205333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.3538205333
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2873713256
Short name T2
Test name
Test status
Simulation time 132096811240 ps
CPU time 903.15 seconds
Started Jan 24 04:23:39 PM PST 24
Finished Jan 24 04:38:43 PM PST 24
Peak memory 215208 kb
Host smart-09f0727f-f1ef-4a68-8158-80b5b3684e37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2873713256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2873713256
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.338765356
Short name T70
Test name
Test status
Simulation time 423782719 ps
CPU time 3.6 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:59 PM PST 24
Peak memory 209768 kb
Host smart-abdfeb9e-7939-440f-80a7-3a267ebfbf69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338765356 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.338765356
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2279446615
Short name T66
Test name
Test status
Simulation time 96908401 ps
CPU time 3.05 seconds
Started Jan 24 02:00:37 PM PST 24
Finished Jan 24 02:00:43 PM PST 24
Peak memory 201184 kb
Host smart-17385de9-c88d-4b8d-9f98-da39b5845e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279446615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2279446615
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3994426501
Short name T3
Test name
Test status
Simulation time 2614173396 ps
CPU time 14.37 seconds
Started Jan 24 04:51:10 PM PST 24
Finished Jan 24 04:51:27 PM PST 24
Peak memory 201752 kb
Host smart-0b99c940-6411-4410-9d53-cc81f3de17ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994426501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3994426501
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3391767173
Short name T69
Test name
Test status
Simulation time 139895299 ps
CPU time 1.98 seconds
Started Jan 24 02:00:40 PM PST 24
Finished Jan 24 02:00:45 PM PST 24
Peak memory 217944 kb
Host smart-4dce347b-af9d-4715-bf93-e8712cfde95c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391767173 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3391767173
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3317811136
Short name T35
Test name
Test status
Simulation time 128280557 ps
CPU time 1.89 seconds
Started Jan 24 02:18:25 PM PST 24
Finished Jan 24 02:18:44 PM PST 24
Peak memory 201244 kb
Host smart-0f572ed9-1f76-43db-b687-223cd7a847bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317811136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3317811136
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.3066292571
Short name T47
Test name
Test status
Simulation time 17339447 ps
CPU time 0.73 seconds
Started Jan 24 04:11:05 PM PST 24
Finished Jan 24 04:11:17 PM PST 24
Peak memory 200144 kb
Host smart-892ec0da-81ef-48b3-a4ca-2691573862fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066292571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3066292571
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.87334892
Short name T52
Test name
Test status
Simulation time 224692976 ps
CPU time 2.11 seconds
Started Jan 24 04:11:59 PM PST 24
Finished Jan 24 04:12:03 PM PST 24
Peak memory 216036 kb
Host smart-ba80547a-c191-4d11-be07-8b1f2e115faf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87334892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_
sec_cm.87334892
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2751692433
Short name T285
Test name
Test status
Simulation time 52475282 ps
CPU time 0.99 seconds
Started Jan 24 04:14:29 PM PST 24
Finished Jan 24 04:14:32 PM PST 24
Peak memory 201284 kb
Host smart-d2775ee5-6c70-4a81-9acc-f615f47224cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751692433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.2751692433
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.4042304155
Short name T274
Test name
Test status
Simulation time 430093287 ps
CPU time 2.81 seconds
Started Jan 24 04:24:34 PM PST 24
Finished Jan 24 04:24:38 PM PST 24
Peak memory 201236 kb
Host smart-e9aaede9-31b9-4451-a30e-564ae4b4c4ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042304155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.4042304155
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.2386663314
Short name T151
Test name
Test status
Simulation time 287944979455 ps
CPU time 1340.38 seconds
Started Jan 24 04:14:49 PM PST 24
Finished Jan 24 04:37:11 PM PST 24
Peak memory 210012 kb
Host smart-ff5f6e60-d402-4cd0-8fee-e02ddf20cc42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2386663314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2386663314
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.235262932
Short name T158
Test name
Test status
Simulation time 98166633 ps
CPU time 1.36 seconds
Started Jan 24 02:02:17 PM PST 24
Finished Jan 24 02:02:36 PM PST 24
Peak memory 200980 kb
Host smart-3a859d42-9e2c-4cb2-ae6d-d6b245979346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235262932 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.235262932
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1438151184
Short name T94
Test name
Test status
Simulation time 847786958 ps
CPU time 4.39 seconds
Started Jan 24 02:02:39 PM PST 24
Finished Jan 24 02:02:58 PM PST 24
Peak memory 201136 kb
Host smart-7fb03f50-1e0e-426d-bf98-4352b26cf7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438151184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1438151184
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.597634950
Short name T49
Test name
Test status
Simulation time 38496774 ps
CPU time 1.3 seconds
Started Jan 24 02:00:02 PM PST 24
Finished Jan 24 02:00:08 PM PST 24
Peak memory 200960 kb
Host smart-e037a28c-142a-4b32-88f7-71a948c9a9b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597634950 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.597634950
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2279842519
Short name T113
Test name
Test status
Simulation time 181430639 ps
CPU time 2.15 seconds
Started Jan 24 02:02:16 PM PST 24
Finished Jan 24 02:02:36 PM PST 24
Peak memory 201592 kb
Host smart-9cb2508a-a868-4bf9-abbc-4d14140f39d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279842519 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2279842519
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.1564578151
Short name T8
Test name
Test status
Simulation time 792055577 ps
CPU time 4.51 seconds
Started Jan 24 04:28:35 PM PST 24
Finished Jan 24 04:28:41 PM PST 24
Peak memory 201440 kb
Host smart-edf3de92-75bf-48d1-a1cb-0feab5f06178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564578151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1564578151
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3935307193
Short name T120
Test name
Test status
Simulation time 54387924 ps
CPU time 1.26 seconds
Started Jan 24 02:01:49 PM PST 24
Finished Jan 24 02:02:05 PM PST 24
Peak memory 201408 kb
Host smart-bae9eaeb-96ee-4a2d-9d4f-5bf9e0d3b3fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935307193 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.3935307193
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2532275433
Short name T281
Test name
Test status
Simulation time 21542443 ps
CPU time 0.86 seconds
Started Jan 24 04:11:01 PM PST 24
Finished Jan 24 04:11:15 PM PST 24
Peak memory 201336 kb
Host smart-2efa24bb-3990-4f7b-b0d9-cceda308f5dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532275433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2532275433
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.684006094
Short name T303
Test name
Test status
Simulation time 32028397 ps
CPU time 0.85 seconds
Started Jan 24 04:11:06 PM PST 24
Finished Jan 24 04:11:19 PM PST 24
Peak memory 201264 kb
Host smart-02af641d-924c-48f4-9eea-1e0e2ceaf964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684006094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.684006094
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.4096901927
Short name T96
Test name
Test status
Simulation time 128102325 ps
CPU time 2.71 seconds
Started Jan 24 02:03:06 PM PST 24
Finished Jan 24 02:03:22 PM PST 24
Peak memory 201052 kb
Host smart-a0e224da-3930-492d-a5b0-d7bacd8ba4ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096901927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.4096901927
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.4235898599
Short name T122
Test name
Test status
Simulation time 235570637 ps
CPU time 3.2 seconds
Started Jan 24 02:14:47 PM PST 24
Finished Jan 24 02:15:09 PM PST 24
Peak memory 217916 kb
Host smart-223d6098-fd74-4a89-871c-26a0810c89c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235898599 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.4235898599
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.1578561278
Short name T10
Test name
Test status
Simulation time 14857492698 ps
CPU time 214.77 seconds
Started Jan 24 04:11:23 PM PST 24
Finished Jan 24 04:15:00 PM PST 24
Peak memory 210052 kb
Host smart-5582826a-3f6f-4e0a-8e3e-67bb8daed527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1578561278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1578561278
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2632692522
Short name T98
Test name
Test status
Simulation time 164343174 ps
CPU time 1.92 seconds
Started Jan 24 02:01:09 PM PST 24
Finished Jan 24 02:01:15 PM PST 24
Peak memory 201176 kb
Host smart-aa971066-34f6-4b12-b03c-84ea02606c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632692522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.2632692522
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1785861649
Short name T77
Test name
Test status
Simulation time 433054931 ps
CPU time 3.14 seconds
Started Jan 24 02:02:17 PM PST 24
Finished Jan 24 02:02:38 PM PST 24
Peak memory 201196 kb
Host smart-55194a4d-b5ca-4afa-8d88-b90a47c77861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785861649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1785861649
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2424324650
Short name T89
Test name
Test status
Simulation time 72895853 ps
CPU time 1.92 seconds
Started Jan 24 02:00:02 PM PST 24
Finished Jan 24 02:00:08 PM PST 24
Peak memory 201176 kb
Host smart-27064d19-fed0-4c31-97a4-cdf920c1b07e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424324650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.2424324650
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3071783623
Short name T266
Test name
Test status
Simulation time 280624218 ps
CPU time 4.58 seconds
Started Jan 24 02:41:46 PM PST 24
Finished Jan 24 02:41:58 PM PST 24
Peak memory 201028 kb
Host smart-ab5f2a5c-5e5d-4845-957a-a8dbab999485
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071783623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.3071783623
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1072195057
Short name T199
Test name
Test status
Simulation time 19230011 ps
CPU time 0.79 seconds
Started Jan 24 02:28:00 PM PST 24
Finished Jan 24 02:28:19 PM PST 24
Peak memory 200948 kb
Host smart-d621bb13-6aa2-4c64-aff8-9e20d9e4921c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072195057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1072195057
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1701414586
Short name T197
Test name
Test status
Simulation time 40319748 ps
CPU time 1.16 seconds
Started Jan 24 01:59:59 PM PST 24
Finished Jan 24 02:00:05 PM PST 24
Peak memory 200900 kb
Host smart-56790233-b080-4931-b853-a0700688df7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701414586 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1701414586
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2778708915
Short name T171
Test name
Test status
Simulation time 15165589 ps
CPU time 0.78 seconds
Started Jan 24 02:15:07 PM PST 24
Finished Jan 24 02:15:46 PM PST 24
Peak memory 200960 kb
Host smart-1cbafc46-7c77-4608-afee-e2869ee3d208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778708915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2778708915
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3323794809
Short name T121
Test name
Test status
Simulation time 38348684 ps
CPU time 0.77 seconds
Started Jan 24 01:59:57 PM PST 24
Finished Jan 24 01:59:59 PM PST 24
Peak memory 199184 kb
Host smart-e4f099e6-1d76-4e5f-8fdd-1d13afb9df8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323794809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.3323794809
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4138918637
Short name T204
Test name
Test status
Simulation time 136978344 ps
CPU time 2.05 seconds
Started Jan 24 01:59:40 PM PST 24
Finished Jan 24 01:59:44 PM PST 24
Peak memory 201556 kb
Host smart-e3f16d0c-4fa8-47d4-bddb-381e87203144
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138918637 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.4138918637
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1379149001
Short name T74
Test name
Test status
Simulation time 271262885 ps
CPU time 3.26 seconds
Started Jan 24 01:59:40 PM PST 24
Finished Jan 24 01:59:45 PM PST 24
Peak memory 209660 kb
Host smart-3921e13a-586b-4121-a0c2-30393433f9ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379149001 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.1379149001
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1362702699
Short name T261
Test name
Test status
Simulation time 319428470 ps
CPU time 3.2 seconds
Started Jan 24 01:59:39 PM PST 24
Finished Jan 24 01:59:44 PM PST 24
Peak memory 201096 kb
Host smart-50aa0091-4b5d-471a-98c8-132b405cd70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362702699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1362702699
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3316251646
Short name T207
Test name
Test status
Simulation time 40135099 ps
CPU time 1.28 seconds
Started Jan 24 02:00:23 PM PST 24
Finished Jan 24 02:00:27 PM PST 24
Peak memory 201040 kb
Host smart-9e96199a-228d-4267-ad56-6048f69607c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316251646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.3316251646
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1752225390
Short name T90
Test name
Test status
Simulation time 2185553269 ps
CPU time 13.05 seconds
Started Jan 24 02:00:07 PM PST 24
Finished Jan 24 02:00:24 PM PST 24
Peak memory 201308 kb
Host smart-806631b3-30e8-4158-8e2a-f34b941fa3e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752225390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.1752225390
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3883305485
Short name T215
Test name
Test status
Simulation time 117107413 ps
CPU time 1.08 seconds
Started Jan 24 02:00:11 PM PST 24
Finished Jan 24 02:00:19 PM PST 24
Peak memory 200992 kb
Host smart-b678cb13-a53a-47f5-8ede-e9395768c44c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883305485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.3883305485
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4047672939
Short name T194
Test name
Test status
Simulation time 30997470 ps
CPU time 1.08 seconds
Started Jan 24 02:00:27 PM PST 24
Finished Jan 24 02:00:30 PM PST 24
Peak memory 200984 kb
Host smart-55b33970-6d2b-42c3-ba83-f3ae468e3d48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047672939 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.4047672939
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3989180890
Short name T253
Test name
Test status
Simulation time 31269696 ps
CPU time 0.88 seconds
Started Jan 24 02:00:06 PM PST 24
Finished Jan 24 02:00:11 PM PST 24
Peak memory 200920 kb
Host smart-b86485e2-7b6a-4f85-b3b7-03b6cd49adef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989180890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.3989180890
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2882759088
Short name T185
Test name
Test status
Simulation time 19682306 ps
CPU time 0.69 seconds
Started Jan 24 02:00:06 PM PST 24
Finished Jan 24 02:00:11 PM PST 24
Peak memory 199224 kb
Host smart-0351a62b-f0a1-42a3-8107-682796e45f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882759088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2882759088
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3431522411
Short name T48
Test name
Test status
Simulation time 35703774 ps
CPU time 1.01 seconds
Started Jan 24 02:00:22 PM PST 24
Finished Jan 24 02:00:27 PM PST 24
Peak memory 200984 kb
Host smart-53e619de-5b4e-4b76-8665-cac85a855534
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431522411 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.3431522411
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.254193703
Short name T208
Test name
Test status
Simulation time 107501419 ps
CPU time 1.57 seconds
Started Jan 24 04:03:54 PM PST 24
Finished Jan 24 04:03:59 PM PST 24
Peak memory 201404 kb
Host smart-c8433cba-dc16-489d-be97-3f8fcc97f7a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254193703 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.clkmgr_shadow_reg_errors.254193703
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3294222029
Short name T241
Test name
Test status
Simulation time 412267418 ps
CPU time 3.63 seconds
Started Jan 24 02:00:05 PM PST 24
Finished Jan 24 02:00:13 PM PST 24
Peak memory 201104 kb
Host smart-f4aafce2-0232-42ac-968e-5a221ea1812b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294222029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3294222029
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3542104620
Short name T272
Test name
Test status
Simulation time 337965656 ps
CPU time 2.6 seconds
Started Jan 24 02:00:05 PM PST 24
Finished Jan 24 02:00:12 PM PST 24
Peak memory 201104 kb
Host smart-0445db0f-a040-49e8-bf02-02330a8d6ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542104620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3542104620
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3773513600
Short name T975
Test name
Test status
Simulation time 65605081 ps
CPU time 0.96 seconds
Started Jan 24 02:02:19 PM PST 24
Finished Jan 24 02:02:37 PM PST 24
Peak memory 200864 kb
Host smart-4fb4854d-b1de-44ad-9b81-feb900e17f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773513600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3773513600
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1284837838
Short name T184
Test name
Test status
Simulation time 14021281 ps
CPU time 0.68 seconds
Started Jan 24 02:02:18 PM PST 24
Finished Jan 24 02:02:36 PM PST 24
Peak memory 199228 kb
Host smart-35987c4b-38de-46e2-abe8-680809583d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284837838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1284837838
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.629731384
Short name T262
Test name
Test status
Simulation time 550746273 ps
CPU time 2.22 seconds
Started Jan 24 02:02:20 PM PST 24
Finished Jan 24 02:02:39 PM PST 24
Peak memory 200876 kb
Host smart-aa20e260-6607-485a-887b-34dd8f472b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629731384 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.629731384
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1555258709
Short name T127
Test name
Test status
Simulation time 188904239 ps
CPU time 1.84 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:05 PM PST 24
Peak memory 201496 kb
Host smart-be8a1379-cfce-4d23-b7de-8bedd5320a60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555258709 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1555258709
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.76842060
Short name T227
Test name
Test status
Simulation time 66364016 ps
CPU time 1.82 seconds
Started Jan 24 02:01:49 PM PST 24
Finished Jan 24 02:02:06 PM PST 24
Peak memory 201620 kb
Host smart-bd6be000-1169-4aac-b506-5cc7e6e4e2ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76842060 -assert nopostproc +UVM_TESTNAME=
clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.76842060
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1747440841
Short name T252
Test name
Test status
Simulation time 174610477 ps
CPU time 2.21 seconds
Started Jan 24 02:02:18 PM PST 24
Finished Jan 24 02:02:38 PM PST 24
Peak memory 201176 kb
Host smart-2b054a81-dab7-4a9b-80fe-1a2264fe6d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747440841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.1747440841
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1806675680
Short name T84
Test name
Test status
Simulation time 212727023 ps
CPU time 2.62 seconds
Started Jan 24 02:02:18 PM PST 24
Finished Jan 24 02:02:38 PM PST 24
Peak memory 201080 kb
Host smart-bb46224d-d5af-4bed-90b8-cbf9e3eecc8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806675680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1806675680
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2892535784
Short name T264
Test name
Test status
Simulation time 22028742 ps
CPU time 0.87 seconds
Started Jan 24 02:02:40 PM PST 24
Finished Jan 24 02:02:55 PM PST 24
Peak memory 200896 kb
Host smart-7adfe66b-a90c-46dd-8abc-372b617b57c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892535784 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.2892535784
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1860618358
Short name T214
Test name
Test status
Simulation time 32416603 ps
CPU time 0.81 seconds
Started Jan 24 02:02:30 PM PST 24
Finished Jan 24 02:02:43 PM PST 24
Peak memory 200396 kb
Host smart-93b7f87d-3039-43e8-9d8b-74801041254a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860618358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.1860618358
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1351383051
Short name T217
Test name
Test status
Simulation time 80814113 ps
CPU time 1.49 seconds
Started Jan 24 02:02:34 PM PST 24
Finished Jan 24 02:02:51 PM PST 24
Peak memory 201108 kb
Host smart-d8ca018e-fa2b-47ae-bad6-78b4fffb40d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351383051 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.1351383051
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.671635295
Short name T222
Test name
Test status
Simulation time 99025420 ps
CPU time 1.87 seconds
Started Jan 24 02:02:18 PM PST 24
Finished Jan 24 02:02:37 PM PST 24
Peak memory 209680 kb
Host smart-532c1068-daf4-4373-a9f3-029b14a37fb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671635295 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.671635295
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2226058960
Short name T76
Test name
Test status
Simulation time 424764310 ps
CPU time 2.68 seconds
Started Jan 24 02:02:16 PM PST 24
Finished Jan 24 02:02:37 PM PST 24
Peak memory 201264 kb
Host smart-7d4ad61e-d4d6-459e-8f7e-71f22a272a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226058960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.2226058960
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2808918648
Short name T978
Test name
Test status
Simulation time 15580776 ps
CPU time 0.79 seconds
Started Jan 24 02:02:40 PM PST 24
Finished Jan 24 02:02:54 PM PST 24
Peak memory 200872 kb
Host smart-d1783c9d-fbc1-4ce1-bd06-1f73fdd44f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808918648 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.2808918648
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2415114337
Short name T86
Test name
Test status
Simulation time 19899404 ps
CPU time 0.88 seconds
Started Jan 24 02:02:33 PM PST 24
Finished Jan 24 02:02:50 PM PST 24
Peak memory 200944 kb
Host smart-80dd0413-da62-4e89-a050-2472d902d3d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415114337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2415114337
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2337172317
Short name T238
Test name
Test status
Simulation time 32392433 ps
CPU time 0.8 seconds
Started Jan 24 02:02:39 PM PST 24
Finished Jan 24 02:02:54 PM PST 24
Peak memory 199212 kb
Host smart-5100e9eb-ad6d-47df-9c79-794cd9e2fb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337172317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.2337172317
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2905279449
Short name T181
Test name
Test status
Simulation time 28042585 ps
CPU time 1.07 seconds
Started Jan 24 02:02:31 PM PST 24
Finished Jan 24 02:02:46 PM PST 24
Peak memory 200984 kb
Host smart-60f2aa76-8fd2-416d-b760-0d9137d7a835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905279449 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.2905279449
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2835830041
Short name T112
Test name
Test status
Simulation time 208038733 ps
CPU time 2.09 seconds
Started Jan 24 02:19:33 PM PST 24
Finished Jan 24 02:19:42 PM PST 24
Peak memory 201564 kb
Host smart-2af92148-9a22-4c03-8ddb-7ae9f9df02c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835830041 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2835830041
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1609334568
Short name T206
Test name
Test status
Simulation time 65788250 ps
CPU time 1.79 seconds
Started Jan 24 02:33:19 PM PST 24
Finished Jan 24 02:33:46 PM PST 24
Peak memory 201696 kb
Host smart-b4b6cc03-57f5-4080-bda9-ec81189e3cbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609334568 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1609334568
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3633812001
Short name T196
Test name
Test status
Simulation time 81039309 ps
CPU time 2.94 seconds
Started Jan 24 02:02:33 PM PST 24
Finished Jan 24 02:02:51 PM PST 24
Peak memory 201192 kb
Host smart-d3d9b14b-712c-4e10-90a9-c709cf41d92f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633812001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3633812001
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3281731679
Short name T156
Test name
Test status
Simulation time 24671443 ps
CPU time 1.05 seconds
Started Jan 24 02:02:46 PM PST 24
Finished Jan 24 02:02:57 PM PST 24
Peak memory 201092 kb
Host smart-430045b3-e0ac-4846-9c54-6eb5c6101062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281731679 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3281731679
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3886466337
Short name T176
Test name
Test status
Simulation time 16358092 ps
CPU time 0.8 seconds
Started Jan 24 02:02:47 PM PST 24
Finished Jan 24 02:02:57 PM PST 24
Peak memory 200960 kb
Host smart-ef18a0ae-716c-40fd-900c-3061f8fed25e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886466337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.3886466337
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2193558397
Short name T183
Test name
Test status
Simulation time 25511524 ps
CPU time 0.72 seconds
Started Jan 24 02:02:46 PM PST 24
Finished Jan 24 02:02:57 PM PST 24
Peak memory 199116 kb
Host smart-ed439a13-da3c-49a7-8c70-a1c13a073964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193558397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2193558397
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2573561961
Short name T984
Test name
Test status
Simulation time 156165448 ps
CPU time 1.61 seconds
Started Jan 24 02:02:45 PM PST 24
Finished Jan 24 02:02:58 PM PST 24
Peak memory 201224 kb
Host smart-6bf9a1ed-b375-4107-89cd-6c9cf9f12644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573561961 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.2573561961
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2773408628
Short name T983
Test name
Test status
Simulation time 122396967 ps
CPU time 2.05 seconds
Started Jan 24 02:02:32 PM PST 24
Finished Jan 24 02:02:47 PM PST 24
Peak memory 217980 kb
Host smart-a5ac73c6-6688-47f5-a940-2a18d617f40d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773408628 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2773408628
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1442585419
Short name T228
Test name
Test status
Simulation time 248641881 ps
CPU time 2.09 seconds
Started Jan 24 02:02:38 PM PST 24
Finished Jan 24 02:02:55 PM PST 24
Peak memory 209748 kb
Host smart-30a9466f-908c-4de2-b4bc-17bd1e778028
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442585419 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1442585419
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1296522414
Short name T210
Test name
Test status
Simulation time 129805677 ps
CPU time 1.97 seconds
Started Jan 24 03:28:44 PM PST 24
Finished Jan 24 03:28:47 PM PST 24
Peak memory 201228 kb
Host smart-7b318783-759d-4faf-a0b6-5807109e0131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296522414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.1296522414
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2751657947
Short name T97
Test name
Test status
Simulation time 124404086 ps
CPU time 2.77 seconds
Started Jan 24 02:02:48 PM PST 24
Finished Jan 24 02:03:00 PM PST 24
Peak memory 201244 kb
Host smart-cc7cc94e-e2df-46e6-b4c4-5f9539d8f9f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751657947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.2751657947
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2938446413
Short name T243
Test name
Test status
Simulation time 28028372 ps
CPU time 1.1 seconds
Started Jan 24 02:03:03 PM PST 24
Finished Jan 24 02:03:16 PM PST 24
Peak memory 201004 kb
Host smart-8b8b3af7-9fbd-49a0-9600-d3874b614c08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938446413 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2938446413
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1906154404
Short name T88
Test name
Test status
Simulation time 14806594 ps
CPU time 0.82 seconds
Started Jan 24 04:37:27 PM PST 24
Finished Jan 24 04:37:29 PM PST 24
Peak memory 200980 kb
Host smart-4ffbc868-fdd0-4b79-b9d3-4acd917e393c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906154404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1906154404
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2108358070
Short name T263
Test name
Test status
Simulation time 21398890 ps
CPU time 0.73 seconds
Started Jan 24 02:55:47 PM PST 24
Finished Jan 24 02:55:56 PM PST 24
Peak memory 199260 kb
Host smart-a99e3ff0-de67-46c5-8293-564f0c9ec44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108358070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2108358070
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1633146775
Short name T231
Test name
Test status
Simulation time 159347224 ps
CPU time 1.62 seconds
Started Jan 24 02:03:04 PM PST 24
Finished Jan 24 02:03:17 PM PST 24
Peak memory 201248 kb
Host smart-cf2138de-7219-4a1f-95a0-f9806ef8245a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633146775 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1633146775
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.74353426
Short name T119
Test name
Test status
Simulation time 366724758 ps
CPU time 2.47 seconds
Started Jan 24 02:03:01 PM PST 24
Finished Jan 24 02:03:10 PM PST 24
Peak memory 209748 kb
Host smart-c466ccaa-97ae-4968-9653-76edcb97324f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74353426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.clkmgr_shadow_reg_errors.74353426
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1662619775
Short name T68
Test name
Test status
Simulation time 426868684 ps
CPU time 3.5 seconds
Started Jan 24 02:22:57 PM PST 24
Finished Jan 24 02:23:25 PM PST 24
Peak memory 201580 kb
Host smart-24c45e3b-2e3f-42d4-b865-9a280dfbb00f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662619775 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1662619775
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2212907810
Short name T186
Test name
Test status
Simulation time 26179044 ps
CPU time 1.5 seconds
Started Jan 24 02:03:00 PM PST 24
Finished Jan 24 02:03:06 PM PST 24
Peak memory 201164 kb
Host smart-69961188-496e-48a8-b05d-10ebf5af0653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212907810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.2212907810
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3381551241
Short name T148
Test name
Test status
Simulation time 118961219 ps
CPU time 1.45 seconds
Started Jan 24 02:03:01 PM PST 24
Finished Jan 24 02:03:13 PM PST 24
Peak memory 201088 kb
Host smart-ab41c860-8c0c-4c64-bb7e-138d93eac2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381551241 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3381551241
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1292395205
Short name T232
Test name
Test status
Simulation time 58192713 ps
CPU time 0.92 seconds
Started Jan 24 02:02:58 PM PST 24
Finished Jan 24 02:03:01 PM PST 24
Peak memory 200936 kb
Host smart-fc24e923-525e-4193-9fe0-c6407036f679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292395205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1292395205
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.4057277497
Short name T213
Test name
Test status
Simulation time 19258696 ps
CPU time 0.68 seconds
Started Jan 24 02:02:59 PM PST 24
Finished Jan 24 02:03:02 PM PST 24
Peak memory 199116 kb
Host smart-5b75f3fa-1810-4fba-9505-89bf2671b2c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057277497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.4057277497
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.954640441
Short name T270
Test name
Test status
Simulation time 52754472 ps
CPU time 1.25 seconds
Started Jan 24 02:03:01 PM PST 24
Finished Jan 24 02:03:11 PM PST 24
Peak memory 201200 kb
Host smart-40322790-a728-4c5c-a125-f14cf2e09474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954640441 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 15.clkmgr_same_csr_outstanding.954640441
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1190020443
Short name T33
Test name
Test status
Simulation time 56322229 ps
CPU time 1.28 seconds
Started Jan 24 02:46:55 PM PST 24
Finished Jan 24 02:47:14 PM PST 24
Peak memory 201396 kb
Host smart-3e35ac3f-2e30-4a62-b485-335121d5443b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190020443 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.1190020443
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3056119070
Short name T115
Test name
Test status
Simulation time 210320864 ps
CPU time 2.87 seconds
Started Jan 24 02:03:06 PM PST 24
Finished Jan 24 02:03:22 PM PST 24
Peak memory 201548 kb
Host smart-40e69fe1-0019-4afa-a706-4cc85cef85a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056119070 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3056119070
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2857713063
Short name T225
Test name
Test status
Simulation time 533765125 ps
CPU time 4.66 seconds
Started Jan 24 02:03:03 PM PST 24
Finished Jan 24 02:03:20 PM PST 24
Peak memory 201180 kb
Host smart-e55bd083-77b7-4862-9fa0-0c926d610c17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857713063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.2857713063
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.753064452
Short name T141
Test name
Test status
Simulation time 129615547 ps
CPU time 1.75 seconds
Started Jan 24 02:02:58 PM PST 24
Finished Jan 24 02:03:02 PM PST 24
Peak memory 201248 kb
Host smart-439d6a8f-eca9-44b4-8a51-e9fb613c2301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753064452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_tl_intg_err.753064452
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4135396721
Short name T152
Test name
Test status
Simulation time 104990863 ps
CPU time 1.39 seconds
Started Jan 24 02:03:15 PM PST 24
Finished Jan 24 02:03:42 PM PST 24
Peak memory 200856 kb
Host smart-17c7ebc1-0cbc-4d6d-8f92-4935c9b41276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135396721 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.4135396721
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1658579982
Short name T91
Test name
Test status
Simulation time 16916416 ps
CPU time 0.77 seconds
Started Jan 24 02:03:14 PM PST 24
Finished Jan 24 02:03:31 PM PST 24
Peak memory 200964 kb
Host smart-ba49e2ad-d9ec-4863-8b4f-defdade53d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658579982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1658579982
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3743911163
Short name T170
Test name
Test status
Simulation time 11981446 ps
CPU time 0.66 seconds
Started Jan 24 02:03:03 PM PST 24
Finished Jan 24 02:03:15 PM PST 24
Peak memory 199276 kb
Host smart-a1bee02f-c2c7-4e2f-bde9-8d1a4276bfa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743911163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.3743911163
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3710709657
Short name T169
Test name
Test status
Simulation time 85458192 ps
CPU time 1.13 seconds
Started Jan 24 02:49:40 PM PST 24
Finished Jan 24 02:49:58 PM PST 24
Peak memory 201084 kb
Host smart-4c201104-3d16-4309-96bb-ba2bdd77bb80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710709657 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.3710709657
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.4182306879
Short name T124
Test name
Test status
Simulation time 123220359 ps
CPU time 2.02 seconds
Started Jan 24 02:03:03 PM PST 24
Finished Jan 24 02:03:17 PM PST 24
Peak memory 201536 kb
Host smart-1966ae5d-420b-49ab-b4e8-3e749bf94b97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182306879 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.4182306879
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2943435193
Short name T203
Test name
Test status
Simulation time 142105021 ps
CPU time 3.02 seconds
Started Jan 24 02:03:01 PM PST 24
Finished Jan 24 02:03:12 PM PST 24
Peak memory 201636 kb
Host smart-d577ef43-b8f2-4c9f-a513-56c3d88ab5fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943435193 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2943435193
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2670501543
Short name T219
Test name
Test status
Simulation time 406622643 ps
CPU time 3.43 seconds
Started Jan 24 02:03:06 PM PST 24
Finished Jan 24 02:03:23 PM PST 24
Peak memory 201088 kb
Host smart-7ddd563b-6bf7-43e1-9437-4f4f98d6a79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670501543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2670501543
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1002503508
Short name T142
Test name
Test status
Simulation time 123509766 ps
CPU time 1.97 seconds
Started Jan 24 02:02:58 PM PST 24
Finished Jan 24 02:03:03 PM PST 24
Peak memory 201236 kb
Host smart-5264dc56-a7fe-4b18-b2c7-d6e0d2a262fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002503508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.1002503508
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.977920538
Short name T202
Test name
Test status
Simulation time 33294249 ps
CPU time 1.13 seconds
Started Jan 24 02:29:38 PM PST 24
Finished Jan 24 02:29:53 PM PST 24
Peak memory 201036 kb
Host smart-a40df49b-e25f-4468-b171-568fe9dec5e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977920538 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.977920538
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2246186042
Short name T251
Test name
Test status
Simulation time 33985158 ps
CPU time 0.88 seconds
Started Jan 24 02:03:15 PM PST 24
Finished Jan 24 02:03:41 PM PST 24
Peak memory 200812 kb
Host smart-b1020875-a53b-4033-9c0e-8d3cd48d7dc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246186042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.2246186042
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2696660313
Short name T178
Test name
Test status
Simulation time 12033543 ps
CPU time 0.69 seconds
Started Jan 24 02:03:11 PM PST 24
Finished Jan 24 02:03:28 PM PST 24
Peak memory 199196 kb
Host smart-575234fd-2752-43c0-8cb3-ca94fbc6746c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696660313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2696660313
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.127445488
Short name T131
Test name
Test status
Simulation time 35041693 ps
CPU time 1.05 seconds
Started Jan 24 02:03:10 PM PST 24
Finished Jan 24 02:03:27 PM PST 24
Peak memory 200952 kb
Host smart-919d75c7-d091-4354-b75b-fa0bd0d5d594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127445488 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 17.clkmgr_same_csr_outstanding.127445488
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3338152986
Short name T125
Test name
Test status
Simulation time 262890239 ps
CPU time 2.12 seconds
Started Jan 24 02:03:06 PM PST 24
Finished Jan 24 02:03:21 PM PST 24
Peak memory 217580 kb
Host smart-99e3f6d7-679d-493c-911b-31c96451f784
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338152986 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3338152986
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.4148070474
Short name T265
Test name
Test status
Simulation time 861949209 ps
CPU time 5.12 seconds
Started Jan 24 02:03:11 PM PST 24
Finished Jan 24 02:03:32 PM PST 24
Peak memory 201204 kb
Host smart-2032229c-7eaf-44e7-abc4-29ed719480df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148070474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.4148070474
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.733099211
Short name T980
Test name
Test status
Simulation time 119450526 ps
CPU time 2.64 seconds
Started Jan 24 02:23:09 PM PST 24
Finished Jan 24 02:23:33 PM PST 24
Peak memory 201180 kb
Host smart-f70a0095-2c51-4e20-a1be-ec574375c350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733099211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.733099211
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3457944640
Short name T216
Test name
Test status
Simulation time 33259748 ps
CPU time 1.04 seconds
Started Jan 24 02:03:37 PM PST 24
Finished Jan 24 02:04:36 PM PST 24
Peak memory 200880 kb
Host smart-ab628d49-65e9-447e-804d-7b4a1331b9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457944640 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3457944640
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3413022252
Short name T65
Test name
Test status
Simulation time 18094523 ps
CPU time 0.82 seconds
Started Jan 24 02:03:38 PM PST 24
Finished Jan 24 02:04:32 PM PST 24
Peak memory 200900 kb
Host smart-38f4e995-a1d8-4f1e-9eed-83bac097dead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413022252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.3413022252
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1197468002
Short name T166
Test name
Test status
Simulation time 76266923 ps
CPU time 1.38 seconds
Started Jan 24 02:03:45 PM PST 24
Finished Jan 24 02:04:45 PM PST 24
Peak memory 200988 kb
Host smart-bb865a38-8cec-4d5b-8e46-cd2d62aba9b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197468002 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1197468002
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3750690284
Short name T129
Test name
Test status
Simulation time 76671660 ps
CPU time 1.49 seconds
Started Jan 24 02:31:19 PM PST 24
Finished Jan 24 02:31:31 PM PST 24
Peak memory 201332 kb
Host smart-ffb4c2bf-a336-4448-a788-9a14c1594a72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750690284 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3750690284
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3561715933
Short name T71
Test name
Test status
Simulation time 255848383 ps
CPU time 2.43 seconds
Started Jan 24 02:03:14 PM PST 24
Finished Jan 24 02:03:31 PM PST 24
Peak memory 209728 kb
Host smart-1d590f34-12f9-44f9-b83b-920a95f65880
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561715933 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3561715933
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1592538347
Short name T976
Test name
Test status
Simulation time 194250563 ps
CPU time 2.93 seconds
Started Jan 24 02:16:26 PM PST 24
Finished Jan 24 02:17:00 PM PST 24
Peak memory 201184 kb
Host smart-e1e56ba3-ab9c-4987-a47e-7ff862c32200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592538347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.1592538347
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3521047718
Short name T7
Test name
Test status
Simulation time 110313618 ps
CPU time 1.19 seconds
Started Jan 24 02:03:38 PM PST 24
Finished Jan 24 02:04:32 PM PST 24
Peak memory 200948 kb
Host smart-1c205a06-efe4-4984-a267-4f84b315172b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521047718 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3521047718
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1332804855
Short name T248
Test name
Test status
Simulation time 29509127 ps
CPU time 0.84 seconds
Started Jan 24 02:03:38 PM PST 24
Finished Jan 24 02:04:32 PM PST 24
Peak memory 200980 kb
Host smart-b910e0af-e037-4aba-904b-8c9935489476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332804855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.1332804855
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3904706169
Short name T198
Test name
Test status
Simulation time 18433463 ps
CPU time 0.66 seconds
Started Jan 24 02:03:42 PM PST 24
Finished Jan 24 02:04:44 PM PST 24
Peak memory 199224 kb
Host smart-24d22113-0d86-488f-9d6d-d94c5043eb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904706169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.3904706169
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1591140451
Short name T245
Test name
Test status
Simulation time 33195867 ps
CPU time 0.97 seconds
Started Jan 24 02:03:39 PM PST 24
Finished Jan 24 02:04:42 PM PST 24
Peak memory 200964 kb
Host smart-7cf12f80-af74-4cc2-9d48-077512a7c462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591140451 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.1591140451
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2960295507
Short name T255
Test name
Test status
Simulation time 53740496 ps
CPU time 1.24 seconds
Started Jan 24 02:03:37 PM PST 24
Finished Jan 24 02:04:33 PM PST 24
Peak memory 201304 kb
Host smart-8d1fa3ef-6f1a-4996-974b-e8d3f5ab9ef8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960295507 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2960295507
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2316532964
Short name T72
Test name
Test status
Simulation time 146933564 ps
CPU time 3.1 seconds
Started Jan 24 02:03:40 PM PST 24
Finished Jan 24 02:04:37 PM PST 24
Peak memory 209776 kb
Host smart-14bd22bc-c3ca-4342-bc56-05b386ae615d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316532964 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2316532964
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1926648941
Short name T977
Test name
Test status
Simulation time 43193491 ps
CPU time 1.47 seconds
Started Jan 24 02:03:41 PM PST 24
Finished Jan 24 02:04:44 PM PST 24
Peak memory 201008 kb
Host smart-72dc7730-f37c-45d9-9f93-8167844ac880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926648941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1926648941
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1999937076
Short name T99
Test name
Test status
Simulation time 194186968 ps
CPU time 2.9 seconds
Started Jan 24 02:03:37 PM PST 24
Finished Jan 24 02:04:38 PM PST 24
Peak memory 201212 kb
Host smart-8832d4ff-a425-48e2-afe7-7a7a70a9fade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999937076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.1999937076
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1764756061
Short name T230
Test name
Test status
Simulation time 86956106 ps
CPU time 1.68 seconds
Started Jan 24 02:00:39 PM PST 24
Finished Jan 24 02:00:44 PM PST 24
Peak memory 201140 kb
Host smart-8e1818d4-c6a2-4544-aa71-0a31c3c4ad53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764756061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1764756061
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2179030977
Short name T92
Test name
Test status
Simulation time 139619135 ps
CPU time 3.62 seconds
Started Jan 24 02:00:25 PM PST 24
Finished Jan 24 02:00:30 PM PST 24
Peak memory 201200 kb
Host smart-db35dfba-5dd1-4bfa-9bd9-a8e4cea61647
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179030977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.2179030977
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1058535796
Short name T174
Test name
Test status
Simulation time 20200032 ps
CPU time 0.86 seconds
Started Jan 24 02:00:23 PM PST 24
Finished Jan 24 02:00:27 PM PST 24
Peak memory 200612 kb
Host smart-3b93acb9-a3a9-4c53-acda-2a573927c971
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058535796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.1058535796
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2844928528
Short name T147
Test name
Test status
Simulation time 27089129 ps
CPU time 1.55 seconds
Started Jan 24 02:00:35 PM PST 24
Finished Jan 24 02:00:39 PM PST 24
Peak memory 201052 kb
Host smart-672751be-ece9-452c-9216-5875568fb44d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844928528 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2844928528
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.973724136
Short name T269
Test name
Test status
Simulation time 22315901 ps
CPU time 0.88 seconds
Started Jan 24 02:00:26 PM PST 24
Finished Jan 24 02:00:28 PM PST 24
Peak memory 200924 kb
Host smart-39ceae1c-4357-4130-b922-c923dd2b5f75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973724136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.c
lkmgr_csr_rw.973724136
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3044401109
Short name T182
Test name
Test status
Simulation time 21088930 ps
CPU time 0.7 seconds
Started Jan 24 02:00:21 PM PST 24
Finished Jan 24 02:00:24 PM PST 24
Peak memory 199256 kb
Host smart-b6d3cab4-d08c-41c0-81a3-cc87f2bfd4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044401109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.3044401109
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.4259008471
Short name T38
Test name
Test status
Simulation time 50968538 ps
CPU time 1 seconds
Started Jan 24 02:00:37 PM PST 24
Finished Jan 24 02:00:41 PM PST 24
Peak memory 200984 kb
Host smart-2b4ad86a-0dbd-4740-8947-a7ffe0113454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259008471 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.4259008471
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.900418257
Short name T34
Test name
Test status
Simulation time 230887878 ps
CPU time 2.38 seconds
Started Jan 24 02:00:22 PM PST 24
Finished Jan 24 02:00:27 PM PST 24
Peak memory 209764 kb
Host smart-429f185e-eda0-4387-bec0-2bcc0a77dee1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900418257 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.clkmgr_shadow_reg_errors.900418257
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2460199254
Short name T73
Test name
Test status
Simulation time 163569870 ps
CPU time 3.23 seconds
Started Jan 24 02:00:29 PM PST 24
Finished Jan 24 02:00:34 PM PST 24
Peak memory 217996 kb
Host smart-75eccf74-1990-4cc7-b8fe-980dbf8bd04f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460199254 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2460199254
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2679138143
Short name T221
Test name
Test status
Simulation time 41881105 ps
CPU time 2.68 seconds
Started Jan 24 02:00:22 PM PST 24
Finished Jan 24 02:00:28 PM PST 24
Peak memory 201196 kb
Host smart-6e6db6b0-4fb9-4edf-8111-64bfb494fc37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679138143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.2679138143
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3171689862
Short name T982
Test name
Test status
Simulation time 147720408 ps
CPU time 2.85 seconds
Started Jan 24 02:00:22 PM PST 24
Finished Jan 24 02:00:28 PM PST 24
Peak memory 201192 kb
Host smart-de3584c6-1ffe-4d52-ab05-a653b945ec71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171689862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3171689862
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.565925929
Short name T173
Test name
Test status
Simulation time 27492375 ps
CPU time 0.69 seconds
Started Jan 24 02:03:38 PM PST 24
Finished Jan 24 02:04:36 PM PST 24
Peak memory 199232 kb
Host smart-1ee6db76-d7ff-4b99-a6ca-073aa5cc4aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565925929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clk
mgr_intr_test.565925929
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2099723501
Short name T267
Test name
Test status
Simulation time 12917362 ps
CPU time 0.67 seconds
Started Jan 24 02:03:39 PM PST 24
Finished Jan 24 02:04:32 PM PST 24
Peak memory 199228 kb
Host smart-b8016a55-80d4-4b63-a797-f62ed3d8deb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099723501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.2099723501
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3265605491
Short name T242
Test name
Test status
Simulation time 30984296 ps
CPU time 0.69 seconds
Started Jan 24 02:03:38 PM PST 24
Finished Jan 24 02:04:36 PM PST 24
Peak memory 199260 kb
Host smart-cd7af4cb-631c-4872-bdd1-88dd04a1a9e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265605491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.3265605491
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1920925551
Short name T240
Test name
Test status
Simulation time 21719775 ps
CPU time 0.7 seconds
Started Jan 24 02:04:23 PM PST 24
Finished Jan 24 02:05:20 PM PST 24
Peak memory 199196 kb
Host smart-c43dbe77-19ae-4e42-85ca-cfabf88dcb85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920925551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.1920925551
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1849481956
Short name T211
Test name
Test status
Simulation time 12551334 ps
CPU time 0.66 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:04:58 PM PST 24
Peak memory 199196 kb
Host smart-770f8d6f-f6f1-4ebe-ab66-2f98699e6365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849481956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1849481956
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2978430974
Short name T190
Test name
Test status
Simulation time 12642320 ps
CPU time 0.66 seconds
Started Jan 24 02:04:25 PM PST 24
Finished Jan 24 02:05:23 PM PST 24
Peak memory 199228 kb
Host smart-10a29a7d-24d0-4eb8-8e9e-f35cf297e47e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978430974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2978430974
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.535671226
Short name T175
Test name
Test status
Simulation time 10827236 ps
CPU time 0.71 seconds
Started Jan 24 02:04:22 PM PST 24
Finished Jan 24 02:05:19 PM PST 24
Peak memory 199228 kb
Host smart-9dec399b-69fc-4ec9-88ae-a01c2a3aef60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535671226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clk
mgr_intr_test.535671226
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2868299185
Short name T191
Test name
Test status
Simulation time 47454588 ps
CPU time 0.74 seconds
Started Jan 24 02:04:22 PM PST 24
Finished Jan 24 02:05:18 PM PST 24
Peak memory 199188 kb
Host smart-ab31a03e-37c6-40d0-9697-085fcd421c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868299185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.2868299185
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1456602818
Short name T981
Test name
Test status
Simulation time 13847983 ps
CPU time 0.65 seconds
Started Jan 24 02:03:49 PM PST 24
Finished Jan 24 02:04:31 PM PST 24
Peak memory 199212 kb
Host smart-bc854031-3341-444b-bb29-c59e4ce258dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456602818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.1456602818
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3126244897
Short name T969
Test name
Test status
Simulation time 15547284 ps
CPU time 0.69 seconds
Started Jan 24 02:03:50 PM PST 24
Finished Jan 24 02:04:34 PM PST 24
Peak memory 199232 kb
Host smart-07efbc64-090f-4799-a7f3-1f22eb99454c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126244897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3126244897
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2230754943
Short name T212
Test name
Test status
Simulation time 144873125 ps
CPU time 2 seconds
Started Jan 24 02:00:35 PM PST 24
Finished Jan 24 02:00:39 PM PST 24
Peak memory 201184 kb
Host smart-2d272265-918c-4cf1-860d-bc30418fe0dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230754943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.2230754943
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.439008931
Short name T973
Test name
Test status
Simulation time 370444804 ps
CPU time 3.97 seconds
Started Jan 24 02:00:37 PM PST 24
Finished Jan 24 02:00:44 PM PST 24
Peak memory 201156 kb
Host smart-2f60eea9-3ec8-4bba-9609-15f896e55d27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439008931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.439008931
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1331626520
Short name T189
Test name
Test status
Simulation time 42563859 ps
CPU time 0.83 seconds
Started Jan 24 02:00:38 PM PST 24
Finished Jan 24 02:00:42 PM PST 24
Peak memory 200976 kb
Host smart-8c05f3df-23c4-4ba1-a721-26f10b905076
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331626520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1331626520
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2855571251
Short name T271
Test name
Test status
Simulation time 34176284 ps
CPU time 1.19 seconds
Started Jan 24 02:46:21 PM PST 24
Finished Jan 24 02:46:25 PM PST 24
Peak memory 201012 kb
Host smart-ea432dec-f125-48d6-8099-5399fceac70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855571251 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.2855571251
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1930624230
Short name T187
Test name
Test status
Simulation time 59682558 ps
CPU time 0.91 seconds
Started Jan 24 02:00:36 PM PST 24
Finished Jan 24 02:00:39 PM PST 24
Peak memory 200888 kb
Host smart-f2576b6a-9c6b-4aec-8954-d9d7411694e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930624230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1930624230
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3750241828
Short name T223
Test name
Test status
Simulation time 38515649 ps
CPU time 0.71 seconds
Started Jan 24 02:00:39 PM PST 24
Finished Jan 24 02:00:43 PM PST 24
Peak memory 199220 kb
Host smart-368994d3-1739-423a-9e6c-e49d2d2e43ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750241828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.3750241828
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2022862280
Short name T205
Test name
Test status
Simulation time 88355211 ps
CPU time 1.15 seconds
Started Jan 24 02:00:36 PM PST 24
Finished Jan 24 02:00:41 PM PST 24
Peak memory 201064 kb
Host smart-0af455d9-3034-461b-bcf5-64b2e1e7d1fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022862280 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.2022862280
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4223453211
Short name T260
Test name
Test status
Simulation time 230636585 ps
CPU time 2.15 seconds
Started Jan 24 02:00:40 PM PST 24
Finished Jan 24 02:00:45 PM PST 24
Peak memory 201620 kb
Host smart-4f8530d1-bfca-4b08-abb0-a1afa2f62f8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223453211 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4223453211
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.990752454
Short name T237
Test name
Test status
Simulation time 164330162 ps
CPU time 2.07 seconds
Started Jan 24 02:00:37 PM PST 24
Finished Jan 24 02:00:42 PM PST 24
Peak memory 201136 kb
Host smart-d95b672a-ab5c-4e55-9c37-95e532f8c19b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990752454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.990752454
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3149577883
Short name T39
Test name
Test status
Simulation time 25097068 ps
CPU time 0.68 seconds
Started Jan 24 02:04:03 PM PST 24
Finished Jan 24 02:04:46 PM PST 24
Peak memory 199116 kb
Host smart-935eba2a-6f41-4afe-af2e-9a664a7d0cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149577883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3149577883
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1151503740
Short name T233
Test name
Test status
Simulation time 64587103 ps
CPU time 0.78 seconds
Started Jan 24 02:04:01 PM PST 24
Finished Jan 24 02:04:43 PM PST 24
Peak memory 199260 kb
Host smart-a503c20f-7c14-4a29-bf30-0382c41ad924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151503740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1151503740
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3573091087
Short name T209
Test name
Test status
Simulation time 17976381 ps
CPU time 0.68 seconds
Started Jan 24 02:04:08 PM PST 24
Finished Jan 24 02:04:57 PM PST 24
Peak memory 199240 kb
Host smart-36da7b6d-eeed-48be-a8dd-b13e836cba15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573091087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.3573091087
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.4042800230
Short name T167
Test name
Test status
Simulation time 14191116 ps
CPU time 0.68 seconds
Started Jan 24 02:04:11 PM PST 24
Finished Jan 24 02:05:00 PM PST 24
Peak memory 199228 kb
Host smart-3f27dab3-68f9-4ce8-85bb-c27f1f48975b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042800230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.4042800230
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.867420512
Short name T244
Test name
Test status
Simulation time 14149575 ps
CPU time 0.67 seconds
Started Jan 24 02:04:02 PM PST 24
Finished Jan 24 02:04:43 PM PST 24
Peak memory 199192 kb
Host smart-45ea3cb4-a52e-49f4-8a60-0780f274c12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867420512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk
mgr_intr_test.867420512
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.690806467
Short name T193
Test name
Test status
Simulation time 14497089 ps
CPU time 0.73 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:04:58 PM PST 24
Peak memory 199112 kb
Host smart-fd5e16d4-825d-4fcb-a537-ae32434765a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690806467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk
mgr_intr_test.690806467
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3244263625
Short name T246
Test name
Test status
Simulation time 32399748 ps
CPU time 0.71 seconds
Started Jan 24 02:04:14 PM PST 24
Finished Jan 24 02:05:03 PM PST 24
Peak memory 199188 kb
Host smart-029d153a-1d1a-4490-bfe6-636f3e8e3dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244263625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.3244263625
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.4010754396
Short name T165
Test name
Test status
Simulation time 20530086 ps
CPU time 0.68 seconds
Started Jan 24 02:04:12 PM PST 24
Finished Jan 24 02:05:01 PM PST 24
Peak memory 199276 kb
Host smart-c0395b54-77fe-497b-b4d2-7a146edc0c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010754396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.4010754396
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3754470652
Short name T201
Test name
Test status
Simulation time 33035675 ps
CPU time 0.7 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:04:57 PM PST 24
Peak memory 199232 kb
Host smart-36cb70e7-4bc8-4ca6-b8fe-6a765bf98598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754470652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.3754470652
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.159629321
Short name T249
Test name
Test status
Simulation time 57186892 ps
CPU time 0.75 seconds
Started Jan 24 02:04:08 PM PST 24
Finished Jan 24 02:04:57 PM PST 24
Peak memory 199200 kb
Host smart-220832a5-c525-4cce-8cdc-557730ed220b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159629321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.159629321
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3272166377
Short name T200
Test name
Test status
Simulation time 66242403 ps
CPU time 1.85 seconds
Started Jan 24 02:00:54 PM PST 24
Finished Jan 24 02:00:59 PM PST 24
Peak memory 201272 kb
Host smart-bd467151-1d36-4aa5-b73e-08787e3ccef4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272166377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3272166377
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.4096767816
Short name T229
Test name
Test status
Simulation time 494631799 ps
CPU time 8.72 seconds
Started Jan 24 02:00:49 PM PST 24
Finished Jan 24 02:01:04 PM PST 24
Peak memory 201212 kb
Host smart-43c8c825-dca2-4316-afc7-c61ff6bb38a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096767816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.4096767816
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2214537191
Short name T192
Test name
Test status
Simulation time 55277370 ps
CPU time 0.86 seconds
Started Jan 24 02:00:49 PM PST 24
Finished Jan 24 02:00:57 PM PST 24
Peak memory 200512 kb
Host smart-da19e997-31e2-4469-bdd3-dcb01a13260b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214537191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.2214537191
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.758289806
Short name T37
Test name
Test status
Simulation time 21816370 ps
CPU time 0.95 seconds
Started Jan 24 02:01:11 PM PST 24
Finished Jan 24 02:01:15 PM PST 24
Peak memory 200988 kb
Host smart-80885395-17d1-460a-ae07-13e99e12ddba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758289806 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.758289806
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3455643807
Short name T239
Test name
Test status
Simulation time 64485842 ps
CPU time 1.04 seconds
Started Jan 24 02:00:52 PM PST 24
Finished Jan 24 02:00:58 PM PST 24
Peak memory 200964 kb
Host smart-a755fac9-b53b-4b5c-8b80-5ad7930cf120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455643807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3455643807
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1026645858
Short name T224
Test name
Test status
Simulation time 75512350 ps
CPU time 0.8 seconds
Started Jan 24 02:00:48 PM PST 24
Finished Jan 24 02:00:56 PM PST 24
Peak memory 199184 kb
Host smart-154dacef-45c0-45ca-9e4f-df5c8e8061a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026645858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1026645858
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.4238989180
Short name T226
Test name
Test status
Simulation time 63314832 ps
CPU time 1.19 seconds
Started Jan 24 02:01:13 PM PST 24
Finished Jan 24 02:01:17 PM PST 24
Peak memory 200992 kb
Host smart-48777597-af05-4780-91ca-90d7b532f5d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238989180 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.4238989180
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1399272846
Short name T259
Test name
Test status
Simulation time 64110677 ps
CPU time 1.34 seconds
Started Jan 24 02:00:35 PM PST 24
Finished Jan 24 02:00:38 PM PST 24
Peak memory 201328 kb
Host smart-c58e0104-ab93-4009-8cc7-8efc0b50152b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399272846 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.1399272846
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1474207632
Short name T116
Test name
Test status
Simulation time 79733798 ps
CPU time 1.77 seconds
Started Jan 24 02:00:38 PM PST 24
Finished Jan 24 02:00:43 PM PST 24
Peak memory 209812 kb
Host smart-a729a030-f086-456a-83c3-a52110fcfbb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474207632 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.1474207632
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.4247113158
Short name T78
Test name
Test status
Simulation time 46047804 ps
CPU time 1.78 seconds
Started Jan 24 02:00:39 PM PST 24
Finished Jan 24 02:00:44 PM PST 24
Peak memory 201148 kb
Host smart-8ad31742-9dcb-4dd7-aa25-c6061c611eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247113158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.4247113158
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1198248770
Short name T85
Test name
Test status
Simulation time 147505111 ps
CPU time 1.99 seconds
Started Jan 24 02:00:49 PM PST 24
Finished Jan 24 02:00:58 PM PST 24
Peak memory 201204 kb
Host smart-cfc531fa-679d-43c0-89aa-6b1d4987041a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198248770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1198248770
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3359132270
Short name T218
Test name
Test status
Simulation time 14099159 ps
CPU time 0.68 seconds
Started Jan 24 02:04:10 PM PST 24
Finished Jan 24 02:04:59 PM PST 24
Peak memory 199240 kb
Host smart-f73c43e9-56eb-4930-a565-7cc051154195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359132270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3359132270
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2938260095
Short name T979
Test name
Test status
Simulation time 40360925 ps
CPU time 0.72 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:04:59 PM PST 24
Peak memory 199240 kb
Host smart-ef8e527a-7ea1-41c7-aa61-bbea748fc257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938260095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2938260095
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2875857436
Short name T258
Test name
Test status
Simulation time 16247275 ps
CPU time 0.71 seconds
Started Jan 24 02:04:13 PM PST 24
Finished Jan 24 02:05:02 PM PST 24
Peak memory 199232 kb
Host smart-4f9ca267-dfe2-4e35-b0d0-746066fdc244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875857436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.2875857436
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3419104825
Short name T247
Test name
Test status
Simulation time 28248931 ps
CPU time 0.69 seconds
Started Jan 24 02:04:11 PM PST 24
Finished Jan 24 02:04:59 PM PST 24
Peak memory 199276 kb
Host smart-d2c6202d-f1c4-4b70-9c30-de887b6ef8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419104825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3419104825
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.4084900350
Short name T172
Test name
Test status
Simulation time 14283242 ps
CPU time 0.65 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:04:57 PM PST 24
Peak memory 199196 kb
Host smart-a271e46c-dab9-4fbe-9692-bada7b0bb81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084900350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.4084900350
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3896156411
Short name T235
Test name
Test status
Simulation time 13654633 ps
CPU time 0.67 seconds
Started Jan 24 02:04:08 PM PST 24
Finished Jan 24 02:04:57 PM PST 24
Peak memory 199304 kb
Host smart-9e987dcb-a5c6-4fe9-8ad8-ad57e99efd9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896156411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.3896156411
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1958547448
Short name T971
Test name
Test status
Simulation time 29069941 ps
CPU time 0.68 seconds
Started Jan 24 02:04:13 PM PST 24
Finished Jan 24 02:05:02 PM PST 24
Peak memory 199216 kb
Host smart-112db24c-a934-4725-a504-d6b5b9c9527c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958547448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.1958547448
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1742293970
Short name T118
Test name
Test status
Simulation time 44875953 ps
CPU time 0.85 seconds
Started Jan 24 02:14:05 PM PST 24
Finished Jan 24 02:14:16 PM PST 24
Peak memory 199240 kb
Host smart-d2db112a-76f7-4da0-bb70-ca5435fb3ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742293970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.1742293970
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3110640980
Short name T168
Test name
Test status
Simulation time 14713333 ps
CPU time 0.71 seconds
Started Jan 24 02:04:13 PM PST 24
Finished Jan 24 02:05:02 PM PST 24
Peak memory 199232 kb
Host smart-c0f82ac0-0391-4b6f-b8e3-dbe9ab3d9ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110640980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.3110640980
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2628031212
Short name T177
Test name
Test status
Simulation time 17830734 ps
CPU time 0.67 seconds
Started Jan 24 02:04:13 PM PST 24
Finished Jan 24 02:05:02 PM PST 24
Peak memory 199216 kb
Host smart-7e4a6e95-fcb7-4415-a78a-be333b3e39e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628031212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2628031212
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3876932114
Short name T157
Test name
Test status
Simulation time 53982031 ps
CPU time 1.25 seconds
Started Jan 24 02:01:24 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 201016 kb
Host smart-b98932b5-e8cd-4571-9b1a-242573931faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876932114 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.3876932114
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1435351884
Short name T268
Test name
Test status
Simulation time 37372595 ps
CPU time 0.73 seconds
Started Jan 24 02:01:25 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 199256 kb
Host smart-fb0c5f6d-b399-48a3-98cc-0f023f9ef6a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435351884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.1435351884
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.709740708
Short name T254
Test name
Test status
Simulation time 91354255 ps
CPU time 1.19 seconds
Started Jan 24 02:01:26 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 200996 kb
Host smart-0d0345be-7126-4151-8b94-dd27d4d305e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709740708 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.clkmgr_same_csr_outstanding.709740708
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.98670748
Short name T114
Test name
Test status
Simulation time 118763853 ps
CPU time 2.14 seconds
Started Jan 24 02:01:10 PM PST 24
Finished Jan 24 02:01:16 PM PST 24
Peak memory 201568 kb
Host smart-5ac95e25-470c-4d61-ad21-786f0b8b1eab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98670748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.clkmgr_shadow_reg_errors.98670748
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3191824391
Short name T250
Test name
Test status
Simulation time 377077177 ps
CPU time 3.34 seconds
Started Jan 24 02:01:11 PM PST 24
Finished Jan 24 02:01:18 PM PST 24
Peak memory 209760 kb
Host smart-08b790d5-19c6-45d1-b079-37f2d1a99fd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191824391 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3191824391
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3126988111
Short name T81
Test name
Test status
Simulation time 26508405 ps
CPU time 1.78 seconds
Started Jan 24 02:01:10 PM PST 24
Finished Jan 24 02:01:16 PM PST 24
Peak memory 201048 kb
Host smart-a5f847fe-33aa-4a2b-bb17-f596b6c7c4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126988111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.3126988111
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3951357974
Short name T130
Test name
Test status
Simulation time 60723841 ps
CPU time 1.3 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:02:01 PM PST 24
Peak memory 200964 kb
Host smart-9e74a35a-eeee-4f1f-83ae-1f4c5ce1ef04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951357974 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3951357974
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2021176683
Short name T6
Test name
Test status
Simulation time 23501585 ps
CPU time 0.78 seconds
Started Jan 24 02:01:23 PM PST 24
Finished Jan 24 02:01:26 PM PST 24
Peak memory 200932 kb
Host smart-65a9fafb-435c-402c-9358-d73ab862cd74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021176683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.2021176683
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2071582583
Short name T188
Test name
Test status
Simulation time 20721790 ps
CPU time 0.71 seconds
Started Jan 24 02:01:24 PM PST 24
Finished Jan 24 02:01:27 PM PST 24
Peak memory 199156 kb
Host smart-7f00a558-b60b-4aeb-8fe3-1b4a8737b9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071582583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.2071582583
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1474022366
Short name T257
Test name
Test status
Simulation time 40267794 ps
CPU time 1.04 seconds
Started Jan 24 02:01:26 PM PST 24
Finished Jan 24 02:01:29 PM PST 24
Peak memory 201060 kb
Host smart-72981678-7527-40a2-8d54-1c420c4007e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474022366 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1474022366
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.3537455990
Short name T128
Test name
Test status
Simulation time 65571716 ps
CPU time 1.29 seconds
Started Jan 24 02:01:26 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 201368 kb
Host smart-a239e6c9-7791-4f87-a190-d3c073d86800
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537455990 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.3537455990
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1654322644
Short name T117
Test name
Test status
Simulation time 59107253 ps
CPU time 1.61 seconds
Started Jan 24 02:01:31 PM PST 24
Finished Jan 24 02:01:35 PM PST 24
Peak memory 201536 kb
Host smart-46b87e99-0577-4c9c-88ce-9743047c001a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654322644 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1654322644
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1295912075
Short name T82
Test name
Test status
Simulation time 97736044 ps
CPU time 1.76 seconds
Started Jan 24 02:01:24 PM PST 24
Finished Jan 24 02:01:28 PM PST 24
Peak memory 201124 kb
Host smart-87cfc55e-8e42-423c-b295-91246c5fda9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295912075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.1295912075
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2251943731
Short name T234
Test name
Test status
Simulation time 68133163 ps
CPU time 1.53 seconds
Started Jan 24 02:01:22 PM PST 24
Finished Jan 24 02:01:27 PM PST 24
Peak memory 201236 kb
Host smart-5c96c556-d3b9-425b-8c4a-633ddd160675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251943731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.2251943731
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1301491584
Short name T36
Test name
Test status
Simulation time 87015906 ps
CPU time 1.79 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:02:00 PM PST 24
Peak memory 201152 kb
Host smart-57af08e9-5ee0-43c8-86a2-95b91cdc3718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301491584 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1301491584
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3594581008
Short name T179
Test name
Test status
Simulation time 21130334 ps
CPU time 0.91 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:56 PM PST 24
Peak memory 200732 kb
Host smart-6df84223-d2e8-4959-a337-7af666d19b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594581008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.3594581008
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1151955763
Short name T180
Test name
Test status
Simulation time 23975545 ps
CPU time 0.68 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:01:58 PM PST 24
Peak memory 199224 kb
Host smart-d0796dd1-dcb6-47ef-b422-e68ad9a9a1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151955763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.1151955763
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2829950505
Short name T87
Test name
Test status
Simulation time 95649294 ps
CPU time 1.51 seconds
Started Jan 24 03:36:39 PM PST 24
Finished Jan 24 03:36:57 PM PST 24
Peak memory 200980 kb
Host smart-002a1bec-8e55-4d71-981b-5c8a69d76d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829950505 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2829950505
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1605533624
Short name T126
Test name
Test status
Simulation time 65836604 ps
CPU time 1.28 seconds
Started Jan 24 02:01:46 PM PST 24
Finished Jan 24 02:01:57 PM PST 24
Peak memory 201400 kb
Host smart-c2c027e0-25ff-46a1-affa-0e890059fb28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605533624 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.1605533624
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.698039547
Short name T123
Test name
Test status
Simulation time 173508296 ps
CPU time 3.11 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:58 PM PST 24
Peak memory 201552 kb
Host smart-d7e22f94-e287-40fb-93f9-d455e544137e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698039547 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.698039547
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2190969902
Short name T79
Test name
Test status
Simulation time 171692933 ps
CPU time 2.61 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:02:01 PM PST 24
Peak memory 201208 kb
Host smart-decd67bf-f9c3-48b6-b15f-e6fbb0a2138b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190969902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.2190969902
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2408620032
Short name T95
Test name
Test status
Simulation time 300358190 ps
CPU time 3 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:06 PM PST 24
Peak memory 201200 kb
Host smart-dab17e71-6a75-4208-a3c8-12ab5a35c0eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408620032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.2408620032
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.345515400
Short name T195
Test name
Test status
Simulation time 19392450 ps
CPU time 1.12 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:03 PM PST 24
Peak memory 200964 kb
Host smart-33ec93e3-d6f2-406e-8e09-cf57fa64ef71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345515400 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.345515400
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3458505239
Short name T972
Test name
Test status
Simulation time 25338185 ps
CPU time 0.83 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:02 PM PST 24
Peak memory 200864 kb
Host smart-254b343f-f1dc-4f44-8bc9-84fa0ae288a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458505239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3458505239
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.980970159
Short name T236
Test name
Test status
Simulation time 33445962 ps
CPU time 0.77 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:56 PM PST 24
Peak memory 199232 kb
Host smart-b303188b-e60e-4152-a497-0b149ada33d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980970159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_intr_test.980970159
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3108878721
Short name T50
Test name
Test status
Simulation time 35886391 ps
CPU time 1.3 seconds
Started Jan 24 02:23:42 PM PST 24
Finished Jan 24 02:23:58 PM PST 24
Peak memory 201244 kb
Host smart-7680403d-424c-433e-8cb4-0efa00bb6178
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108878721 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.3108878721
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.981079592
Short name T256
Test name
Test status
Simulation time 86318032 ps
CPU time 1.34 seconds
Started Jan 24 02:01:53 PM PST 24
Finished Jan 24 02:02:14 PM PST 24
Peak memory 201312 kb
Host smart-f1265eeb-1597-476f-96e8-0bdc11a5d28d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981079592 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.clkmgr_shadow_reg_errors.981079592
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.244370224
Short name T67
Test name
Test status
Simulation time 694395449 ps
CPU time 3.98 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:59 PM PST 24
Peak memory 201132 kb
Host smart-ae3b2cd3-7e8f-47ea-abaf-26e929826896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244370224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.244370224
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.801948140
Short name T80
Test name
Test status
Simulation time 154853170 ps
CPU time 1.84 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:56 PM PST 24
Peak memory 201208 kb
Host smart-c17e4461-1e03-4750-a9f3-34fdd7c65fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801948140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.801948140
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.97775657
Short name T220
Test name
Test status
Simulation time 30078090 ps
CPU time 1 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:01 PM PST 24
Peak memory 201004 kb
Host smart-14449ed3-3529-4c99-a451-b272353adfde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97775657 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.97775657
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.4168504240
Short name T83
Test name
Test status
Simulation time 24858413 ps
CPU time 0.78 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:01:58 PM PST 24
Peak memory 200872 kb
Host smart-beb500b0-588d-4fd2-b465-6c4831cc1307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168504240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.4168504240
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2906301680
Short name T974
Test name
Test status
Simulation time 13741062 ps
CPU time 0.68 seconds
Started Jan 24 02:01:47 PM PST 24
Finished Jan 24 02:01:57 PM PST 24
Peak memory 199284 kb
Host smart-1d536eca-f399-49c5-a86e-529a2cb7f3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906301680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2906301680
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.560154649
Short name T51
Test name
Test status
Simulation time 82108823 ps
CPU time 1.29 seconds
Started Jan 24 02:01:48 PM PST 24
Finished Jan 24 02:02:03 PM PST 24
Peak memory 201164 kb
Host smart-5b1145cf-fa32-4af0-90ec-6b0bc9693878
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560154649 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.clkmgr_same_csr_outstanding.560154649
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2866541305
Short name T75
Test name
Test status
Simulation time 82733548 ps
CPU time 1.82 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:57 PM PST 24
Peak memory 201620 kb
Host smart-a3892547-1491-42eb-9c0f-c3750a9815a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866541305 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.2866541305
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2484219931
Short name T970
Test name
Test status
Simulation time 51866784 ps
CPU time 2.66 seconds
Started Jan 24 02:01:45 PM PST 24
Finished Jan 24 02:01:58 PM PST 24
Peak memory 201136 kb
Host smart-263936b3-83e5-4f88-89bf-0390c603633e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484219931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.2484219931
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3503930872
Short name T143
Test name
Test status
Simulation time 95337588 ps
CPU time 1.82 seconds
Started Jan 24 02:01:49 PM PST 24
Finished Jan 24 02:02:06 PM PST 24
Peak memory 201112 kb
Host smart-43f854c2-b4ca-46e9-9b1f-1a163f2c78a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503930872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.3503930872
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1594635227
Short name T829
Test name
Test status
Simulation time 41806670 ps
CPU time 0.77 seconds
Started Jan 24 04:10:42 PM PST 24
Finished Jan 24 04:10:49 PM PST 24
Peak memory 200072 kb
Host smart-3831bf07-9a9e-447c-addb-f8352cff1621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594635227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1594635227
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1336840845
Short name T341
Test name
Test status
Simulation time 23511370 ps
CPU time 0.91 seconds
Started Jan 24 04:11:00 PM PST 24
Finished Jan 24 04:11:15 PM PST 24
Peak memory 201292 kb
Host smart-456d9a1a-1947-4a9e-a8fc-1afd66d250d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336840845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1336840845
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.493304550
Short name T685
Test name
Test status
Simulation time 59047817 ps
CPU time 0.91 seconds
Started Jan 24 04:10:53 PM PST 24
Finished Jan 24 04:11:12 PM PST 24
Peak memory 201268 kb
Host smart-10a73e8d-628b-4405-80bf-1a9ddb88d8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493304550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.493304550
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.26177887
Short name T853
Test name
Test status
Simulation time 730275221 ps
CPU time 3.02 seconds
Started Jan 24 04:10:44 PM PST 24
Finished Jan 24 04:10:52 PM PST 24
Peak memory 201364 kb
Host smart-710750b8-d791-4ca6-8739-e44d4acd4767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26177887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.26177887
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1663080246
Short name T888
Test name
Test status
Simulation time 144097711 ps
CPU time 1.24 seconds
Started Jan 24 04:10:48 PM PST 24
Finished Jan 24 04:11:10 PM PST 24
Peak memory 201416 kb
Host smart-90f2678f-b28f-4262-b9b7-b57b5e46464e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663080246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1663080246
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.2769338777
Short name T655
Test name
Test status
Simulation time 27603308 ps
CPU time 0.98 seconds
Started Jan 24 04:10:55 PM PST 24
Finished Jan 24 04:11:12 PM PST 24
Peak memory 201292 kb
Host smart-d0a2dbb4-9024-47eb-b978-1ac4a2a2b510
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769338777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.2769338777
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1727503806
Short name T801
Test name
Test status
Simulation time 41482573 ps
CPU time 0.97 seconds
Started Jan 24 04:32:52 PM PST 24
Finished Jan 24 04:32:53 PM PST 24
Peak memory 201336 kb
Host smart-42134cb7-6707-445b-94c0-342fe04bf7ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727503806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1727503806
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1013630603
Short name T20
Test name
Test status
Simulation time 16152999 ps
CPU time 0.8 seconds
Started Jan 24 05:23:13 PM PST 24
Finished Jan 24 05:23:15 PM PST 24
Peak memory 201272 kb
Host smart-4fef8e1e-8857-411f-b084-8c3ed0a33b9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013630603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.1013630603
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.3977031424
Short name T522
Test name
Test status
Simulation time 16788188 ps
CPU time 0.78 seconds
Started Jan 24 04:10:44 PM PST 24
Finished Jan 24 04:10:50 PM PST 24
Peak memory 201156 kb
Host smart-0191b3df-43cb-4a1f-8f61-c2403fc05fe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977031424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3977031424
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3456605617
Short name T591
Test name
Test status
Simulation time 1101116921 ps
CPU time 4.08 seconds
Started Jan 24 06:47:12 PM PST 24
Finished Jan 24 06:47:16 PM PST 24
Peak memory 201436 kb
Host smart-d68b4503-a9c3-47b9-9ebe-58d0cb7605fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456605617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3456605617
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.2928947166
Short name T64
Test name
Test status
Simulation time 331949010 ps
CPU time 2.25 seconds
Started Jan 24 05:27:19 PM PST 24
Finished Jan 24 05:27:22 PM PST 24
Peak memory 216196 kb
Host smart-42b52e9c-39b7-4a33-8104-940f7f61fb2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928947166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.2928947166
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3421354116
Short name T712
Test name
Test status
Simulation time 27237068 ps
CPU time 0.89 seconds
Started Jan 24 04:10:51 PM PST 24
Finished Jan 24 04:11:15 PM PST 24
Peak memory 201304 kb
Host smart-53637f80-4260-4044-9023-e1bc7f8cd8b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421354116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3421354116
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.1144869695
Short name T751
Test name
Test status
Simulation time 7417395463 ps
CPU time 29.61 seconds
Started Jan 24 04:11:05 PM PST 24
Finished Jan 24 04:11:47 PM PST 24
Peak memory 201700 kb
Host smart-ce984e86-54f4-4086-9dd1-1f76d32c18a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144869695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.1144869695
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.893573949
Short name T155
Test name
Test status
Simulation time 156206705025 ps
CPU time 947.84 seconds
Started Jan 24 04:11:00 PM PST 24
Finished Jan 24 04:27:02 PM PST 24
Peak memory 210048 kb
Host smart-d26a6847-07d4-4f02-af02-4de63063cd10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=893573949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.893573949
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2207815013
Short name T312
Test name
Test status
Simulation time 19619730 ps
CPU time 0.79 seconds
Started Jan 24 04:10:46 PM PST 24
Finished Jan 24 04:11:05 PM PST 24
Peak memory 201196 kb
Host smart-4e8aa2dd-13d7-41bd-8f95-1238c69c51b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207815013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2207815013
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.2574355601
Short name T545
Test name
Test status
Simulation time 16064092 ps
CPU time 0.71 seconds
Started Jan 24 04:11:28 PM PST 24
Finished Jan 24 04:11:30 PM PST 24
Peak memory 201264 kb
Host smart-ec7632ed-9c82-4a2a-a2f5-bad0f4d40246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574355601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.2574355601
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3730502354
Short name T787
Test name
Test status
Simulation time 91617065 ps
CPU time 1.08 seconds
Started Jan 24 04:20:33 PM PST 24
Finished Jan 24 04:20:36 PM PST 24
Peak memory 201304 kb
Host smart-f028c782-4e24-4296-8dd1-4179773d0951
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730502354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3730502354
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.641941790
Short name T645
Test name
Test status
Simulation time 32155629 ps
CPU time 0.84 seconds
Started Jan 24 04:11:08 PM PST 24
Finished Jan 24 04:11:22 PM PST 24
Peak memory 201280 kb
Host smart-5e2f85bf-120e-4533-82c2-36e2d9324d1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641941790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.641941790
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.2758861604
Short name T826
Test name
Test status
Simulation time 2157547047 ps
CPU time 9.72 seconds
Started Jan 24 04:24:49 PM PST 24
Finished Jan 24 04:25:00 PM PST 24
Peak memory 201680 kb
Host smart-1c4f71d3-73d3-454d-a8fd-02b8c3b7587b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758861604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.2758861604
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.822016412
Short name T868
Test name
Test status
Simulation time 1575576805 ps
CPU time 11.56 seconds
Started Jan 24 04:11:02 PM PST 24
Finished Jan 24 04:11:26 PM PST 24
Peak memory 201384 kb
Host smart-60114abe-88e8-411b-87d1-e4549496cebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822016412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_tim
eout.822016412
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.4204039029
Short name T280
Test name
Test status
Simulation time 49845186 ps
CPU time 0.89 seconds
Started Jan 24 04:33:54 PM PST 24
Finished Jan 24 04:33:58 PM PST 24
Peak memory 201320 kb
Host smart-92d33b89-bb63-497c-8461-dfb4d6bf5c2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204039029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.4204039029
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.51567730
Short name T565
Test name
Test status
Simulation time 60160320 ps
CPU time 0.88 seconds
Started Jan 24 04:11:02 PM PST 24
Finished Jan 24 04:11:15 PM PST 24
Peak memory 201084 kb
Host smart-966377fe-df19-4ce3-9745-992a79fb1174
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51567730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.51567730
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2916303781
Short name T619
Test name
Test status
Simulation time 330821447 ps
CPU time 1.96 seconds
Started Jan 24 04:11:21 PM PST 24
Finished Jan 24 04:11:26 PM PST 24
Peak memory 201196 kb
Host smart-6da6dcf7-52be-4b49-9d59-198d7801ba09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916303781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2916303781
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.3545459709
Short name T53
Test name
Test status
Simulation time 294376618 ps
CPU time 2.29 seconds
Started Jan 24 04:11:25 PM PST 24
Finished Jan 24 04:11:30 PM PST 24
Peak memory 215996 kb
Host smart-99509739-3cbf-4a49-b2a1-e0445303e518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545459709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.3545459709
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1060837610
Short name T516
Test name
Test status
Simulation time 21926558 ps
CPU time 0.84 seconds
Started Jan 24 04:11:08 PM PST 24
Finished Jan 24 04:11:22 PM PST 24
Peak memory 201284 kb
Host smart-c2f675de-c6ef-4250-a5a3-dceb9a085d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060837610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1060837610
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.409334176
Short name T958
Test name
Test status
Simulation time 3079733818 ps
CPU time 22.56 seconds
Started Jan 24 04:11:24 PM PST 24
Finished Jan 24 04:11:49 PM PST 24
Peak memory 201728 kb
Host smart-45b88941-127e-40de-b171-ecb09aba5525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409334176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.409334176
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2242392429
Short name T560
Test name
Test status
Simulation time 35413195 ps
CPU time 1.02 seconds
Started Jan 24 04:11:08 PM PST 24
Finished Jan 24 04:11:22 PM PST 24
Peak memory 201280 kb
Host smart-c3014fa0-3120-4f62-91b7-2f83ed4d4167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242392429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2242392429
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.332416843
Short name T841
Test name
Test status
Simulation time 31921451 ps
CPU time 0.79 seconds
Started Jan 24 04:24:41 PM PST 24
Finished Jan 24 04:24:43 PM PST 24
Peak memory 201260 kb
Host smart-67934fb1-3d11-42b3-8097-ad81c68445db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332416843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkm
gr_alert_test.332416843
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1697040983
Short name T952
Test name
Test status
Simulation time 77668578 ps
CPU time 1.05 seconds
Started Jan 24 04:58:08 PM PST 24
Finished Jan 24 04:58:13 PM PST 24
Peak memory 201304 kb
Host smart-ea64f1da-8e58-46a3-a123-185e5649b59f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697040983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1697040983
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2787144950
Short name T678
Test name
Test status
Simulation time 38720293 ps
CPU time 0.74 seconds
Started Jan 24 04:43:32 PM PST 24
Finished Jan 24 04:43:33 PM PST 24
Peak memory 200164 kb
Host smart-5745125d-885b-49dd-a186-b320d2026540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787144950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2787144950
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1146469821
Short name T299
Test name
Test status
Simulation time 34074354 ps
CPU time 0.89 seconds
Started Jan 24 04:14:03 PM PST 24
Finished Jan 24 04:14:08 PM PST 24
Peak memory 201308 kb
Host smart-608b7cb7-d114-4859-9755-4f7b85d93967
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146469821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1146469821
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.3402153219
Short name T160
Test name
Test status
Simulation time 34634088 ps
CPU time 0.89 seconds
Started Jan 24 04:13:44 PM PST 24
Finished Jan 24 04:13:46 PM PST 24
Peak memory 201276 kb
Host smart-a68615ea-5805-4b56-a7c5-36bc4c71c0a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402153219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3402153219
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1134376067
Short name T1
Test name
Test status
Simulation time 602338559 ps
CPU time 3.08 seconds
Started Jan 24 04:13:50 PM PST 24
Finished Jan 24 04:13:54 PM PST 24
Peak memory 201300 kb
Host smart-ea5c8103-96e2-4cc4-b16d-31909d16f466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134376067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1134376067
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.2830300656
Short name T31
Test name
Test status
Simulation time 2420667340 ps
CPU time 17.42 seconds
Started Jan 24 04:13:45 PM PST 24
Finished Jan 24 04:14:04 PM PST 24
Peak memory 201776 kb
Host smart-45698a57-99c0-4341-9128-8e3425b8f84e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830300656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.2830300656
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.17550192
Short name T603
Test name
Test status
Simulation time 18674178 ps
CPU time 0.79 seconds
Started Jan 24 06:16:34 PM PST 24
Finished Jan 24 06:16:36 PM PST 24
Peak memory 201192 kb
Host smart-896b2d72-45eb-45d7-89a9-e295825c850e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.clkmgr_idle_intersig_mubi.17550192
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3934034110
Short name T30
Test name
Test status
Simulation time 47816418 ps
CPU time 0.86 seconds
Started Jan 24 04:13:54 PM PST 24
Finished Jan 24 04:13:57 PM PST 24
Peak memory 201248 kb
Host smart-3a623a69-42cc-4a20-8dfe-e6f1da6bfc2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934034110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3934034110
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2776584285
Short name T610
Test name
Test status
Simulation time 78445026 ps
CPU time 0.93 seconds
Started Jan 24 04:13:59 PM PST 24
Finished Jan 24 04:14:07 PM PST 24
Peak memory 201276 kb
Host smart-5c33c3dd-9e57-4c18-9c3a-ad382883336e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776584285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.2776584285
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3246586885
Short name T393
Test name
Test status
Simulation time 15047194 ps
CPU time 0.73 seconds
Started Jan 24 04:34:13 PM PST 24
Finished Jan 24 04:34:20 PM PST 24
Peak memory 201172 kb
Host smart-855c3181-41c8-4e6f-8795-7a1e79a31d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246586885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3246586885
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.3057671003
Short name T968
Test name
Test status
Simulation time 832363519 ps
CPU time 3.44 seconds
Started Jan 24 04:14:05 PM PST 24
Finished Jan 24 04:14:18 PM PST 24
Peak memory 201476 kb
Host smart-418904e0-b267-4bc9-948b-06f569b7b0fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057671003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3057671003
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.1428906165
Short name T279
Test name
Test status
Simulation time 19584698 ps
CPU time 0.85 seconds
Started Jan 24 05:58:18 PM PST 24
Finished Jan 24 05:58:22 PM PST 24
Peak memory 201268 kb
Host smart-115010bc-bad7-4b7b-9942-8fd8a2b450e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428906165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1428906165
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1998856282
Short name T878
Test name
Test status
Simulation time 3756815845 ps
CPU time 26.08 seconds
Started Jan 24 04:14:00 PM PST 24
Finished Jan 24 04:14:33 PM PST 24
Peak memory 201736 kb
Host smart-59747058-30ab-4e9e-83d6-ff1c06e88bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998856282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1998856282
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.4109343528
Short name T150
Test name
Test status
Simulation time 260448245243 ps
CPU time 1177.57 seconds
Started Jan 24 04:14:03 PM PST 24
Finished Jan 24 04:33:45 PM PST 24
Peak memory 218160 kb
Host smart-f17791e7-35bf-4add-875b-b75a1439bf0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4109343528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.4109343528
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.920697524
Short name T394
Test name
Test status
Simulation time 70082540 ps
CPU time 0.99 seconds
Started Jan 24 04:13:52 PM PST 24
Finished Jan 24 04:13:55 PM PST 24
Peak memory 201280 kb
Host smart-1cb53589-0b83-4538-909d-5f2c189e889a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920697524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.920697524
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1826881454
Short name T871
Test name
Test status
Simulation time 15593390 ps
CPU time 0.76 seconds
Started Jan 24 04:14:10 PM PST 24
Finished Jan 24 04:14:19 PM PST 24
Peak memory 201232 kb
Host smart-e7456882-8a6a-4590-be49-94c334acb40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826881454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1826881454
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1443146500
Short name T914
Test name
Test status
Simulation time 36612277 ps
CPU time 0.8 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:22 PM PST 24
Peak memory 201288 kb
Host smart-7d70751b-e033-4d60-a705-f43522f3e9e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443146500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1443146500
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.2553629277
Short name T758
Test name
Test status
Simulation time 41280473 ps
CPU time 0.78 seconds
Started Jan 24 04:14:11 PM PST 24
Finished Jan 24 04:14:19 PM PST 24
Peak memory 201212 kb
Host smart-fae863e4-8a24-4a9e-86bf-2448eb6262c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553629277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2553629277
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2799467926
Short name T750
Test name
Test status
Simulation time 27813643 ps
CPU time 0.82 seconds
Started Jan 24 04:14:11 PM PST 24
Finished Jan 24 04:14:19 PM PST 24
Peak memory 201304 kb
Host smart-d6e79fa0-55ac-494a-ae1d-9cb736c81f3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799467926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2799467926
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.1509345052
Short name T722
Test name
Test status
Simulation time 77515626 ps
CPU time 1.01 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:20 PM PST 24
Peak memory 201324 kb
Host smart-602ba213-4a90-46c4-b4a7-4f03d5e24118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509345052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1509345052
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1559906596
Short name T109
Test name
Test status
Simulation time 1401614143 ps
CPU time 10.61 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:32 PM PST 24
Peak memory 200924 kb
Host smart-69c28b20-10ee-4a97-9112-f4710876113f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559906596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1559906596
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1855753329
Short name T776
Test name
Test status
Simulation time 1575914621 ps
CPU time 11.62 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:31 PM PST 24
Peak memory 201432 kb
Host smart-6151ed26-9bcd-4596-b0eb-31cf42c62897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855753329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1855753329
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.3849396833
Short name T703
Test name
Test status
Simulation time 35924673 ps
CPU time 1.09 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:22 PM PST 24
Peak memory 200912 kb
Host smart-103855d6-91ea-4ac3-bfc2-87fb42b298c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849396833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.3849396833
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1419807756
Short name T698
Test name
Test status
Simulation time 74709750 ps
CPU time 1.06 seconds
Started Jan 24 04:14:09 PM PST 24
Finished Jan 24 04:14:19 PM PST 24
Peak memory 201284 kb
Host smart-a7f53477-fcc6-437b-8177-f0b2bf05902a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419807756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1419807756
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3200773575
Short name T701
Test name
Test status
Simulation time 70958312 ps
CPU time 1 seconds
Started Jan 24 04:27:39 PM PST 24
Finished Jan 24 04:27:41 PM PST 24
Peak memory 201300 kb
Host smart-70e7b435-ed61-4152-a280-e000d3f091e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200773575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.3200773575
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.2912700334
Short name T924
Test name
Test status
Simulation time 25677414 ps
CPU time 0.76 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:20 PM PST 24
Peak memory 201172 kb
Host smart-1cc1c0d6-4bdd-4b48-b581-6356ae888ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912700334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2912700334
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.967409945
Short name T392
Test name
Test status
Simulation time 1173895131 ps
CPU time 4.57 seconds
Started Jan 24 04:14:10 PM PST 24
Finished Jan 24 04:14:23 PM PST 24
Peak memory 201436 kb
Host smart-537971d8-e45d-46f6-82dd-c4ba058b3cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967409945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.967409945
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.2424791860
Short name T492
Test name
Test status
Simulation time 21659604 ps
CPU time 0.88 seconds
Started Jan 24 04:14:05 PM PST 24
Finished Jan 24 04:14:15 PM PST 24
Peak memory 201320 kb
Host smart-f918d42a-f950-4561-94eb-e37822f71e45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424791860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.2424791860
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2432048426
Short name T503
Test name
Test status
Simulation time 3439336412 ps
CPU time 14.34 seconds
Started Jan 24 04:14:15 PM PST 24
Finished Jan 24 04:14:33 PM PST 24
Peak memory 201728 kb
Host smart-203e0fca-2c6b-4c83-8e93-883ae6380ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432048426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2432048426
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.188068931
Short name T965
Test name
Test status
Simulation time 235200795307 ps
CPU time 1390.58 seconds
Started Jan 24 04:14:12 PM PST 24
Finished Jan 24 04:37:29 PM PST 24
Peak memory 210064 kb
Host smart-063fdd69-c2fe-4982-ad66-c4f2078124e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=188068931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.188068931
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3132847726
Short name T466
Test name
Test status
Simulation time 21020416 ps
CPU time 0.82 seconds
Started Jan 24 04:14:11 PM PST 24
Finished Jan 24 04:14:19 PM PST 24
Peak memory 201296 kb
Host smart-0152a9af-1d3f-413b-a102-d25062d31a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132847726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3132847726
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.3169128760
Short name T369
Test name
Test status
Simulation time 15550357 ps
CPU time 0.74 seconds
Started Jan 24 04:14:29 PM PST 24
Finished Jan 24 04:14:32 PM PST 24
Peak memory 201248 kb
Host smart-0aae0e8f-45e0-45d7-a8cf-a0031c41bb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169128760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.3169128760
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.565678092
Short name T848
Test name
Test status
Simulation time 29352778 ps
CPU time 0.96 seconds
Started Jan 24 04:14:20 PM PST 24
Finished Jan 24 04:14:26 PM PST 24
Peak memory 201256 kb
Host smart-57723ee0-3a4a-42c4-bd39-d70d98ee3570
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565678092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.565678092
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.561137313
Short name T553
Test name
Test status
Simulation time 16112562 ps
CPU time 0.72 seconds
Started Jan 24 04:14:16 PM PST 24
Finished Jan 24 04:14:23 PM PST 24
Peak memory 200120 kb
Host smart-9a26f7ce-1b51-4113-950b-819ba94a42e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561137313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.561137313
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.40624104
Short name T915
Test name
Test status
Simulation time 25273075 ps
CPU time 0.91 seconds
Started Jan 24 04:14:29 PM PST 24
Finished Jan 24 04:14:32 PM PST 24
Peak memory 201256 kb
Host smart-195682af-e1de-4506-b2de-e37b15c1beb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40624104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.clkmgr_div_intersig_mubi.40624104
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.1572507452
Short name T430
Test name
Test status
Simulation time 28490126 ps
CPU time 0.9 seconds
Started Jan 24 04:14:19 PM PST 24
Finished Jan 24 04:14:26 PM PST 24
Peak memory 201292 kb
Host smart-40eefb0c-b5ea-4399-b8dc-023b1b689f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572507452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1572507452
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1231812474
Short name T404
Test name
Test status
Simulation time 2354567624 ps
CPU time 16.76 seconds
Started Jan 24 04:14:22 PM PST 24
Finished Jan 24 04:14:42 PM PST 24
Peak memory 201648 kb
Host smart-76e74366-be08-48b6-b208-ab52669894a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231812474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1231812474
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.208009260
Short name T493
Test name
Test status
Simulation time 1337674307 ps
CPU time 9.71 seconds
Started Jan 24 04:14:19 PM PST 24
Finished Jan 24 04:14:34 PM PST 24
Peak memory 201424 kb
Host smart-6f401c5d-b2c5-407e-8186-aac5f0236b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208009260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti
meout.208009260
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2098946279
Short name T955
Test name
Test status
Simulation time 67267811 ps
CPU time 1 seconds
Started Jan 24 04:14:19 PM PST 24
Finished Jan 24 04:14:26 PM PST 24
Peak memory 201252 kb
Host smart-d70158e5-9efd-459d-9287-c28693aa4e11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098946279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2098946279
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1876503608
Short name T771
Test name
Test status
Simulation time 23029867 ps
CPU time 0.83 seconds
Started Jan 24 04:14:22 PM PST 24
Finished Jan 24 04:14:27 PM PST 24
Peak memory 201280 kb
Host smart-51c59da3-bb72-4baf-9986-e82c20d2a9bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876503608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1876503608
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3796211189
Short name T483
Test name
Test status
Simulation time 37963435 ps
CPU time 0.79 seconds
Started Jan 24 04:14:21 PM PST 24
Finished Jan 24 04:14:26 PM PST 24
Peak memory 201296 kb
Host smart-1b724419-4e61-4042-8994-979c74a65b04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796211189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3796211189
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.908615789
Short name T463
Test name
Test status
Simulation time 12648451 ps
CPU time 0.76 seconds
Started Jan 24 04:14:22 PM PST 24
Finished Jan 24 04:14:27 PM PST 24
Peak memory 201152 kb
Host smart-0bccd724-1b9a-4ac0-b433-05ed00ae0bdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908615789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.908615789
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.973372427
Short name T612
Test name
Test status
Simulation time 421826179 ps
CPU time 1.92 seconds
Started Jan 24 04:14:36 PM PST 24
Finished Jan 24 04:14:40 PM PST 24
Peak memory 201320 kb
Host smart-aae6a664-3a64-4cb5-9cfc-b5ca8037915b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973372427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.973372427
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.4045578884
Short name T326
Test name
Test status
Simulation time 48462003 ps
CPU time 0.94 seconds
Started Jan 24 04:14:19 PM PST 24
Finished Jan 24 04:14:26 PM PST 24
Peak memory 201284 kb
Host smart-bcb5f894-35c5-4ebf-b3d1-2a25b857bd10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045578884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.4045578884
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.839383400
Short name T368
Test name
Test status
Simulation time 288647790 ps
CPU time 1.7 seconds
Started Jan 24 04:14:33 PM PST 24
Finished Jan 24 04:14:36 PM PST 24
Peak memory 200512 kb
Host smart-ec45b391-a159-43ba-a96e-f903efa68fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839383400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.839383400
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3694000751
Short name T487
Test name
Test status
Simulation time 26278383410 ps
CPU time 470.47 seconds
Started Jan 24 04:14:30 PM PST 24
Finished Jan 24 04:22:23 PM PST 24
Peak memory 218200 kb
Host smart-96ed681f-763a-4c34-a2e7-139a5b0b1cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3694000751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3694000751
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.2901484717
Short name T359
Test name
Test status
Simulation time 69373620 ps
CPU time 0.99 seconds
Started Jan 24 04:14:22 PM PST 24
Finished Jan 24 04:14:27 PM PST 24
Peak memory 201188 kb
Host smart-ad1c53de-e569-45c9-893d-17d86f8bc22d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901484717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2901484717
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.321910696
Short name T440
Test name
Test status
Simulation time 13789103 ps
CPU time 0.82 seconds
Started Jan 24 04:14:57 PM PST 24
Finished Jan 24 04:15:00 PM PST 24
Peak memory 201208 kb
Host smart-7d078073-c194-40c7-a86a-6e816897a351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321910696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm
gr_alert_test.321910696
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2378673148
Short name T845
Test name
Test status
Simulation time 44372238 ps
CPU time 0.86 seconds
Started Jan 24 04:14:38 PM PST 24
Finished Jan 24 04:14:42 PM PST 24
Peak memory 201240 kb
Host smart-a08c7d80-8a91-4d3b-bfb0-27901e0c7ec1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378673148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.2378673148
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.979720393
Short name T706
Test name
Test status
Simulation time 27484922 ps
CPU time 0.78 seconds
Started Jan 24 04:14:28 PM PST 24
Finished Jan 24 04:14:31 PM PST 24
Peak memory 201180 kb
Host smart-829e2216-5562-4a4b-b603-960c29fefd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979720393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.979720393
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2617312923
Short name T627
Test name
Test status
Simulation time 77761541 ps
CPU time 0.99 seconds
Started Jan 24 04:14:57 PM PST 24
Finished Jan 24 04:14:59 PM PST 24
Peak memory 201248 kb
Host smart-fa92c559-1be3-4d95-9196-43d64c8532f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617312923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2617312923
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.2162518122
Short name T446
Test name
Test status
Simulation time 14741041 ps
CPU time 0.72 seconds
Started Jan 24 04:14:36 PM PST 24
Finished Jan 24 04:14:39 PM PST 24
Peak memory 201296 kb
Host smart-6cf619dc-3d42-42ed-93f5-ef9a61a791e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162518122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2162518122
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.673078904
Short name T960
Test name
Test status
Simulation time 2475071329 ps
CPU time 18.72 seconds
Started Jan 24 04:14:34 PM PST 24
Finished Jan 24 04:14:55 PM PST 24
Peak memory 201628 kb
Host smart-9f5c7dec-5f14-4ade-9a84-5b03f8931503
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673078904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.673078904
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.4160632917
Short name T650
Test name
Test status
Simulation time 1946867512 ps
CPU time 10.35 seconds
Started Jan 24 04:14:33 PM PST 24
Finished Jan 24 04:14:45 PM PST 24
Peak memory 200528 kb
Host smart-e75eb2ce-ee86-424f-94a4-f9a5d96e086e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160632917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.4160632917
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.4105332178
Short name T59
Test name
Test status
Simulation time 13562645 ps
CPU time 0.72 seconds
Started Jan 24 04:14:36 PM PST 24
Finished Jan 24 04:14:39 PM PST 24
Peak memory 201244 kb
Host smart-b375ccba-7ab6-440c-b763-3fdfa5da5bae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105332178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.4105332178
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.733208625
Short name T308
Test name
Test status
Simulation time 58781395 ps
CPU time 0.86 seconds
Started Jan 24 04:14:34 PM PST 24
Finished Jan 24 04:14:36 PM PST 24
Peak memory 201240 kb
Host smart-d72ca30c-a6d0-4644-bcf5-aabeb2ebb7b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733208625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.733208625
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1364918701
Short name T805
Test name
Test status
Simulation time 14411708 ps
CPU time 0.74 seconds
Started Jan 24 04:14:36 PM PST 24
Finished Jan 24 04:14:38 PM PST 24
Peak memory 201168 kb
Host smart-b5500af3-e983-495a-ace0-d7c5e5f08a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364918701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1364918701
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.855662333
Short name T425
Test name
Test status
Simulation time 673920699 ps
CPU time 2.73 seconds
Started Jan 24 04:14:46 PM PST 24
Finished Jan 24 04:14:51 PM PST 24
Peak memory 201444 kb
Host smart-19fdf884-ea65-40c6-9589-10977fd3c402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855662333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.855662333
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2008991790
Short name T57
Test name
Test status
Simulation time 62463871 ps
CPU time 0.91 seconds
Started Jan 24 04:14:34 PM PST 24
Finished Jan 24 04:14:36 PM PST 24
Peak memory 201244 kb
Host smart-34b0e533-c145-498a-88a7-3173d131f86f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008991790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2008991790
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.4238660863
Short name T642
Test name
Test status
Simulation time 7749989682 ps
CPU time 38.78 seconds
Started Jan 24 04:14:48 PM PST 24
Finished Jan 24 04:15:29 PM PST 24
Peak memory 201692 kb
Host smart-c26d5e26-6194-4345-b06a-6b458e7c64b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238660863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.4238660863
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.773133833
Short name T886
Test name
Test status
Simulation time 80802086 ps
CPU time 1.03 seconds
Started Jan 24 04:14:30 PM PST 24
Finished Jan 24 04:14:33 PM PST 24
Peak memory 201232 kb
Host smart-20d141b2-3d12-4bc2-8a72-4744153cb511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773133833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.773133833
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.2528873351
Short name T759
Test name
Test status
Simulation time 15218948 ps
CPU time 0.73 seconds
Started Jan 24 04:15:11 PM PST 24
Finished Jan 24 04:15:13 PM PST 24
Peak memory 201224 kb
Host smart-b7bcb683-ffdc-4aba-86cf-94109fea35b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528873351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.2528873351
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1087500896
Short name T592
Test name
Test status
Simulation time 40221145 ps
CPU time 0.91 seconds
Started Jan 24 04:15:14 PM PST 24
Finished Jan 24 04:15:17 PM PST 24
Peak memory 201336 kb
Host smart-7f119749-a462-4063-8d55-e2fe6825018f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087500896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.1087500896
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.3134693306
Short name T653
Test name
Test status
Simulation time 21308829 ps
CPU time 0.7 seconds
Started Jan 24 04:15:03 PM PST 24
Finished Jan 24 04:15:06 PM PST 24
Peak memory 201188 kb
Host smart-ac9e2291-33a1-42a0-bcc4-3cec9867fb5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134693306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3134693306
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.3996485041
Short name T508
Test name
Test status
Simulation time 68570765 ps
CPU time 0.98 seconds
Started Jan 24 04:15:14 PM PST 24
Finished Jan 24 04:15:17 PM PST 24
Peak memory 201308 kb
Host smart-52d03f6d-1cb6-4ac1-970a-6ded48127071
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996485041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.3996485041
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.4063430362
Short name T373
Test name
Test status
Simulation time 25493969 ps
CPU time 0.89 seconds
Started Jan 24 04:14:57 PM PST 24
Finished Jan 24 04:14:59 PM PST 24
Peak memory 201292 kb
Host smart-2ebcd1a9-ce76-4313-8d95-351c10aa045d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063430362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.4063430362
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.779108727
Short name T806
Test name
Test status
Simulation time 1774971055 ps
CPU time 7.98 seconds
Started Jan 24 04:15:02 PM PST 24
Finished Jan 24 04:15:12 PM PST 24
Peak memory 201568 kb
Host smart-324361a2-121c-4b54-a251-aa7aa65ca045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779108727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.779108727
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.2868457264
Short name T533
Test name
Test status
Simulation time 998693812 ps
CPU time 4.64 seconds
Started Jan 24 04:14:53 PM PST 24
Finished Jan 24 04:15:00 PM PST 24
Peak memory 201432 kb
Host smart-583fa39a-ed9c-4b7d-a50a-3a0ecb2f80ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868457264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.2868457264
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1187843377
Short name T383
Test name
Test status
Simulation time 67214973 ps
CPU time 0.89 seconds
Started Jan 24 04:15:12 PM PST 24
Finished Jan 24 04:15:15 PM PST 24
Peak memory 201292 kb
Host smart-123bf2f3-3319-4f4f-a96e-71e50c32c6ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187843377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1187843377
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.867467230
Short name T839
Test name
Test status
Simulation time 32589010 ps
CPU time 0.82 seconds
Started Jan 24 04:15:12 PM PST 24
Finished Jan 24 04:15:15 PM PST 24
Peak memory 201300 kb
Host smart-351970a8-337c-49d2-8a04-0e381ad8d212
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867467230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_clk_byp_req_intersig_mubi.867467230
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3320676537
Short name T28
Test name
Test status
Simulation time 19325406 ps
CPU time 0.79 seconds
Started Jan 24 04:15:14 PM PST 24
Finished Jan 24 04:15:17 PM PST 24
Peak memory 201284 kb
Host smart-cd177514-a296-4dee-ac29-19491094b57c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320676537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3320676537
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.3549656357
Short name T930
Test name
Test status
Simulation time 30310586 ps
CPU time 0.77 seconds
Started Jan 24 04:14:57 PM PST 24
Finished Jan 24 04:14:59 PM PST 24
Peak memory 201128 kb
Host smart-a2ef36ca-abf6-4a0c-aded-bf4ef1e82e82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549656357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3549656357
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.2559327182
Short name T777
Test name
Test status
Simulation time 903880387 ps
CPU time 5.42 seconds
Started Jan 24 04:15:12 PM PST 24
Finished Jan 24 04:15:19 PM PST 24
Peak memory 201448 kb
Host smart-8897f736-51bd-4a37-ac95-8fd04293ec2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559327182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2559327182
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2615548988
Short name T673
Test name
Test status
Simulation time 22887597 ps
CPU time 0.9 seconds
Started Jan 24 04:15:02 PM PST 24
Finished Jan 24 04:15:05 PM PST 24
Peak memory 201316 kb
Host smart-c1e63114-fa77-4a21-a84a-2b5b12c364ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615548988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2615548988
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.3782708115
Short name T514
Test name
Test status
Simulation time 8180178468 ps
CPU time 57.4 seconds
Started Jan 24 04:15:15 PM PST 24
Finished Jan 24 04:16:14 PM PST 24
Peak memory 201752 kb
Host smart-f3fdd002-9792-4db9-acbc-f51aad26fcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782708115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.3782708115
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.2888835810
Short name T561
Test name
Test status
Simulation time 30151491151 ps
CPU time 267.39 seconds
Started Jan 24 04:15:12 PM PST 24
Finished Jan 24 04:19:41 PM PST 24
Peak memory 216192 kb
Host smart-55a618c5-8c44-4a10-a0cf-dd33f07328c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2888835810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2888835810
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.154147494
Short name T793
Test name
Test status
Simulation time 86733865 ps
CPU time 1.05 seconds
Started Jan 24 04:15:01 PM PST 24
Finished Jan 24 04:15:04 PM PST 24
Peak memory 201320 kb
Host smart-ad8c48c2-e5d9-415e-a6bb-72d1c66510df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154147494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.154147494
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.2332759962
Short name T844
Test name
Test status
Simulation time 15660094 ps
CPU time 0.76 seconds
Started Jan 24 04:15:24 PM PST 24
Finished Jan 24 04:15:27 PM PST 24
Peak memory 201224 kb
Host smart-f909e7da-559b-474b-b228-9020bb1b6d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332759962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.2332759962
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2849476618
Short name T663
Test name
Test status
Simulation time 30154920 ps
CPU time 0.92 seconds
Started Jan 24 04:15:26 PM PST 24
Finished Jan 24 04:15:30 PM PST 24
Peak memory 200532 kb
Host smart-db049fbf-b1fa-4e8b-a05f-460ba6453ec1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849476618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2849476618
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1853627342
Short name T909
Test name
Test status
Simulation time 18773088 ps
CPU time 0.74 seconds
Started Jan 24 04:15:23 PM PST 24
Finished Jan 24 04:15:25 PM PST 24
Peak memory 201208 kb
Host smart-20924dd8-9ec3-4e35-a080-ca5dcfe01f1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853627342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1853627342
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.984491724
Short name T800
Test name
Test status
Simulation time 13137660 ps
CPU time 0.74 seconds
Started Jan 24 04:15:24 PM PST 24
Finished Jan 24 04:15:27 PM PST 24
Peak memory 201296 kb
Host smart-1a589fe7-a6de-4261-b577-ad38f90615f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984491724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.984491724
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1780356358
Short name T587
Test name
Test status
Simulation time 20826050 ps
CPU time 0.87 seconds
Started Jan 24 04:15:18 PM PST 24
Finished Jan 24 04:15:20 PM PST 24
Peak memory 201320 kb
Host smart-254e1087-22d0-4695-b272-6af55efaad66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780356358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1780356358
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.2285617563
Short name T107
Test name
Test status
Simulation time 2241207204 ps
CPU time 16.22 seconds
Started Jan 24 04:15:14 PM PST 24
Finished Jan 24 04:15:32 PM PST 24
Peak memory 201660 kb
Host smart-2a2edbba-e965-4b2b-a96b-ef0fdefc523c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285617563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2285617563
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.258043002
Short name T630
Test name
Test status
Simulation time 633961508 ps
CPU time 2.57 seconds
Started Jan 24 04:15:11 PM PST 24
Finished Jan 24 04:15:15 PM PST 24
Peak memory 201424 kb
Host smart-a4738a6c-3862-4f56-aecb-2841230f6f82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258043002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_ti
meout.258043002
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.404970518
Short name T334
Test name
Test status
Simulation time 25001245 ps
CPU time 0.9 seconds
Started Jan 24 04:15:24 PM PST 24
Finished Jan 24 04:15:28 PM PST 24
Peak memory 201288 kb
Host smart-3d813ffa-0a11-49ba-abb8-9b1274ab8c50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404970518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.404970518
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.4293235141
Short name T900
Test name
Test status
Simulation time 16747611 ps
CPU time 0.76 seconds
Started Jan 24 04:15:21 PM PST 24
Finished Jan 24 04:15:23 PM PST 24
Peak memory 201292 kb
Host smart-b87ab0ee-c6aa-4410-a855-37243c3d3376
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293235141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.4293235141
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.712479256
Short name T589
Test name
Test status
Simulation time 26885318 ps
CPU time 0.87 seconds
Started Jan 24 04:15:22 PM PST 24
Finished Jan 24 04:15:24 PM PST 24
Peak memory 201292 kb
Host smart-b45ea587-236c-4276-a13b-30a936897a09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712479256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_ctrl_intersig_mubi.712479256
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.843961775
Short name T358
Test name
Test status
Simulation time 16071784 ps
CPU time 0.78 seconds
Started Jan 24 04:15:10 PM PST 24
Finished Jan 24 04:15:12 PM PST 24
Peak memory 201120 kb
Host smart-987a4be8-2adf-40a1-aa10-48ee5195f0e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843961775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.843961775
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.4231052599
Short name T639
Test name
Test status
Simulation time 606598943 ps
CPU time 3.22 seconds
Started Jan 24 04:15:20 PM PST 24
Finished Jan 24 04:15:25 PM PST 24
Peak memory 201432 kb
Host smart-8c870f23-56b9-41b8-9366-4c3b212879a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231052599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.4231052599
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1986880971
Short name T556
Test name
Test status
Simulation time 60405805 ps
CPU time 0.91 seconds
Started Jan 24 04:15:12 PM PST 24
Finished Jan 24 04:15:15 PM PST 24
Peak memory 201264 kb
Host smart-ab5367d1-bebe-4551-b055-4a2f6b33d92c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986880971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1986880971
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3522951925
Short name T416
Test name
Test status
Simulation time 8999570857 ps
CPU time 46.84 seconds
Started Jan 24 04:15:26 PM PST 24
Finished Jan 24 04:16:16 PM PST 24
Peak memory 200856 kb
Host smart-7b2c7410-cc97-4d8b-bff5-4234baa5467c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522951925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3522951925
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.2250667498
Short name T762
Test name
Test status
Simulation time 107388948769 ps
CPU time 701.92 seconds
Started Jan 24 04:15:29 PM PST 24
Finished Jan 24 04:27:14 PM PST 24
Peak memory 210024 kb
Host smart-07465ad2-4a36-485b-ab0c-b9996095cf00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2250667498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.2250667498
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2753844890
Short name T887
Test name
Test status
Simulation time 24497369 ps
CPU time 0.88 seconds
Started Jan 24 04:15:23 PM PST 24
Finished Jan 24 04:15:25 PM PST 24
Peak memory 201320 kb
Host smart-c2d5ac56-c6d8-4a01-8780-b79d082a2e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753844890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2753844890
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.591114844
Short name T822
Test name
Test status
Simulation time 80198277 ps
CPU time 0.93 seconds
Started Jan 24 04:15:40 PM PST 24
Finished Jan 24 04:15:43 PM PST 24
Peak memory 201276 kb
Host smart-ecf7bd20-1a59-437c-9050-4d34fc107758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591114844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.591114844
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.2140667907
Short name T321
Test name
Test status
Simulation time 45093003 ps
CPU time 0.87 seconds
Started Jan 24 04:54:33 PM PST 24
Finished Jan 24 04:54:35 PM PST 24
Peak memory 201296 kb
Host smart-94ed3791-073b-4a14-b13b-962e032a927a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140667907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.2140667907
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.3044031403
Short name T46
Test name
Test status
Simulation time 16792183 ps
CPU time 0.73 seconds
Started Jan 24 04:15:23 PM PST 24
Finished Jan 24 04:15:26 PM PST 24
Peak memory 200104 kb
Host smart-ed27ddb2-20d1-49e9-9784-93738b47cd61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044031403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3044031403
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1491887513
Short name T772
Test name
Test status
Simulation time 36930608 ps
CPU time 0.89 seconds
Started Jan 24 04:15:34 PM PST 24
Finished Jan 24 04:15:41 PM PST 24
Peak memory 201304 kb
Host smart-23209e1d-8dd1-46b3-9726-5459ca6ab080
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491887513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.1491887513
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.4108956347
Short name T947
Test name
Test status
Simulation time 13654721 ps
CPU time 0.76 seconds
Started Jan 24 04:15:25 PM PST 24
Finished Jan 24 04:15:28 PM PST 24
Peak memory 201312 kb
Host smart-f3401727-7253-4249-b56e-dbd71d089c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108956347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.4108956347
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.3264093992
Short name T584
Test name
Test status
Simulation time 2472060961 ps
CPU time 10.23 seconds
Started Jan 24 04:15:25 PM PST 24
Finished Jan 24 04:15:37 PM PST 24
Peak memory 201632 kb
Host smart-422e8640-978c-4523-93b7-7693d061cb2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264093992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3264093992
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.901322610
Short name T742
Test name
Test status
Simulation time 425161072 ps
CPU time 2.07 seconds
Started Jan 24 04:15:29 PM PST 24
Finished Jan 24 04:15:34 PM PST 24
Peak memory 201356 kb
Host smart-accfcc75-8675-4ce7-ae2d-a0687d27a14d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901322610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti
meout.901322610
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3578285299
Short name T879
Test name
Test status
Simulation time 60633110 ps
CPU time 0.92 seconds
Started Jan 24 04:15:25 PM PST 24
Finished Jan 24 04:15:28 PM PST 24
Peak memory 201268 kb
Host smart-1c198213-a7d8-4e52-85f5-d88f912ee987
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578285299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.3578285299
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1852464395
Short name T420
Test name
Test status
Simulation time 39795952 ps
CPU time 0.78 seconds
Started Jan 24 04:15:32 PM PST 24
Finished Jan 24 04:15:39 PM PST 24
Peak memory 201240 kb
Host smart-a4cc59dd-9722-4891-947a-8c0d2a6a88c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852464395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1852464395
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3491943775
Short name T486
Test name
Test status
Simulation time 31905588 ps
CPU time 0.93 seconds
Started Jan 24 04:15:24 PM PST 24
Finished Jan 24 04:15:28 PM PST 24
Peak memory 201316 kb
Host smart-e74b5ebd-30ae-4d60-a237-7c337e5310e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491943775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3491943775
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.1274917339
Short name T525
Test name
Test status
Simulation time 47755839 ps
CPU time 0.89 seconds
Started Jan 24 04:15:23 PM PST 24
Finished Jan 24 04:15:26 PM PST 24
Peak memory 201168 kb
Host smart-fa35bdef-5bb2-427d-a24b-b80d04489be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274917339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1274917339
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.1315433692
Short name T93
Test name
Test status
Simulation time 643282452 ps
CPU time 2.65 seconds
Started Jan 24 04:15:30 PM PST 24
Finished Jan 24 04:15:35 PM PST 24
Peak memory 201376 kb
Host smart-9c427f81-c79b-4f33-8ef1-5abef5a5f788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315433692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1315433692
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2239557294
Short name T24
Test name
Test status
Simulation time 19293092 ps
CPU time 0.8 seconds
Started Jan 24 04:15:26 PM PST 24
Finished Jan 24 04:15:30 PM PST 24
Peak memory 201192 kb
Host smart-a27d52c3-b068-4f1d-ba97-2d3011f22baf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239557294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2239557294
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.220115863
Short name T654
Test name
Test status
Simulation time 930977719 ps
CPU time 4.14 seconds
Started Jan 24 04:15:31 PM PST 24
Finished Jan 24 04:15:37 PM PST 24
Peak memory 201392 kb
Host smart-25ad90f9-4834-4135-8997-88729179f9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220115863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.220115863
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2616664925
Short name T858
Test name
Test status
Simulation time 46841318903 ps
CPU time 873.45 seconds
Started Jan 24 04:26:53 PM PST 24
Finished Jan 24 04:41:30 PM PST 24
Peak memory 218184 kb
Host smart-dc5d4af6-296f-40a5-a716-cb700156ee95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2616664925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2616664925
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.2005368355
Short name T537
Test name
Test status
Simulation time 242326947 ps
CPU time 1.5 seconds
Started Jan 24 04:15:29 PM PST 24
Finished Jan 24 04:15:33 PM PST 24
Peak memory 201116 kb
Host smart-a862e1ad-7068-4984-a047-11eb3fc6f34b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005368355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2005368355
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.1068272302
Short name T795
Test name
Test status
Simulation time 38420510 ps
CPU time 0.86 seconds
Started Jan 24 04:16:01 PM PST 24
Finished Jan 24 04:16:03 PM PST 24
Peak memory 201252 kb
Host smart-7ba1abb5-9dee-49ab-aa17-d4226af3fdf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068272302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.1068272302
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.324647441
Short name T468
Test name
Test status
Simulation time 23070938 ps
CPU time 0.88 seconds
Started Jan 24 04:15:49 PM PST 24
Finished Jan 24 04:15:51 PM PST 24
Peak memory 201308 kb
Host smart-bcb44ad3-7db4-4844-91ba-3ce9c6c940ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324647441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.324647441
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.2264960975
Short name T447
Test name
Test status
Simulation time 26125785 ps
CPU time 0.71 seconds
Started Jan 24 04:15:55 PM PST 24
Finished Jan 24 04:15:57 PM PST 24
Peak memory 200064 kb
Host smart-c36ef7f8-6992-4b20-be25-121b52964521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264960975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.2264960975
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.368856304
Short name T752
Test name
Test status
Simulation time 60232550 ps
CPU time 0.91 seconds
Started Jan 24 04:15:54 PM PST 24
Finished Jan 24 04:15:56 PM PST 24
Peak memory 201272 kb
Host smart-54382e92-d30d-4007-aa79-57da1f1be150
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368856304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_div_intersig_mubi.368856304
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1836571845
Short name T544
Test name
Test status
Simulation time 45763169 ps
CPU time 0.95 seconds
Started Jan 24 04:15:31 PM PST 24
Finished Jan 24 04:15:34 PM PST 24
Peak memory 201320 kb
Host smart-399b0a18-4823-4261-b4c6-3e870c54d191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836571845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1836571845
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2216053938
Short name T760
Test name
Test status
Simulation time 1113327064 ps
CPU time 4.59 seconds
Started Jan 24 04:15:32 PM PST 24
Finished Jan 24 04:15:43 PM PST 24
Peak memory 201408 kb
Host smart-12155e95-0a41-4ac7-a41c-f6fda3f2ffaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216053938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2216053938
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3044390492
Short name T880
Test name
Test status
Simulation time 83726734 ps
CPU time 1.14 seconds
Started Jan 24 04:15:47 PM PST 24
Finished Jan 24 04:15:50 PM PST 24
Peak memory 201284 kb
Host smart-0c3c2347-069c-4b2a-9f11-aaf90badca07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044390492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.3044390492
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3883165117
Short name T785
Test name
Test status
Simulation time 28588459 ps
CPU time 0.9 seconds
Started Jan 24 04:15:48 PM PST 24
Finished Jan 24 04:15:51 PM PST 24
Peak memory 201292 kb
Host smart-a29865b9-0e86-4b77-a541-d19442f9a33a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883165117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.3883165117
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2700474931
Short name T923
Test name
Test status
Simulation time 19694277 ps
CPU time 0.81 seconds
Started Jan 24 04:15:47 PM PST 24
Finished Jan 24 04:15:49 PM PST 24
Peak memory 201300 kb
Host smart-341fc26f-f7cd-4e20-9692-43594d878902
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700474931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.2700474931
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.3032396289
Short name T908
Test name
Test status
Simulation time 974438630 ps
CPU time 4.51 seconds
Started Jan 24 04:15:48 PM PST 24
Finished Jan 24 04:15:54 PM PST 24
Peak memory 201504 kb
Host smart-4f5124a5-d43d-4821-87a8-dad727b85d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032396289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3032396289
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.597146009
Short name T737
Test name
Test status
Simulation time 42717850 ps
CPU time 0.97 seconds
Started Jan 24 04:36:42 PM PST 24
Finished Jan 24 04:36:45 PM PST 24
Peak memory 201304 kb
Host smart-74a69c5d-b54e-47dd-8015-64c0985709f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597146009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.597146009
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.456864159
Short name T661
Test name
Test status
Simulation time 7077237902 ps
CPU time 31.69 seconds
Started Jan 24 04:16:01 PM PST 24
Finished Jan 24 04:16:34 PM PST 24
Peak memory 201708 kb
Host smart-7afbee7d-9007-4e20-b7d0-88a4cfef5f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456864159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.456864159
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.3753250827
Short name T894
Test name
Test status
Simulation time 31421275588 ps
CPU time 420.05 seconds
Started Jan 24 04:15:53 PM PST 24
Finished Jan 24 04:22:54 PM PST 24
Peak memory 218128 kb
Host smart-cf5efe64-dcde-4a71-ba48-75786fce0616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3753250827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.3753250827
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.1655776109
Short name T647
Test name
Test status
Simulation time 70297018 ps
CPU time 1.02 seconds
Started Jan 24 05:27:45 PM PST 24
Finished Jan 24 05:27:52 PM PST 24
Peak memory 201320 kb
Host smart-15b8cec2-c5b6-4846-b49f-b0b75e7e464a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655776109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1655776109
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.3166980604
Short name T378
Test name
Test status
Simulation time 24441051 ps
CPU time 0.78 seconds
Started Jan 24 04:16:11 PM PST 24
Finished Jan 24 04:16:13 PM PST 24
Peak memory 201240 kb
Host smart-7e40ea90-4307-437e-9ff0-a266c2901483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166980604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.3166980604
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1368177409
Short name T307
Test name
Test status
Simulation time 23963646 ps
CPU time 0.88 seconds
Started Jan 24 04:32:41 PM PST 24
Finished Jan 24 04:32:43 PM PST 24
Peak memory 201304 kb
Host smart-d5d5d8f4-6162-4f19-9d28-94338e98668a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368177409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1368177409
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.1821147563
Short name T534
Test name
Test status
Simulation time 16368593 ps
CPU time 0.72 seconds
Started Jan 24 04:16:09 PM PST 24
Finished Jan 24 04:16:12 PM PST 24
Peak memory 201212 kb
Host smart-991803e0-2664-43b9-b7e4-2bcfc4cbe212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821147563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1821147563
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.199851083
Short name T686
Test name
Test status
Simulation time 20654651 ps
CPU time 0.8 seconds
Started Jan 24 04:16:12 PM PST 24
Finished Jan 24 04:16:15 PM PST 24
Peak memory 201308 kb
Host smart-875bc1d3-83e8-490f-92a8-325765f7e84a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199851083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_div_intersig_mubi.199851083
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.1075476793
Short name T948
Test name
Test status
Simulation time 23464525 ps
CPU time 0.88 seconds
Started Jan 24 04:16:00 PM PST 24
Finished Jan 24 04:16:03 PM PST 24
Peak memory 201332 kb
Host smart-51f493ec-f36a-440c-951d-fde683022a04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075476793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.1075476793
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.666071243
Short name T11
Test name
Test status
Simulation time 2060592600 ps
CPU time 8.92 seconds
Started Jan 24 04:15:59 PM PST 24
Finished Jan 24 04:16:10 PM PST 24
Peak memory 201500 kb
Host smart-59d779bc-5ad6-4f2a-9df2-021aedddfda0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666071243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.666071243
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.1137489900
Short name T921
Test name
Test status
Simulation time 1937676423 ps
CPU time 9.28 seconds
Started Jan 24 04:15:59 PM PST 24
Finished Jan 24 04:16:10 PM PST 24
Peak memory 201372 kb
Host smart-2b028944-3743-492e-bbd5-af0107aded55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137489900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.1137489900
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1537424792
Short name T672
Test name
Test status
Simulation time 25564335 ps
CPU time 0.92 seconds
Started Jan 24 04:16:08 PM PST 24
Finished Jan 24 04:16:10 PM PST 24
Peak memory 201308 kb
Host smart-587cda1a-d611-428e-9dbc-21c661692531
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537424792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1537424792
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2322344207
Short name T590
Test name
Test status
Simulation time 23320918 ps
CPU time 0.87 seconds
Started Jan 24 04:16:14 PM PST 24
Finished Jan 24 04:16:16 PM PST 24
Peak memory 201312 kb
Host smart-665cad4a-6cbd-4e86-8ad5-bb89b2bf1d20
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322344207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2322344207
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2339387860
Short name T631
Test name
Test status
Simulation time 16305918 ps
CPU time 0.79 seconds
Started Jan 24 04:16:08 PM PST 24
Finished Jan 24 04:16:10 PM PST 24
Peak memory 201292 kb
Host smart-46527158-86a0-45e7-9566-11d1d29b3622
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339387860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2339387860
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2194110989
Short name T899
Test name
Test status
Simulation time 14734968 ps
CPU time 0.75 seconds
Started Jan 24 04:15:58 PM PST 24
Finished Jan 24 04:16:00 PM PST 24
Peak memory 201228 kb
Host smart-b94011d1-94d4-4a60-8069-87ff23cf3f8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194110989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2194110989
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3215489551
Short name T741
Test name
Test status
Simulation time 238890090 ps
CPU time 1.91 seconds
Started Jan 24 04:16:12 PM PST 24
Finished Jan 24 04:16:15 PM PST 24
Peak memory 201260 kb
Host smart-831f4617-b1a6-4796-8e0f-1885ddafee17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215489551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3215489551
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2134768074
Short name T485
Test name
Test status
Simulation time 26066096 ps
CPU time 0.85 seconds
Started Jan 24 04:15:58 PM PST 24
Finished Jan 24 04:16:01 PM PST 24
Peak memory 201244 kb
Host smart-f6ff0127-7808-4e34-b3d8-9085220cd9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134768074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2134768074
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.4272014349
Short name T329
Test name
Test status
Simulation time 5489235562 ps
CPU time 24.53 seconds
Started Jan 24 04:16:11 PM PST 24
Finished Jan 24 04:16:37 PM PST 24
Peak memory 201720 kb
Host smart-ced9dfc5-b908-42dd-bfd6-3b8890ef1645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272014349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.4272014349
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.2727931274
Short name T715
Test name
Test status
Simulation time 465318896281 ps
CPU time 1528.05 seconds
Started Jan 24 04:16:14 PM PST 24
Finished Jan 24 04:41:43 PM PST 24
Peak memory 218212 kb
Host smart-15ab8bd0-fc18-494c-a993-5d4b863fbd87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2727931274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.2727931274
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.68726163
Short name T509
Test name
Test status
Simulation time 49428772 ps
CPU time 1.02 seconds
Started Jan 24 04:16:13 PM PST 24
Finished Jan 24 04:16:15 PM PST 24
Peak memory 201312 kb
Host smart-0f04b858-2f78-4858-b298-dad01e80012f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68726163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.68726163
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3254672364
Short name T385
Test name
Test status
Simulation time 48343888 ps
CPU time 0.87 seconds
Started Jan 24 04:45:29 PM PST 24
Finished Jan 24 04:45:31 PM PST 24
Peak memory 201320 kb
Host smart-3053cd71-d865-4ac3-99a9-3d70c6fe524a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254672364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3254672364
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1145716623
Short name T366
Test name
Test status
Simulation time 15369994 ps
CPU time 0.74 seconds
Started Jan 24 06:49:58 PM PST 24
Finished Jan 24 06:49:59 PM PST 24
Peak memory 201292 kb
Host smart-6577a699-af9a-4566-93f4-bb92462c4f2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145716623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1145716623
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1510860218
Short name T964
Test name
Test status
Simulation time 15331229 ps
CPU time 0.72 seconds
Started Jan 24 04:16:23 PM PST 24
Finished Jan 24 04:16:25 PM PST 24
Peak memory 200116 kb
Host smart-2e7c51da-2770-4d78-a59a-28f321338bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510860218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1510860218
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1691688062
Short name T905
Test name
Test status
Simulation time 21876000 ps
CPU time 0.81 seconds
Started Jan 24 04:16:23 PM PST 24
Finished Jan 24 04:16:25 PM PST 24
Peak memory 201300 kb
Host smart-35f611fa-c421-4f69-b16c-625eb04f17ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691688062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1691688062
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.1599200240
Short name T934
Test name
Test status
Simulation time 30552174 ps
CPU time 0.84 seconds
Started Jan 24 04:16:10 PM PST 24
Finished Jan 24 04:16:13 PM PST 24
Peak memory 201320 kb
Host smart-e4924130-54f8-4aac-9d26-a6c3a86507dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599200240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1599200240
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3440985914
Short name T935
Test name
Test status
Simulation time 2482212487 ps
CPU time 13.55 seconds
Started Jan 24 04:16:18 PM PST 24
Finished Jan 24 04:16:33 PM PST 24
Peak memory 201672 kb
Host smart-2257b488-0e23-44b5-9433-29c34382a69b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440985914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3440985914
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.4096706577
Short name T350
Test name
Test status
Simulation time 167224625 ps
CPU time 1.29 seconds
Started Jan 24 04:16:17 PM PST 24
Finished Jan 24 04:16:21 PM PST 24
Peak memory 201340 kb
Host smart-d8db09fd-ce87-44f5-bdd4-6627104525d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096706577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.4096706577
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1659040523
Short name T502
Test name
Test status
Simulation time 20557716 ps
CPU time 0.81 seconds
Started Jan 24 05:06:18 PM PST 24
Finished Jan 24 05:06:33 PM PST 24
Peak memory 201236 kb
Host smart-8494dd06-d646-4df8-a979-b9f090e96ad3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659040523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.1659040523
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2471795853
Short name T744
Test name
Test status
Simulation time 73510013 ps
CPU time 0.9 seconds
Started Jan 24 04:16:18 PM PST 24
Finished Jan 24 04:16:22 PM PST 24
Peak memory 201244 kb
Host smart-8c5122a4-49c6-40e6-9b8f-9da3c4daa003
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471795853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2471795853
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3848265231
Short name T669
Test name
Test status
Simulation time 60418385 ps
CPU time 0.94 seconds
Started Jan 24 04:41:54 PM PST 24
Finished Jan 24 04:41:58 PM PST 24
Peak memory 201312 kb
Host smart-e43b3786-ed18-417f-8f11-5c0cc6638232
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848265231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.3848265231
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.173074317
Short name T798
Test name
Test status
Simulation time 17808477 ps
CPU time 0.75 seconds
Started Jan 24 04:16:18 PM PST 24
Finished Jan 24 04:16:21 PM PST 24
Peak memory 201120 kb
Host smart-a7e58363-6bf5-41f3-8a5c-5a84fe19620b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173074317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.173074317
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.599853441
Short name T714
Test name
Test status
Simulation time 572495454 ps
CPU time 2.68 seconds
Started Jan 24 04:16:15 PM PST 24
Finished Jan 24 04:16:19 PM PST 24
Peak memory 201228 kb
Host smart-e27e5382-9a0b-4a0f-8bff-032c1ccb6703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599853441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.599853441
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2314232444
Short name T363
Test name
Test status
Simulation time 38111069 ps
CPU time 0.98 seconds
Started Jan 24 04:16:08 PM PST 24
Finished Jan 24 04:16:10 PM PST 24
Peak memory 201188 kb
Host smart-b4468ea9-c400-4f62-b759-640e41a8fa38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314232444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2314232444
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1059908730
Short name T683
Test name
Test status
Simulation time 7750010085 ps
CPU time 39.91 seconds
Started Jan 24 04:23:33 PM PST 24
Finished Jan 24 04:24:14 PM PST 24
Peak memory 201692 kb
Host smart-31cadbca-a9bf-41ea-bcb1-580f51d441e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059908730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1059908730
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.4257475256
Short name T43
Test name
Test status
Simulation time 25583677557 ps
CPU time 475.11 seconds
Started Jan 24 06:30:39 PM PST 24
Finished Jan 24 06:38:37 PM PST 24
Peak memory 210112 kb
Host smart-006d0fb4-805d-496e-a922-389c2de5143e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4257475256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.4257475256
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.23889119
Short name T676
Test name
Test status
Simulation time 15832482 ps
CPU time 0.78 seconds
Started Jan 24 04:16:17 PM PST 24
Finished Jan 24 04:16:20 PM PST 24
Peak memory 201188 kb
Host smart-30644838-fa90-4aff-b7ac-a24a58b9c44a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.23889119
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.1191096828
Short name T684
Test name
Test status
Simulation time 19294692 ps
CPU time 0.83 seconds
Started Jan 24 04:29:21 PM PST 24
Finished Jan 24 04:29:23 PM PST 24
Peak memory 201212 kb
Host smart-3ab0f0a5-5bfc-4516-a2ed-a0fc8f367b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191096828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.1191096828
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3944119305
Short name T22
Test name
Test status
Simulation time 80643595 ps
CPU time 1.08 seconds
Started Jan 24 04:11:31 PM PST 24
Finished Jan 24 04:11:34 PM PST 24
Peak memory 201300 kb
Host smart-852026e1-5ebb-4a2e-9f60-068a6da58ff2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944119305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.3944119305
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2364874068
Short name T622
Test name
Test status
Simulation time 19701312 ps
CPU time 0.72 seconds
Started Jan 24 04:11:25 PM PST 24
Finished Jan 24 04:11:28 PM PST 24
Peak memory 199612 kb
Host smart-08e9ea09-c8b2-4417-add4-b1d06d1508a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364874068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2364874068
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.4104329629
Short name T518
Test name
Test status
Simulation time 27577279 ps
CPU time 0.93 seconds
Started Jan 24 04:24:00 PM PST 24
Finished Jan 24 04:24:03 PM PST 24
Peak memory 201344 kb
Host smart-1ea9b4b6-5d2e-4439-a524-edbcc7e9fe4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104329629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.4104329629
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.3802501518
Short name T403
Test name
Test status
Simulation time 56326200 ps
CPU time 0.93 seconds
Started Jan 24 04:11:28 PM PST 24
Finished Jan 24 04:11:31 PM PST 24
Peak memory 201300 kb
Host smart-7cd4f1c2-175c-46f4-b670-dcf135a4bb2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802501518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3802501518
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2429820511
Short name T25
Test name
Test status
Simulation time 1422449583 ps
CPU time 6.88 seconds
Started Jan 24 04:11:25 PM PST 24
Finished Jan 24 04:11:35 PM PST 24
Peak memory 201236 kb
Host smart-08f092b3-3833-4d4e-b6c2-782b25ac7038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429820511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2429820511
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.2461967958
Short name T434
Test name
Test status
Simulation time 981929726 ps
CPU time 5.15 seconds
Started Jan 24 04:11:21 PM PST 24
Finished Jan 24 04:11:29 PM PST 24
Peak memory 201368 kb
Host smart-fe1cdafd-4b65-4a51-91ed-3822732b2e3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461967958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.2461967958
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1413150002
Short name T583
Test name
Test status
Simulation time 53354860 ps
CPU time 0.91 seconds
Started Jan 24 04:11:25 PM PST 24
Finished Jan 24 04:11:29 PM PST 24
Peak memory 201020 kb
Host smart-70a31415-8592-4882-9a0d-1399ebdd9afc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413150002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1413150002
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.21778413
Short name T16
Test name
Test status
Simulation time 19506778 ps
CPU time 0.81 seconds
Started Jan 24 04:11:32 PM PST 24
Finished Jan 24 04:11:35 PM PST 24
Peak memory 201300 kb
Host smart-81ec6f14-bd0c-4548-9ea7-4e92985ae2ed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_lc_clk_byp_req_intersig_mubi.21778413
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.535222419
Short name T353
Test name
Test status
Simulation time 48901736 ps
CPU time 0.85 seconds
Started Jan 24 04:11:33 PM PST 24
Finished Jan 24 04:11:36 PM PST 24
Peak memory 201308 kb
Host smart-3116df98-e1fe-4dea-8f8a-0e80768b14f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535222419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_ctrl_intersig_mubi.535222419
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1729213476
Short name T355
Test name
Test status
Simulation time 32906257 ps
CPU time 0.77 seconds
Started Jan 24 04:11:23 PM PST 24
Finished Jan 24 04:11:26 PM PST 24
Peak memory 201184 kb
Host smart-84f50378-82ad-49a9-bbe7-7b7fc475744c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729213476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1729213476
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.491819021
Short name T815
Test name
Test status
Simulation time 660399224 ps
CPU time 2.81 seconds
Started Jan 24 04:11:38 PM PST 24
Finished Jan 24 04:11:43 PM PST 24
Peak memory 201256 kb
Host smart-960bdd4e-a30a-425e-acdd-eec3e71f2e07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491819021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.491819021
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2047130105
Short name T54
Test name
Test status
Simulation time 257830292 ps
CPU time 2.66 seconds
Started Jan 24 04:11:38 PM PST 24
Finished Jan 24 04:11:43 PM PST 24
Peak memory 216060 kb
Host smart-5f384449-f6fd-43f2-b760-9b9e8f252560
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047130105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2047130105
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3711161987
Short name T570
Test name
Test status
Simulation time 59245072 ps
CPU time 1.01 seconds
Started Jan 24 04:11:25 PM PST 24
Finished Jan 24 04:11:29 PM PST 24
Peak memory 200844 kb
Host smart-7107757e-dfe9-4964-ad80-2f8659106f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711161987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3711161987
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.1520941188
Short name T666
Test name
Test status
Simulation time 5144237240 ps
CPU time 27.01 seconds
Started Jan 24 04:11:38 PM PST 24
Finished Jan 24 04:12:08 PM PST 24
Peak memory 201672 kb
Host smart-923995d2-682b-4721-bcb4-255de52b2651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520941188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.1520941188
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.1663186401
Short name T515
Test name
Test status
Simulation time 44007680091 ps
CPU time 812.27 seconds
Started Jan 24 04:11:33 PM PST 24
Finished Jan 24 04:25:07 PM PST 24
Peak memory 210024 kb
Host smart-8f658bc5-c17b-4fd7-a975-707f77c399f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1663186401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.1663186401
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.clkmgr_trans.3223526026
Short name T372
Test name
Test status
Simulation time 118042046 ps
CPU time 1.09 seconds
Started Jan 24 04:11:22 PM PST 24
Finished Jan 24 04:11:25 PM PST 24
Peak memory 201184 kb
Host smart-cae10974-20e2-40f9-b424-a0b61bcc95b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223526026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3223526026
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3130687442
Short name T946
Test name
Test status
Simulation time 12463630 ps
CPU time 0.72 seconds
Started Jan 24 04:16:42 PM PST 24
Finished Jan 24 04:16:44 PM PST 24
Peak memory 201308 kb
Host smart-43929788-e60e-4f0c-a9e6-b5c92a511575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130687442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3130687442
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1389884703
Short name T643
Test name
Test status
Simulation time 43990055 ps
CPU time 0.94 seconds
Started Jan 24 04:40:14 PM PST 24
Finished Jan 24 04:40:16 PM PST 24
Peak memory 201308 kb
Host smart-732aa5a8-6647-4f74-a35a-3e53ab297fb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389884703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.1389884703
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1940752518
Short name T136
Test name
Test status
Simulation time 14904998 ps
CPU time 0.72 seconds
Started Jan 24 04:16:27 PM PST 24
Finished Jan 24 04:16:28 PM PST 24
Peak memory 200060 kb
Host smart-8c103c1b-791f-49e5-8fe5-59ae13c77f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940752518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1940752518
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.447437418
Short name T501
Test name
Test status
Simulation time 14339277 ps
CPU time 0.75 seconds
Started Jan 24 04:16:24 PM PST 24
Finished Jan 24 04:16:26 PM PST 24
Peak memory 201248 kb
Host smart-4370fcc8-311d-4d5e-8b14-ec33331f9e7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447437418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.447437418
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.1745698313
Short name T664
Test name
Test status
Simulation time 80920413 ps
CPU time 1.04 seconds
Started Jan 24 05:41:55 PM PST 24
Finished Jan 24 05:41:57 PM PST 24
Peak memory 201308 kb
Host smart-b98a5c2c-b7ef-4c7f-a6a9-e968b461f2dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745698313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1745698313
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1657142055
Short name T346
Test name
Test status
Simulation time 2348875872 ps
CPU time 10.1 seconds
Started Jan 24 04:16:23 PM PST 24
Finished Jan 24 04:16:34 PM PST 24
Peak memory 201652 kb
Host smart-ccb3f714-9d3e-4d25-a79f-9d3b9882765f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657142055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1657142055
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.4212049871
Short name T415
Test name
Test status
Simulation time 167105253 ps
CPU time 1.23 seconds
Started Jan 24 04:16:23 PM PST 24
Finished Jan 24 04:16:25 PM PST 24
Peak memory 201404 kb
Host smart-5781b2ab-6ba2-444a-a5a9-e112c88e79b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212049871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.4212049871
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3971173114
Short name T104
Test name
Test status
Simulation time 27691187 ps
CPU time 0.97 seconds
Started Jan 24 04:37:34 PM PST 24
Finished Jan 24 04:37:37 PM PST 24
Peak memory 201320 kb
Host smart-a3e11799-61a7-4582-b2c6-d59448a5c0cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971173114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3971173114
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1795965543
Short name T949
Test name
Test status
Simulation time 12925813 ps
CPU time 0.73 seconds
Started Jan 24 04:16:25 PM PST 24
Finished Jan 24 04:16:27 PM PST 24
Peak memory 201288 kb
Host smart-044ab83a-3dc8-4b54-aa18-a0162a632457
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795965543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.1795965543
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1241263145
Short name T354
Test name
Test status
Simulation time 59485956 ps
CPU time 0.9 seconds
Started Jan 24 04:51:20 PM PST 24
Finished Jan 24 04:51:27 PM PST 24
Peak memory 201304 kb
Host smart-96ef2efe-7c5a-42b0-bc8e-22a880ac4784
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241263145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.1241263145
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.2465115957
Short name T877
Test name
Test status
Simulation time 74598100 ps
CPU time 0.87 seconds
Started Jan 24 04:26:47 PM PST 24
Finished Jan 24 04:26:53 PM PST 24
Peak memory 201176 kb
Host smart-ebc8ebe2-357e-413a-9042-67f670d8a58a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465115957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2465115957
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.3659183831
Short name T284
Test name
Test status
Simulation time 917873667 ps
CPU time 5.15 seconds
Started Jan 24 04:16:33 PM PST 24
Finished Jan 24 04:16:39 PM PST 24
Peak memory 201368 kb
Host smart-754eed96-38e8-460b-acd5-9da12ac5fd36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659183831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3659183831
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1373761431
Short name T495
Test name
Test status
Simulation time 5456811103 ps
CPU time 21.08 seconds
Started Jan 24 04:16:42 PM PST 24
Finished Jan 24 04:17:04 PM PST 24
Peak memory 201760 kb
Host smart-b0b0228b-e52c-4808-8744-3b39dcd0f987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373761431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1373761431
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.3561227962
Short name T719
Test name
Test status
Simulation time 24937997688 ps
CPU time 431.07 seconds
Started Jan 24 04:16:35 PM PST 24
Finished Jan 24 04:23:47 PM PST 24
Peak memory 210048 kb
Host smart-7dccfd2a-0488-473b-8a2c-dc8df1d0845d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3561227962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3561227962
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.383506745
Short name T667
Test name
Test status
Simulation time 19501757 ps
CPU time 0.8 seconds
Started Jan 24 04:49:37 PM PST 24
Finished Jan 24 04:49:40 PM PST 24
Peak memory 201248 kb
Host smart-bb8d9b41-59c4-42e0-90ff-ecabfcc64c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383506745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.383506745
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.128384991
Short name T761
Test name
Test status
Simulation time 25259362 ps
CPU time 0.77 seconds
Started Jan 24 04:17:01 PM PST 24
Finished Jan 24 04:17:03 PM PST 24
Peak memory 201256 kb
Host smart-e9137588-4ca5-479f-867d-1c48662f3021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128384991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.128384991
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2741447626
Short name T100
Test name
Test status
Simulation time 26848144 ps
CPU time 0.93 seconds
Started Jan 24 04:16:49 PM PST 24
Finished Jan 24 04:16:51 PM PST 24
Peak memory 201300 kb
Host smart-66412039-c42f-4ccc-a2f8-7d6dbacc826c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741447626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.2741447626
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.641019629
Short name T134
Test name
Test status
Simulation time 47609830 ps
CPU time 0.78 seconds
Started Jan 24 04:40:12 PM PST 24
Finished Jan 24 04:40:13 PM PST 24
Peak memory 200112 kb
Host smart-12d79bfa-7f31-414f-92a6-ae30f2ca5a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641019629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.641019629
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1255508750
Short name T297
Test name
Test status
Simulation time 17922465 ps
CPU time 0.77 seconds
Started Jan 24 04:16:50 PM PST 24
Finished Jan 24 04:16:53 PM PST 24
Peak memory 201276 kb
Host smart-580ada43-0070-4d27-b1ee-1955e623453d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255508750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1255508750
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.899058639
Short name T407
Test name
Test status
Simulation time 29462965 ps
CPU time 0.84 seconds
Started Jan 24 04:16:48 PM PST 24
Finished Jan 24 04:16:50 PM PST 24
Peak memory 201320 kb
Host smart-45583e00-eb15-49f5-be1f-b2c2447b47b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899058639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.899058639
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.490630205
Short name T61
Test name
Test status
Simulation time 1934360361 ps
CPU time 14.51 seconds
Started Jan 24 04:16:43 PM PST 24
Finished Jan 24 04:17:01 PM PST 24
Peak memory 201416 kb
Host smart-482513ec-ead6-4123-84dd-43089f1f7e2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490630205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_ti
meout.490630205
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.2691111859
Short name T675
Test name
Test status
Simulation time 25589385 ps
CPU time 0.87 seconds
Started Jan 24 04:22:02 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 201312 kb
Host smart-29bbe47a-72f8-4da6-9839-8d860172ac5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691111859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.2691111859
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2060621286
Short name T161
Test name
Test status
Simulation time 25152590 ps
CPU time 0.91 seconds
Started Jan 24 04:16:48 PM PST 24
Finished Jan 24 04:16:50 PM PST 24
Peak memory 201288 kb
Host smart-c4fc5bd8-84f6-42b6-a5eb-c4a811b2b47d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060621286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2060621286
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.636348358
Short name T855
Test name
Test status
Simulation time 80664277 ps
CPU time 0.97 seconds
Started Jan 24 04:16:45 PM PST 24
Finished Jan 24 04:16:48 PM PST 24
Peak memory 201292 kb
Host smart-51ad80cf-4251-4bf1-81f6-68ac03d0ce00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636348358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_ctrl_intersig_mubi.636348358
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.1947927772
Short name T442
Test name
Test status
Simulation time 14934941 ps
CPU time 0.72 seconds
Started Jan 24 04:16:42 PM PST 24
Finished Jan 24 04:16:46 PM PST 24
Peak memory 201176 kb
Host smart-dcf06dbd-5619-40a5-8e77-922548e2b7e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947927772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.1947927772
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.3715074645
Short name T893
Test name
Test status
Simulation time 505517722 ps
CPU time 3.17 seconds
Started Jan 24 04:16:49 PM PST 24
Finished Jan 24 04:16:54 PM PST 24
Peak memory 201236 kb
Host smart-e1306963-2352-4e58-9267-fd0b4052562e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715074645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3715074645
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1904427348
Short name T582
Test name
Test status
Simulation time 15286990 ps
CPU time 0.81 seconds
Started Jan 24 05:30:00 PM PST 24
Finished Jan 24 05:30:01 PM PST 24
Peak memory 201324 kb
Host smart-1d19a30c-e31a-49ed-afd6-43992bf1fa83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904427348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1904427348
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.36338309
Short name T475
Test name
Test status
Simulation time 10558981479 ps
CPU time 42.25 seconds
Started Jan 24 04:16:56 PM PST 24
Finished Jan 24 04:17:39 PM PST 24
Peak memory 201700 kb
Host smart-de46aedd-2af6-4d33-a664-9b907d4923a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_stress_all.36338309
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.1510435656
Short name T44
Test name
Test status
Simulation time 193886459832 ps
CPU time 1298.52 seconds
Started Jan 24 04:16:52 PM PST 24
Finished Jan 24 04:38:31 PM PST 24
Peak memory 218156 kb
Host smart-fdf70032-337d-40c9-8321-45ee7535a2d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1510435656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1510435656
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.974442752
Short name T910
Test name
Test status
Simulation time 57182727 ps
CPU time 0.86 seconds
Started Jan 24 04:16:42 PM PST 24
Finished Jan 24 04:16:45 PM PST 24
Peak memory 201192 kb
Host smart-f27ffbd2-6638-4d33-bd3c-3f227c1b4f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974442752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.974442752
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1483861863
Short name T543
Test name
Test status
Simulation time 27539452 ps
CPU time 0.88 seconds
Started Jan 24 04:25:06 PM PST 24
Finished Jan 24 04:25:09 PM PST 24
Peak memory 201308 kb
Host smart-ad2247a1-f742-410d-9d49-2cb3d9bb16a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483861863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1483861863
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.454994756
Short name T768
Test name
Test status
Simulation time 29399737 ps
CPU time 1.02 seconds
Started Jan 24 05:49:01 PM PST 24
Finished Jan 24 05:49:02 PM PST 24
Peak memory 201296 kb
Host smart-94f5f9ac-d41f-480a-a6ea-900ef15d3cab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454994756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.454994756
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3135137630
Short name T138
Test name
Test status
Simulation time 15622309 ps
CPU time 0.72 seconds
Started Jan 24 05:26:11 PM PST 24
Finished Jan 24 05:26:12 PM PST 24
Peak memory 200108 kb
Host smart-1bbfdbbe-b46f-4e78-b61d-85a305eabcd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135137630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3135137630
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2451257238
Short name T596
Test name
Test status
Simulation time 30244914 ps
CPU time 0.91 seconds
Started Jan 24 04:17:05 PM PST 24
Finished Jan 24 04:17:07 PM PST 24
Peak memory 201276 kb
Host smart-a43d4ead-27d5-4c12-96ef-781c2c268ccc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451257238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2451257238
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1124073445
Short name T864
Test name
Test status
Simulation time 33551444 ps
CPU time 0.83 seconds
Started Jan 24 04:16:55 PM PST 24
Finished Jan 24 04:16:57 PM PST 24
Peak memory 201320 kb
Host smart-026f268b-e89c-46fc-a63c-77c0fc249bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124073445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1124073445
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.1761213479
Short name T110
Test name
Test status
Simulation time 257228321 ps
CPU time 1.5 seconds
Started Jan 24 04:16:56 PM PST 24
Finished Jan 24 04:16:58 PM PST 24
Peak memory 201324 kb
Host smart-77a0cba1-d479-4607-a057-cd16e949e508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761213479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1761213479
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.999825371
Short name T332
Test name
Test status
Simulation time 1581907519 ps
CPU time 7.64 seconds
Started Jan 24 04:16:59 PM PST 24
Finished Jan 24 04:17:08 PM PST 24
Peak memory 201376 kb
Host smart-9512da24-be8b-48f2-8278-3611f7e70613
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999825371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.999825371
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1690891677
Short name T530
Test name
Test status
Simulation time 51436585 ps
CPU time 1.06 seconds
Started Jan 24 04:17:04 PM PST 24
Finished Jan 24 04:17:05 PM PST 24
Peak memory 201268 kb
Host smart-f5db7798-eed7-40bc-bfc9-f7bd3f6ef448
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690891677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.1690891677
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.1653135785
Short name T494
Test name
Test status
Simulation time 41967384 ps
CPU time 0.91 seconds
Started Jan 24 04:17:08 PM PST 24
Finished Jan 24 04:17:10 PM PST 24
Peak memory 201280 kb
Host smart-2806bd4c-2629-4805-a6ea-4aaf99e9a627
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653135785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.1653135785
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1123585200
Short name T310
Test name
Test status
Simulation time 37919859 ps
CPU time 0.9 seconds
Started Jan 24 04:17:07 PM PST 24
Finished Jan 24 04:17:09 PM PST 24
Peak memory 201292 kb
Host smart-4c0ee222-0ade-41ca-bb49-a9d793090633
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123585200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.1123585200
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.1028573885
Short name T462
Test name
Test status
Simulation time 16441401 ps
CPU time 0.76 seconds
Started Jan 24 04:17:08 PM PST 24
Finished Jan 24 04:17:10 PM PST 24
Peak memory 201144 kb
Host smart-47e7e939-d557-4213-bdd9-f3324613144f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028573885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.1028573885
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2544182278
Short name T361
Test name
Test status
Simulation time 813603697 ps
CPU time 3.76 seconds
Started Jan 24 04:17:06 PM PST 24
Finished Jan 24 04:17:10 PM PST 24
Peak memory 201376 kb
Host smart-17e0f817-13bf-4ab3-8014-58af5bd2cb07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544182278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2544182278
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.2387941860
Short name T555
Test name
Test status
Simulation time 67763314 ps
CPU time 0.95 seconds
Started Jan 24 04:27:39 PM PST 24
Finished Jan 24 04:27:41 PM PST 24
Peak memory 201256 kb
Host smart-4552e91a-86c9-4aa4-bd0b-3a6bf188d7a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387941860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2387941860
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.2501058248
Short name T379
Test name
Test status
Simulation time 6503566024 ps
CPU time 26.65 seconds
Started Jan 24 04:27:53 PM PST 24
Finished Jan 24 04:28:23 PM PST 24
Peak memory 201736 kb
Host smart-82d52c68-38b3-46e9-a1ec-7e6d4c59a4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501058248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.2501058248
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1428613001
Short name T490
Test name
Test status
Simulation time 60321977561 ps
CPU time 746.73 seconds
Started Jan 24 04:17:07 PM PST 24
Finished Jan 24 04:29:35 PM PST 24
Peak memory 210004 kb
Host smart-fc4f6e79-b6ee-4cec-a3d7-63da61a51a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1428613001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1428613001
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.722618143
Short name T765
Test name
Test status
Simulation time 20427001 ps
CPU time 0.73 seconds
Started Jan 24 04:17:06 PM PST 24
Finished Jan 24 04:17:08 PM PST 24
Peak memory 201244 kb
Host smart-a211eb16-9237-41b9-ba3b-1f185efaf7ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722618143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.722618143
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1497538552
Short name T301
Test name
Test status
Simulation time 12746991 ps
CPU time 0.76 seconds
Started Jan 24 04:17:28 PM PST 24
Finished Jan 24 04:17:30 PM PST 24
Peak memory 201220 kb
Host smart-26f022e3-3bd0-47af-9eee-2577a1ae8462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497538552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1497538552
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3755428195
Short name T901
Test name
Test status
Simulation time 67125832 ps
CPU time 1 seconds
Started Jan 24 04:17:21 PM PST 24
Finished Jan 24 04:17:23 PM PST 24
Peak memory 201296 kb
Host smart-28b316dc-77b8-461e-b21b-ecf50ae0db61
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755428195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.3755428195
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3737026904
Short name T459
Test name
Test status
Simulation time 18884204 ps
CPU time 0.72 seconds
Started Jan 24 04:17:15 PM PST 24
Finished Jan 24 04:17:17 PM PST 24
Peak memory 200104 kb
Host smart-e44877b5-91e1-48a2-9b29-20105021c092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737026904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3737026904
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2852517854
Short name T318
Test name
Test status
Simulation time 50796071 ps
CPU time 0.91 seconds
Started Jan 24 04:17:18 PM PST 24
Finished Jan 24 04:17:19 PM PST 24
Peak memory 201308 kb
Host smart-126ed758-0099-40ba-a476-fa454c42b242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852517854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2852517854
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.1845788685
Short name T18
Test name
Test status
Simulation time 46217611 ps
CPU time 0.92 seconds
Started Jan 24 04:17:08 PM PST 24
Finished Jan 24 04:17:10 PM PST 24
Peak memory 201284 kb
Host smart-f29d16c4-5a39-45b7-bdad-000b1eebd13d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845788685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1845788685
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3685773558
Short name T794
Test name
Test status
Simulation time 1645446666 ps
CPU time 9.58 seconds
Started Jan 24 04:17:11 PM PST 24
Finished Jan 24 04:17:23 PM PST 24
Peak memory 201376 kb
Host smart-faa4b606-52f9-4dce-acaa-d81973e3c14a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685773558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3685773558
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2434485730
Short name T681
Test name
Test status
Simulation time 530225010 ps
CPU time 2.6 seconds
Started Jan 24 04:17:16 PM PST 24
Finished Jan 24 04:17:19 PM PST 24
Peak memory 201404 kb
Host smart-88a14b21-552d-4127-acb8-08f49f0c0531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434485730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2434485730
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.99386358
Short name T843
Test name
Test status
Simulation time 18633252 ps
CPU time 0.84 seconds
Started Jan 24 04:17:21 PM PST 24
Finished Jan 24 04:17:23 PM PST 24
Peak memory 201276 kb
Host smart-fe1dc49d-1ff4-458c-9b31-32cd251a6f05
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99386358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.clkmgr_idle_intersig_mubi.99386358
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3178703017
Short name T897
Test name
Test status
Simulation time 16397007 ps
CPU time 0.76 seconds
Started Jan 24 04:17:15 PM PST 24
Finished Jan 24 04:17:16 PM PST 24
Peak memory 201284 kb
Host smart-20b862bf-7b85-4858-915a-2ce085e8359f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178703017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3178703017
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2670135999
Short name T782
Test name
Test status
Simulation time 23909653 ps
CPU time 0.92 seconds
Started Jan 24 04:17:16 PM PST 24
Finished Jan 24 04:17:18 PM PST 24
Peak memory 201280 kb
Host smart-e0cb7a33-b1b4-4320-959d-bec3d235f3f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670135999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2670135999
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.3044360625
Short name T594
Test name
Test status
Simulation time 84821998 ps
CPU time 0.9 seconds
Started Jan 24 04:17:21 PM PST 24
Finished Jan 24 04:17:23 PM PST 24
Peak memory 201228 kb
Host smart-815cfffe-2f27-4648-b373-e5745b2b9beb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044360625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3044360625
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1421354350
Short name T288
Test name
Test status
Simulation time 117872139 ps
CPU time 1.07 seconds
Started Jan 24 04:17:28 PM PST 24
Finished Jan 24 04:17:30 PM PST 24
Peak memory 201260 kb
Host smart-9d83abbc-2e11-438c-9119-74deacc41de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421354350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1421354350
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.4012736749
Short name T571
Test name
Test status
Simulation time 26593180 ps
CPU time 0.91 seconds
Started Jan 24 04:17:10 PM PST 24
Finished Jan 24 04:17:13 PM PST 24
Peak memory 201320 kb
Host smart-5393a4c1-4347-4bd4-89c7-f75f6c8a9467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012736749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.4012736749
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.471585089
Short name T14
Test name
Test status
Simulation time 2256913358 ps
CPU time 9.73 seconds
Started Jan 24 04:17:27 PM PST 24
Finished Jan 24 04:17:38 PM PST 24
Peak memory 201640 kb
Host smart-d5119903-aa33-4951-9b44-515a62526d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471585089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.471585089
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.1038849960
Short name T708
Test name
Test status
Simulation time 295375789008 ps
CPU time 1382.82 seconds
Started Jan 24 04:17:28 PM PST 24
Finished Jan 24 04:40:32 PM PST 24
Peak memory 218200 kb
Host smart-03340a97-43e3-4db5-b689-174c1dbfcf08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1038849960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1038849960
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.3443483
Short name T566
Test name
Test status
Simulation time 92765051 ps
CPU time 1.1 seconds
Started Jan 24 06:45:50 PM PST 24
Finished Jan 24 06:45:56 PM PST 24
Peak memory 201200 kb
Host smart-57d146e6-f185-4da6-9ca1-57aaf4f8a84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3443483
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.4188136853
Short name T799
Test name
Test status
Simulation time 15566977 ps
CPU time 0.76 seconds
Started Jan 24 04:17:41 PM PST 24
Finished Jan 24 04:17:47 PM PST 24
Peak memory 201244 kb
Host smart-fd08ed14-6d82-4b73-a2b4-cafc7f20768b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188136853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.4188136853
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3563499689
Short name T649
Test name
Test status
Simulation time 54083357 ps
CPU time 0.99 seconds
Started Jan 24 04:21:31 PM PST 24
Finished Jan 24 04:21:48 PM PST 24
Peak memory 201292 kb
Host smart-bfea2741-e8fc-4b13-b58b-5fe97ba55852
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563499689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3563499689
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3782460147
Short name T749
Test name
Test status
Simulation time 39948524 ps
CPU time 0.76 seconds
Started Jan 24 04:17:39 PM PST 24
Finished Jan 24 04:17:47 PM PST 24
Peak memory 201200 kb
Host smart-87551798-1159-4f91-a672-61c84cd95291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782460147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3782460147
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1737275133
Short name T23
Test name
Test status
Simulation time 18823396 ps
CPU time 0.81 seconds
Started Jan 24 04:17:47 PM PST 24
Finished Jan 24 04:17:54 PM PST 24
Peak memory 201312 kb
Host smart-6e2d11e1-ecf3-471a-aade-a23736e51c0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737275133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1737275133
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.1589319340
Short name T333
Test name
Test status
Simulation time 92284066 ps
CPU time 1.09 seconds
Started Jan 24 04:17:28 PM PST 24
Finished Jan 24 04:17:30 PM PST 24
Peak memory 201252 kb
Host smart-32af7e2e-4a26-4d19-9233-7d34617ee6bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589319340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1589319340
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1689291672
Short name T542
Test name
Test status
Simulation time 2163232633 ps
CPU time 9.52 seconds
Started Jan 24 04:17:35 PM PST 24
Finished Jan 24 04:17:55 PM PST 24
Peak memory 201672 kb
Host smart-872d211e-08b7-47c7-b82b-7b76a09dce49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689291672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1689291672
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1217170028
Short name T657
Test name
Test status
Simulation time 861519742 ps
CPU time 6.55 seconds
Started Jan 24 04:17:37 PM PST 24
Finished Jan 24 04:17:52 PM PST 24
Peak memory 201416 kb
Host smart-d049db31-8a60-4e23-8a66-6904d12803cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217170028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1217170028
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2608037708
Short name T872
Test name
Test status
Simulation time 69464798 ps
CPU time 1.09 seconds
Started Jan 24 04:17:40 PM PST 24
Finished Jan 24 04:17:47 PM PST 24
Peak memory 201304 kb
Host smart-4a5add91-8484-456b-83ba-be1b6ef847fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608037708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.2608037708
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2713162767
Short name T702
Test name
Test status
Simulation time 19426567 ps
CPU time 0.74 seconds
Started Jan 24 04:17:41 PM PST 24
Finished Jan 24 04:17:47 PM PST 24
Peak memory 201276 kb
Host smart-8927b2f3-6900-40f8-befe-ef41eac33885
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713162767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2713162767
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.965246093
Short name T479
Test name
Test status
Simulation time 18820465 ps
CPU time 0.8 seconds
Started Jan 24 04:17:42 PM PST 24
Finished Jan 24 04:17:49 PM PST 24
Peak memory 201316 kb
Host smart-bbac4bcd-3b53-4b3d-8ccf-665ac59f3371
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965246093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.965246093
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.1051696779
Short name T569
Test name
Test status
Simulation time 42578378 ps
CPU time 0.81 seconds
Started Jan 24 04:17:34 PM PST 24
Finished Jan 24 04:17:45 PM PST 24
Peak memory 201172 kb
Host smart-75fabe68-276a-4d2b-9d5b-4584e561d66c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051696779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1051696779
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3299763865
Short name T476
Test name
Test status
Simulation time 1155258987 ps
CPU time 4.36 seconds
Started Jan 24 04:17:41 PM PST 24
Finished Jan 24 04:17:51 PM PST 24
Peak memory 201484 kb
Host smart-9e9edd3f-25ca-40be-89b8-ff75af8e24ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299763865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3299763865
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.2097163797
Short name T470
Test name
Test status
Simulation time 21878771 ps
CPU time 0.89 seconds
Started Jan 24 04:45:18 PM PST 24
Finished Jan 24 04:45:21 PM PST 24
Peak memory 201328 kb
Host smart-dc4fde84-716b-4c3c-8a94-437022d447e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097163797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2097163797
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.700678637
Short name T15
Test name
Test status
Simulation time 11873928601 ps
CPU time 43.33 seconds
Started Jan 24 04:17:46 PM PST 24
Finished Jan 24 04:18:37 PM PST 24
Peak memory 201732 kb
Host smart-d137224b-176e-4a9c-a76c-8a90da60dd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700678637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.700678637
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.1346899637
Short name T599
Test name
Test status
Simulation time 32188611843 ps
CPU time 473.06 seconds
Started Jan 24 04:17:47 PM PST 24
Finished Jan 24 04:25:47 PM PST 24
Peak memory 210112 kb
Host smart-558d4767-bad5-443e-b7ea-95513fa17b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1346899637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.1346899637
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.1762514150
Short name T601
Test name
Test status
Simulation time 13661298 ps
CPU time 0.7 seconds
Started Jan 24 04:17:35 PM PST 24
Finished Jan 24 04:17:47 PM PST 24
Peak memory 201248 kb
Host smart-0652558f-0f32-4953-bca0-83ccae3769f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762514150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1762514150
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.280696440
Short name T691
Test name
Test status
Simulation time 38243751 ps
CPU time 0.79 seconds
Started Jan 24 04:18:00 PM PST 24
Finished Jan 24 04:18:03 PM PST 24
Peak memory 201228 kb
Host smart-1a8c87ab-fa73-4fa8-8d81-77acb266672b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280696440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm
gr_alert_test.280696440
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.846975769
Short name T273
Test name
Test status
Simulation time 15408941 ps
CPU time 0.84 seconds
Started Jan 24 04:53:26 PM PST 24
Finished Jan 24 04:53:28 PM PST 24
Peak memory 201316 kb
Host smart-35aebb44-c498-4167-928c-85a657577a0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846975769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.846975769
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.3672714741
Short name T586
Test name
Test status
Simulation time 16464378 ps
CPU time 0.76 seconds
Started Jan 24 04:17:52 PM PST 24
Finished Jan 24 04:17:56 PM PST 24
Peak memory 201212 kb
Host smart-e0bca9c3-d0fd-445b-88fb-b48c351d94d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672714741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3672714741
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.426257061
Short name T380
Test name
Test status
Simulation time 44241165 ps
CPU time 0.84 seconds
Started Jan 24 04:17:59 PM PST 24
Finished Jan 24 04:18:03 PM PST 24
Peak memory 201256 kb
Host smart-93b2af31-e2a1-4178-925a-f42789b40f00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426257061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.426257061
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3284662989
Short name T711
Test name
Test status
Simulation time 47490977 ps
CPU time 0.85 seconds
Started Jan 24 04:17:53 PM PST 24
Finished Jan 24 04:17:57 PM PST 24
Peak memory 201296 kb
Host smart-d9eafd01-d95a-4a97-8422-8f37ec009024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284662989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3284662989
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.1961594689
Short name T405
Test name
Test status
Simulation time 1516439337 ps
CPU time 12.23 seconds
Started Jan 24 04:17:51 PM PST 24
Finished Jan 24 04:18:07 PM PST 24
Peak memory 201360 kb
Host smart-aa9bd0ce-ef4b-447a-8e2a-3112be145208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961594689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.1961594689
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.1608075284
Short name T325
Test name
Test status
Simulation time 385363238 ps
CPU time 2.49 seconds
Started Jan 24 04:17:52 PM PST 24
Finished Jan 24 04:17:58 PM PST 24
Peak memory 201432 kb
Host smart-aaf45e94-ee6e-4524-8562-f35482c76197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608075284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.1608075284
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1600375819
Short name T315
Test name
Test status
Simulation time 46322826 ps
CPU time 0.95 seconds
Started Jan 24 04:17:58 PM PST 24
Finished Jan 24 04:18:01 PM PST 24
Peak memory 201276 kb
Host smart-7019c08b-64c1-40b0-bb27-1dbe1b0333de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600375819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1600375819
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3445971372
Short name T450
Test name
Test status
Simulation time 70884845 ps
CPU time 0.97 seconds
Started Jan 24 04:18:01 PM PST 24
Finished Jan 24 04:18:04 PM PST 24
Peak memory 201240 kb
Host smart-d0ab6c5a-2a69-4457-8317-f44dab5ae856
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445971372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.3445971372
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.341478691
Short name T408
Test name
Test status
Simulation time 36002279 ps
CPU time 0.76 seconds
Started Jan 24 04:17:47 PM PST 24
Finished Jan 24 04:17:55 PM PST 24
Peak memory 201236 kb
Host smart-1efcc5d8-5c12-4748-9866-d32180a937f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341478691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.341478691
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.3045940653
Short name T429
Test name
Test status
Simulation time 823258525 ps
CPU time 4.88 seconds
Started Jan 24 04:25:47 PM PST 24
Finished Jan 24 04:26:00 PM PST 24
Peak memory 201424 kb
Host smart-9b7abd11-f8da-4571-97df-a5669dd7e168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045940653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3045940653
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.3355046126
Short name T885
Test name
Test status
Simulation time 32055492 ps
CPU time 0.88 seconds
Started Jan 24 04:59:28 PM PST 24
Finished Jan 24 04:59:30 PM PST 24
Peak memory 201320 kb
Host smart-e52804f0-6662-40c6-8403-f1a86917faad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355046126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3355046126
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.4267264225
Short name T732
Test name
Test status
Simulation time 9115662635 ps
CPU time 42.7 seconds
Started Jan 24 04:50:35 PM PST 24
Finished Jan 24 04:51:20 PM PST 24
Peak memory 201716 kb
Host smart-b672accb-3aec-4304-90d3-e44f05a1a484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267264225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.4267264225
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.756252200
Short name T559
Test name
Test status
Simulation time 98795871263 ps
CPU time 448.16 seconds
Started Jan 24 04:17:58 PM PST 24
Finished Jan 24 04:25:28 PM PST 24
Peak memory 218236 kb
Host smart-6a703347-5b31-44f4-9e92-acae58429ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=756252200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.756252200
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.4051292373
Short name T827
Test name
Test status
Simulation time 42582617 ps
CPU time 0.93 seconds
Started Jan 24 04:17:51 PM PST 24
Finished Jan 24 04:17:56 PM PST 24
Peak memory 201260 kb
Host smart-243547b0-476f-4efb-9c54-e0757c9e0f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051292373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.4051292373
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.932108825
Short name T40
Test name
Test status
Simulation time 53417574 ps
CPU time 0.93 seconds
Started Jan 24 04:18:14 PM PST 24
Finished Jan 24 04:18:20 PM PST 24
Peak memory 201284 kb
Host smart-1a761a4e-9c45-4482-867d-0922f3fc01ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932108825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkm
gr_alert_test.932108825
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4196829096
Short name T309
Test name
Test status
Simulation time 19469915 ps
CPU time 0.81 seconds
Started Jan 24 04:18:10 PM PST 24
Finished Jan 24 04:18:18 PM PST 24
Peak memory 201292 kb
Host smart-ca8df091-2a40-4da2-bb7e-89403fa2ddaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196829096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.4196829096
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.1735307188
Short name T600
Test name
Test status
Simulation time 18921863 ps
CPU time 0.72 seconds
Started Jan 24 04:18:00 PM PST 24
Finished Jan 24 04:18:03 PM PST 24
Peak memory 200104 kb
Host smart-54ec2012-a490-4d37-91b5-29a39779de57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735307188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1735307188
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.646483494
Short name T376
Test name
Test status
Simulation time 80212706 ps
CPU time 1.02 seconds
Started Jan 24 04:18:06 PM PST 24
Finished Jan 24 04:18:13 PM PST 24
Peak memory 201292 kb
Host smart-97a8b83c-5ebe-4328-a969-ca34adb4d8d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646483494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_div_intersig_mubi.646483494
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3348611155
Short name T417
Test name
Test status
Simulation time 66871117 ps
CPU time 0.94 seconds
Started Jan 24 04:18:04 PM PST 24
Finished Jan 24 04:18:12 PM PST 24
Peak memory 201320 kb
Host smart-4b91687a-2521-43d9-8258-753254bcccc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348611155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3348611155
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3806126909
Short name T850
Test name
Test status
Simulation time 2015133685 ps
CPU time 10.29 seconds
Started Jan 24 04:17:59 PM PST 24
Finished Jan 24 04:18:12 PM PST 24
Peak memory 201540 kb
Host smart-28ac1dc0-67f4-4bea-a4d5-8200c0c84b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806126909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3806126909
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.2035249776
Short name T733
Test name
Test status
Simulation time 380759943 ps
CPU time 2.33 seconds
Started Jan 24 04:17:56 PM PST 24
Finished Jan 24 04:18:00 PM PST 24
Peak memory 201428 kb
Host smart-5632ac87-8c99-4899-bad3-601c0dbe70ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035249776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.2035249776
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.4068340097
Short name T428
Test name
Test status
Simulation time 30586413 ps
CPU time 0.97 seconds
Started Jan 24 04:18:00 PM PST 24
Finished Jan 24 04:18:03 PM PST 24
Peak memory 201288 kb
Host smart-f332f758-e48a-4bb7-a600-75b5d35e983c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068340097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.4068340097
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3911871997
Short name T755
Test name
Test status
Simulation time 66161966 ps
CPU time 0.96 seconds
Started Jan 24 04:18:10 PM PST 24
Finished Jan 24 04:18:18 PM PST 24
Peak memory 201296 kb
Host smart-f7db94bc-f895-45b8-84d1-ad40c7fa7e97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911871997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3911871997
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1244310395
Short name T803
Test name
Test status
Simulation time 57925918 ps
CPU time 0.98 seconds
Started Jan 24 06:28:08 PM PST 24
Finished Jan 24 06:28:09 PM PST 24
Peak memory 201308 kb
Host smart-bcd5d20c-59d8-4285-ba09-9ff195b4edec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244310395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1244310395
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.2375022357
Short name T614
Test name
Test status
Simulation time 13402135 ps
CPU time 0.71 seconds
Started Jan 24 05:29:32 PM PST 24
Finished Jan 24 05:29:33 PM PST 24
Peak memory 201160 kb
Host smart-1f9d654a-d2f2-4b28-83c8-f70d52cfd1b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375022357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2375022357
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.716680236
Short name T367
Test name
Test status
Simulation time 1099106927 ps
CPU time 6.29 seconds
Started Jan 24 04:18:08 PM PST 24
Finished Jan 24 04:18:19 PM PST 24
Peak memory 201468 kb
Host smart-7d33b4a0-1dbd-4cdb-8826-82808678ae9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716680236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.716680236
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.548500332
Short name T467
Test name
Test status
Simulation time 49556685 ps
CPU time 0.9 seconds
Started Jan 24 06:22:35 PM PST 24
Finished Jan 24 06:22:37 PM PST 24
Peak memory 201316 kb
Host smart-f9842185-36a6-4fb0-81ee-d14cb416c032
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548500332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.548500332
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.279914818
Short name T966
Test name
Test status
Simulation time 7052774580 ps
CPU time 29.77 seconds
Started Jan 24 04:18:10 PM PST 24
Finished Jan 24 04:18:46 PM PST 24
Peak memory 201688 kb
Host smart-05ff59b9-0039-40ad-87e9-7f6a082df2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279914818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.279914818
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.805817164
Short name T465
Test name
Test status
Simulation time 27907529296 ps
CPU time 247.05 seconds
Started Jan 24 04:18:07 PM PST 24
Finished Jan 24 04:22:19 PM PST 24
Peak memory 210024 kb
Host smart-07413d69-9bd8-4547-9acf-187f0dd3421d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=805817164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.805817164
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.2101677438
Short name T713
Test name
Test status
Simulation time 115370405 ps
CPU time 1.13 seconds
Started Jan 24 04:18:02 PM PST 24
Finished Jan 24 04:18:10 PM PST 24
Peak memory 201324 kb
Host smart-f008426d-522b-4465-8147-286637560afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101677438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2101677438
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.32978883
Short name T42
Test name
Test status
Simulation time 52072037 ps
CPU time 0.86 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:04 PM PST 24
Peak memory 201260 kb
Host smart-b8c3fcb8-66a3-4357-9f74-f81139ca410b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmg
r_alert_test.32978883
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3364217231
Short name T313
Test name
Test status
Simulation time 31876067 ps
CPU time 0.82 seconds
Started Jan 24 04:18:31 PM PST 24
Finished Jan 24 04:18:34 PM PST 24
Peak memory 201304 kb
Host smart-5a8c3145-a242-4a7f-bbc4-0521d368b97c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364217231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3364217231
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.3221856364
Short name T953
Test name
Test status
Simulation time 43120617 ps
CPU time 0.76 seconds
Started Jan 24 04:32:47 PM PST 24
Finished Jan 24 04:32:49 PM PST 24
Peak memory 201196 kb
Host smart-c8528c22-063e-4df7-9a5e-9daecddb8380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221856364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3221856364
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.2400044592
Short name T461
Test name
Test status
Simulation time 155809109 ps
CPU time 1.25 seconds
Started Jan 24 04:18:34 PM PST 24
Finished Jan 24 04:18:38 PM PST 24
Peak memory 201244 kb
Host smart-750e1b8d-3c87-434e-a347-014dc12107b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400044592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.2400044592
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.2247372233
Short name T453
Test name
Test status
Simulation time 72638913 ps
CPU time 0.96 seconds
Started Jan 24 04:18:16 PM PST 24
Finished Jan 24 04:18:21 PM PST 24
Peak memory 201304 kb
Host smart-77bb6d0a-550c-414a-89a8-c3fc4732fa64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247372233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2247372233
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3768357195
Short name T695
Test name
Test status
Simulation time 1550380166 ps
CPU time 6.08 seconds
Started Jan 24 04:18:17 PM PST 24
Finished Jan 24 04:18:27 PM PST 24
Peak memory 201360 kb
Host smart-3f515839-38dd-4701-9bf2-72b8c7294cd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768357195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3768357195
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1269910287
Short name T818
Test name
Test status
Simulation time 61103583 ps
CPU time 1.13 seconds
Started Jan 24 04:18:18 PM PST 24
Finished Jan 24 04:18:23 PM PST 24
Peak memory 201288 kb
Host smart-47896178-d1f2-409c-9685-cc289674c4ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269910287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.1269910287
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.134122295
Short name T731
Test name
Test status
Simulation time 25378366 ps
CPU time 0.92 seconds
Started Jan 24 04:18:24 PM PST 24
Finished Jan 24 04:18:26 PM PST 24
Peak memory 201244 kb
Host smart-55ad56dc-0b6e-4203-8989-34541625748b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134122295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_clk_byp_req_intersig_mubi.134122295
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3279529873
Short name T433
Test name
Test status
Simulation time 15734236 ps
CPU time 0.75 seconds
Started Jan 24 04:30:26 PM PST 24
Finished Jan 24 04:30:29 PM PST 24
Peak memory 201300 kb
Host smart-5d6600b3-954f-4135-bbcd-3321b061a7e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279529873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.3279529873
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.1559723922
Short name T283
Test name
Test status
Simulation time 77336944 ps
CPU time 0.93 seconds
Started Jan 24 04:32:04 PM PST 24
Finished Jan 24 04:32:06 PM PST 24
Peak memory 201128 kb
Host smart-c72c3cec-1685-4ca0-a214-88c809d4501b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559723922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1559723922
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.3769667993
Short name T500
Test name
Test status
Simulation time 396692822 ps
CPU time 1.92 seconds
Started Jan 24 04:18:34 PM PST 24
Finished Jan 24 04:18:39 PM PST 24
Peak memory 201284 kb
Host smart-9299c91f-a8e0-4e41-8095-1c936e632b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769667993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.3769667993
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3499630495
Short name T546
Test name
Test status
Simulation time 25593321 ps
CPU time 0.9 seconds
Started Jan 24 08:24:52 PM PST 24
Finished Jan 24 08:24:58 PM PST 24
Peak memory 201204 kb
Host smart-fe32fdae-4525-4d97-8329-a5cbde6484a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499630495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3499630495
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.1432144392
Short name T942
Test name
Test status
Simulation time 4777968682 ps
CPU time 34.82 seconds
Started Jan 24 04:18:33 PM PST 24
Finished Jan 24 04:19:11 PM PST 24
Peak memory 201676 kb
Host smart-5e83566a-2425-4318-a14c-b29f339512f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432144392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.1432144392
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1811333590
Short name T756
Test name
Test status
Simulation time 68357423575 ps
CPU time 603.72 seconds
Started Jan 24 04:18:34 PM PST 24
Finished Jan 24 04:28:40 PM PST 24
Peak memory 210036 kb
Host smart-dbcfe561-7908-4b07-b53b-89063acd0fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1811333590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1811333590
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.336113665
Short name T943
Test name
Test status
Simulation time 22910355 ps
CPU time 0.8 seconds
Started Jan 24 04:18:15 PM PST 24
Finished Jan 24 04:18:20 PM PST 24
Peak memory 201128 kb
Host smart-181537ac-5cdc-4a11-99ff-25a3298844de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336113665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.336113665
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.161986401
Short name T774
Test name
Test status
Simulation time 68309183 ps
CPU time 0.9 seconds
Started Jan 24 05:00:47 PM PST 24
Finished Jan 24 05:00:50 PM PST 24
Peak memory 201320 kb
Host smart-cbcb74c4-9e4e-452f-9d80-fe6143362d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161986401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.161986401
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.909662369
Short name T585
Test name
Test status
Simulation time 235615621 ps
CPU time 1.37 seconds
Started Jan 24 04:18:45 PM PST 24
Finished Jan 24 04:18:48 PM PST 24
Peak memory 201348 kb
Host smart-8b1df3e3-e219-4b01-b587-473959361f9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909662369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.909662369
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3176369974
Short name T498
Test name
Test status
Simulation time 14559577 ps
CPU time 0.7 seconds
Started Jan 24 04:18:48 PM PST 24
Finished Jan 24 04:18:50 PM PST 24
Peak memory 201188 kb
Host smart-08f31976-1487-4177-b2f9-f861a2f1f40c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176369974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3176369974
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.1768739487
Short name T693
Test name
Test status
Simulation time 82785015 ps
CPU time 0.98 seconds
Started Jan 24 04:18:42 PM PST 24
Finished Jan 24 04:18:46 PM PST 24
Peak memory 201256 kb
Host smart-693cc5c4-343a-4b1a-b672-a335e229b965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768739487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1768739487
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.330729097
Short name T377
Test name
Test status
Simulation time 319483834 ps
CPU time 2.89 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:07 PM PST 24
Peak memory 201368 kb
Host smart-a0d5863b-b61e-4e6b-9c29-7e894698ab94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330729097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.330729097
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.4171832934
Short name T738
Test name
Test status
Simulation time 1784545447 ps
CPU time 7.07 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:10 PM PST 24
Peak memory 201416 kb
Host smart-32648fa6-aaad-4b53-9911-760b8210d64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171832934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.4171832934
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.494883120
Short name T736
Test name
Test status
Simulation time 15065674 ps
CPU time 0.78 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:05 PM PST 24
Peak memory 201180 kb
Host smart-35491714-ab5a-490b-ab61-930dd0da06a1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494883120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_idle_intersig_mubi.494883120
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1236703804
Short name T473
Test name
Test status
Simulation time 32580196 ps
CPU time 0.87 seconds
Started Jan 24 05:13:08 PM PST 24
Finished Jan 24 05:13:09 PM PST 24
Peak memory 201292 kb
Host smart-c76dcad2-4f6f-456f-b638-04d5a1ad24ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236703804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1236703804
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.296522032
Short name T387
Test name
Test status
Simulation time 17430294 ps
CPU time 0.78 seconds
Started Jan 24 04:18:44 PM PST 24
Finished Jan 24 04:18:47 PM PST 24
Peak memory 201304 kb
Host smart-8d8a61bc-35ea-4589-be89-261938b0af64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296522032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.clkmgr_lc_ctrl_intersig_mubi.296522032
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.2170184682
Short name T674
Test name
Test status
Simulation time 18521355 ps
CPU time 0.8 seconds
Started Jan 24 04:18:48 PM PST 24
Finished Jan 24 04:18:50 PM PST 24
Peak memory 201120 kb
Host smart-4229c347-8408-47f6-88d8-5bb3e73d708a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170184682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2170184682
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.505625343
Short name T526
Test name
Test status
Simulation time 1072807705 ps
CPU time 6.22 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:10 PM PST 24
Peak memory 201124 kb
Host smart-c4e6d6bb-a2c5-4301-954b-99696762c92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505625343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.505625343
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.2626122204
Short name T670
Test name
Test status
Simulation time 23705302 ps
CPU time 0.87 seconds
Started Jan 24 04:18:47 PM PST 24
Finished Jan 24 04:18:50 PM PST 24
Peak memory 201316 kb
Host smart-cad1abd2-12c5-4539-8071-af17b509b489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626122204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2626122204
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1893833030
Short name T671
Test name
Test status
Simulation time 10403983531 ps
CPU time 53.89 seconds
Started Jan 24 04:18:46 PM PST 24
Finished Jan 24 04:19:41 PM PST 24
Peak memory 201704 kb
Host smart-6852904b-23a6-40c1-81c2-7a829efafc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893833030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1893833030
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.1936844698
Short name T371
Test name
Test status
Simulation time 98174147476 ps
CPU time 681.84 seconds
Started Jan 24 04:58:20 PM PST 24
Finished Jan 24 05:09:43 PM PST 24
Peak memory 213324 kb
Host smart-d81c8dce-e2b1-40d3-96f1-821022b7230f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1936844698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.1936844698
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3817903582
Short name T951
Test name
Test status
Simulation time 23536314 ps
CPU time 0.88 seconds
Started Jan 24 05:16:11 PM PST 24
Finished Jan 24 05:16:13 PM PST 24
Peak memory 201248 kb
Host smart-807f4d1a-e7cf-4874-b167-88501d4c3e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817903582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3817903582
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.351573422
Short name T289
Test name
Test status
Simulation time 16731950 ps
CPU time 0.75 seconds
Started Jan 24 04:19:07 PM PST 24
Finished Jan 24 04:19:09 PM PST 24
Peak memory 201260 kb
Host smart-b4048756-ca4e-4b9c-9781-eaeaa52ee2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351573422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkm
gr_alert_test.351573422
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2320117102
Short name T276
Test name
Test status
Simulation time 90535690 ps
CPU time 0.94 seconds
Started Jan 24 04:18:55 PM PST 24
Finished Jan 24 04:19:03 PM PST 24
Peak memory 201328 kb
Host smart-878fdb93-5394-41b4-8741-d17c01e9aa3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320117102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.2320117102
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.592390974
Short name T735
Test name
Test status
Simulation time 99228924 ps
CPU time 0.89 seconds
Started Jan 24 04:18:54 PM PST 24
Finished Jan 24 04:19:03 PM PST 24
Peak memory 201180 kb
Host smart-8cdb845d-9702-4e45-92e1-221be1260913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592390974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.592390974
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.183623085
Short name T523
Test name
Test status
Simulation time 65437795 ps
CPU time 1.04 seconds
Started Jan 24 04:19:02 PM PST 24
Finished Jan 24 04:19:08 PM PST 24
Peak memory 201304 kb
Host smart-494b1b77-f636-4c9a-8b00-8233181dfbfa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183623085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_div_intersig_mubi.183623085
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2221956240
Short name T506
Test name
Test status
Simulation time 2289104354 ps
CPU time 10.8 seconds
Started Jan 24 04:18:53 PM PST 24
Finished Jan 24 04:19:08 PM PST 24
Peak memory 201660 kb
Host smart-c5482bad-9240-4f59-a66d-accef3f8e921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221956240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2221956240
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.1441288437
Short name T699
Test name
Test status
Simulation time 766773623 ps
CPU time 2.87 seconds
Started Jan 24 04:18:55 PM PST 24
Finished Jan 24 04:19:05 PM PST 24
Peak memory 201404 kb
Host smart-156bca99-cd69-46d4-a44a-3890a8e3fb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441288437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.1441288437
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1436962526
Short name T838
Test name
Test status
Simulation time 41146050 ps
CPU time 0.93 seconds
Started Jan 24 04:18:54 PM PST 24
Finished Jan 24 04:19:03 PM PST 24
Peak memory 201244 kb
Host smart-82503932-3585-4409-bebf-fa95923ffcb7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436962526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.1436962526
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.517453844
Short name T697
Test name
Test status
Simulation time 31635216 ps
CPU time 0.82 seconds
Started Jan 24 04:18:53 PM PST 24
Finished Jan 24 04:19:02 PM PST 24
Peak memory 201236 kb
Host smart-23280f7c-a20e-4b4d-8755-7d0c49762158
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517453844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_clk_byp_req_intersig_mubi.517453844
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1311937566
Short name T557
Test name
Test status
Simulation time 154596207 ps
CPU time 1.23 seconds
Started Jan 24 04:18:54 PM PST 24
Finished Jan 24 04:19:04 PM PST 24
Peak memory 201284 kb
Host smart-f1e3df90-2329-4635-a935-3b81d6a86ae7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311937566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.1311937566
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2727235878
Short name T788
Test name
Test status
Simulation time 40746404 ps
CPU time 0.76 seconds
Started Jan 24 04:18:53 PM PST 24
Finished Jan 24 04:19:00 PM PST 24
Peak memory 201252 kb
Host smart-eb2b2d0b-0f69-4d98-b9f2-06986af52ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727235878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2727235878
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.72289348
Short name T870
Test name
Test status
Simulation time 163905463 ps
CPU time 1.45 seconds
Started Jan 24 04:18:55 PM PST 24
Finished Jan 24 04:19:04 PM PST 24
Peak memory 201220 kb
Host smart-b975acff-d18f-439f-be7c-8b1070ad45aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72289348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.72289348
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.3771869330
Short name T597
Test name
Test status
Simulation time 29723940 ps
CPU time 0.84 seconds
Started Jan 24 04:18:59 PM PST 24
Finished Jan 24 04:19:05 PM PST 24
Peak memory 201020 kb
Host smart-00f326f5-8230-45ad-a14d-56d6d6583a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771869330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3771869330
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.2719566557
Short name T314
Test name
Test status
Simulation time 7093483740 ps
CPU time 28.87 seconds
Started Jan 24 04:18:55 PM PST 24
Finished Jan 24 04:19:31 PM PST 24
Peak memory 201728 kb
Host smart-426df6aa-eeef-412b-86f2-968991ad2369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719566557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.2719566557
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.4145682820
Short name T12
Test name
Test status
Simulation time 9458129907 ps
CPU time 134.51 seconds
Started Jan 24 04:18:53 PM PST 24
Finished Jan 24 04:21:16 PM PST 24
Peak memory 210060 kb
Host smart-b9e232bb-6d0b-430c-ba03-b1394790fd60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4145682820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.4145682820
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.3876148249
Short name T931
Test name
Test status
Simulation time 22723123 ps
CPU time 0.83 seconds
Started Jan 24 04:18:53 PM PST 24
Finished Jan 24 04:19:00 PM PST 24
Peak memory 201244 kb
Host smart-002c4adb-93dc-4e8b-ba5e-8d51cca1f129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876148249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3876148249
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.273419512
Short name T41
Test name
Test status
Simulation time 15423127 ps
CPU time 0.74 seconds
Started Jan 24 04:12:11 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201236 kb
Host smart-27a7b466-f371-4fb2-820d-f762dfe64030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273419512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_alert_test.273419512
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1945770196
Short name T144
Test name
Test status
Simulation time 46569390 ps
CPU time 0.93 seconds
Started Jan 24 04:11:54 PM PST 24
Finished Jan 24 04:11:56 PM PST 24
Peak memory 201308 kb
Host smart-8cf1e782-16e9-427b-8080-e8f3e344fbbf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945770196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1945770196
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2369728890
Short name T460
Test name
Test status
Simulation time 13663827 ps
CPU time 0.72 seconds
Started Jan 24 05:26:11 PM PST 24
Finished Jan 24 05:26:13 PM PST 24
Peak memory 201212 kb
Host smart-a2026981-894e-43db-bdde-e31025e60ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369728890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2369728890
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3223595439
Short name T532
Test name
Test status
Simulation time 18240187 ps
CPU time 0.76 seconds
Started Jan 24 04:11:52 PM PST 24
Finished Jan 24 04:11:55 PM PST 24
Peak memory 201308 kb
Host smart-584f6a2c-9756-4e69-8d97-3ba9deb4ca89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223595439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3223595439
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.1021278810
Short name T362
Test name
Test status
Simulation time 28314642 ps
CPU time 0.84 seconds
Started Jan 24 04:11:31 PM PST 24
Finished Jan 24 04:11:34 PM PST 24
Peak memory 201320 kb
Host smart-e5be7c2c-7850-4f61-a066-e962fc77c6ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021278810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1021278810
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.2505410991
Short name T912
Test name
Test status
Simulation time 1406954669 ps
CPU time 8.19 seconds
Started Jan 24 04:20:45 PM PST 24
Finished Jan 24 04:20:54 PM PST 24
Peak memory 201368 kb
Host smart-8bde6b86-4db5-41b4-a56d-dc36fe95cf67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505410991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2505410991
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2780350807
Short name T335
Test name
Test status
Simulation time 928856598 ps
CPU time 4.08 seconds
Started Jan 24 04:11:47 PM PST 24
Finished Jan 24 04:11:53 PM PST 24
Peak memory 201428 kb
Host smart-03e26674-38f2-451f-9977-2e89e74dfd0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780350807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2780350807
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.845094439
Short name T961
Test name
Test status
Simulation time 17756848 ps
CPU time 0.84 seconds
Started Jan 24 04:35:03 PM PST 24
Finished Jan 24 04:35:09 PM PST 24
Peak memory 201236 kb
Host smart-7f13c9f1-8d91-42c6-8049-ef1c5ec15b38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845094439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_idle_intersig_mubi.845094439
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2398392578
Short name T727
Test name
Test status
Simulation time 73764001 ps
CPU time 1.02 seconds
Started Jan 24 04:11:50 PM PST 24
Finished Jan 24 04:11:53 PM PST 24
Peak memory 201276 kb
Host smart-2ec93d50-8cb7-4615-ab3b-3c86229beeb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398392578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2398392578
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.647757434
Short name T536
Test name
Test status
Simulation time 14477983 ps
CPU time 0.72 seconds
Started Jan 24 04:11:49 PM PST 24
Finished Jan 24 04:11:51 PM PST 24
Peak memory 201340 kb
Host smart-6ca4c4e6-4a50-4a2c-a5ef-8e88cf4ac5c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647757434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_ctrl_intersig_mubi.647757434
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3687790581
Short name T797
Test name
Test status
Simulation time 12746372 ps
CPU time 0.71 seconds
Started Jan 24 04:11:42 PM PST 24
Finished Jan 24 04:11:46 PM PST 24
Peak memory 201116 kb
Host smart-a95e17a4-f765-4dfe-90c6-6864d3cafda1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687790581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3687790581
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.1002379626
Short name T19
Test name
Test status
Simulation time 1228120014 ps
CPU time 4.77 seconds
Started Jan 24 04:11:54 PM PST 24
Finished Jan 24 04:12:00 PM PST 24
Peak memory 201452 kb
Host smart-74af71ac-2bff-40bf-83e0-499994400c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002379626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1002379626
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.202725124
Short name T427
Test name
Test status
Simulation time 31877985 ps
CPU time 0.87 seconds
Started Jan 24 04:26:46 PM PST 24
Finished Jan 24 04:26:53 PM PST 24
Peak memory 201292 kb
Host smart-afdee948-5685-4d58-86c0-c6cda05dc864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202725124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.202725124
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.2916434386
Short name T381
Test name
Test status
Simulation time 291651520 ps
CPU time 1.97 seconds
Started Jan 24 04:12:08 PM PST 24
Finished Jan 24 04:12:18 PM PST 24
Peak memory 201232 kb
Host smart-97400685-ae0b-4360-9179-8387c3a012cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916434386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.2916434386
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.2872953307
Short name T746
Test name
Test status
Simulation time 101406301494 ps
CPU time 967.32 seconds
Started Jan 24 04:12:00 PM PST 24
Finished Jan 24 04:28:09 PM PST 24
Peak memory 209984 kb
Host smart-898f5b5a-be7d-4ad7-91be-8567616d8340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2872953307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2872953307
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.2890217192
Short name T882
Test name
Test status
Simulation time 15949084 ps
CPU time 0.74 seconds
Started Jan 24 04:11:41 PM PST 24
Finished Jan 24 04:11:45 PM PST 24
Peak memory 201132 kb
Host smart-190427db-f9b5-480c-a0b5-837aab66a26d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890217192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2890217192
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.3770880266
Short name T488
Test name
Test status
Simulation time 69522843 ps
CPU time 0.96 seconds
Started Jan 24 04:19:15 PM PST 24
Finished Jan 24 04:19:17 PM PST 24
Peak memory 201248 kb
Host smart-c1ce36ea-2a35-40fc-83af-c1bfe7facb15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770880266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.3770880266
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.3210348918
Short name T925
Test name
Test status
Simulation time 47975142 ps
CPU time 0.78 seconds
Started Jan 24 04:19:07 PM PST 24
Finished Jan 24 04:19:10 PM PST 24
Peak memory 200128 kb
Host smart-d93b02e9-61a0-49d7-83cc-8db7978c6d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210348918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3210348918
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3835965232
Short name T769
Test name
Test status
Simulation time 37730698 ps
CPU time 0.88 seconds
Started Jan 24 04:19:14 PM PST 24
Finished Jan 24 04:19:16 PM PST 24
Peak memory 201280 kb
Host smart-0de4daae-4f16-49d4-a9e1-5b7a29407e13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835965232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.3835965232
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.3760992249
Short name T837
Test name
Test status
Simulation time 36037374 ps
CPU time 0.84 seconds
Started Jan 24 04:19:05 PM PST 24
Finished Jan 24 04:19:09 PM PST 24
Peak memory 201328 kb
Host smart-05a331e0-2ff0-4b75-ab9a-e68ac1cae967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760992249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3760992249
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.3479391515
Short name T62
Test name
Test status
Simulation time 807411035 ps
CPU time 3.82 seconds
Started Jan 24 04:19:09 PM PST 24
Finished Jan 24 04:19:15 PM PST 24
Peak memory 201376 kb
Host smart-4006e7ff-dde4-47d1-b759-ea0f021cf4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479391515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3479391515
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.922866649
Short name T328
Test name
Test status
Simulation time 982071535 ps
CPU time 5.12 seconds
Started Jan 24 04:19:06 PM PST 24
Finished Jan 24 04:19:14 PM PST 24
Peak memory 201408 kb
Host smart-3a3f1379-a916-41ea-9316-7eaf32c22adc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922866649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti
meout.922866649
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2449853487
Short name T696
Test name
Test status
Simulation time 24795428 ps
CPU time 0.92 seconds
Started Jan 24 04:19:07 PM PST 24
Finished Jan 24 04:19:10 PM PST 24
Peak memory 201284 kb
Host smart-dadebbf7-54b2-4b57-9a8b-dc3c8bf6f204
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449853487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2449853487
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2254360641
Short name T680
Test name
Test status
Simulation time 39890907 ps
CPU time 0.93 seconds
Started Jan 24 05:13:10 PM PST 24
Finished Jan 24 05:13:12 PM PST 24
Peak memory 201300 kb
Host smart-9093e3c3-e1f1-42e3-9a95-fc875157ed8e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254360641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.2254360641
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3342733996
Short name T477
Test name
Test status
Simulation time 73342195 ps
CPU time 0.97 seconds
Started Jan 24 04:29:10 PM PST 24
Finished Jan 24 04:29:12 PM PST 24
Peak memory 201316 kb
Host smart-fe5e4a7f-2f6c-4bc7-9fa5-51c157c5b27f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342733996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3342733996
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.4066903874
Short name T875
Test name
Test status
Simulation time 18376112 ps
CPU time 0.76 seconds
Started Jan 24 04:19:06 PM PST 24
Finished Jan 24 04:19:09 PM PST 24
Peak memory 201168 kb
Host smart-a65679b4-025c-4120-8827-3b7202d11de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066903874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.4066903874
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.1590169714
Short name T32
Test name
Test status
Simulation time 786041697 ps
CPU time 4.42 seconds
Started Jan 24 04:19:22 PM PST 24
Finished Jan 24 04:19:28 PM PST 24
Peak memory 201428 kb
Host smart-0b7ddfef-f4c0-410b-a375-1160622f7dd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590169714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.1590169714
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.253152435
Short name T939
Test name
Test status
Simulation time 21962567 ps
CPU time 0.85 seconds
Started Jan 24 04:19:06 PM PST 24
Finished Jan 24 04:19:09 PM PST 24
Peak memory 201236 kb
Host smart-951c0a76-938d-4f40-a7b4-d19f040ca704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253152435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.253152435
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.812873198
Short name T577
Test name
Test status
Simulation time 7625200135 ps
CPU time 54.57 seconds
Started Jan 24 04:19:14 PM PST 24
Finished Jan 24 04:20:10 PM PST 24
Peak memory 201704 kb
Host smart-acf7ce36-ecfe-43e5-b0a2-df052d0474a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812873198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.812873198
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.4176145782
Short name T9
Test name
Test status
Simulation time 48782562177 ps
CPU time 869.3 seconds
Started Jan 24 04:19:15 PM PST 24
Finished Jan 24 04:33:45 PM PST 24
Peak memory 210112 kb
Host smart-818685ce-9d7a-4b9c-a53c-5dad19848b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4176145782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.4176145782
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.3959744468
Short name T105
Test name
Test status
Simulation time 29624846 ps
CPU time 0.81 seconds
Started Jan 24 04:19:06 PM PST 24
Finished Jan 24 04:19:09 PM PST 24
Peak memory 201312 kb
Host smart-6b9ee877-cfda-4a3c-8d1d-3f09169540ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959744468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3959744468
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.873895958
Short name T517
Test name
Test status
Simulation time 11960204 ps
CPU time 0.7 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:43 PM PST 24
Peak memory 201264 kb
Host smart-f3a9c082-b608-4004-a2ad-37a2a29c0e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873895958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkm
gr_alert_test.873895958
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2905225591
Short name T688
Test name
Test status
Simulation time 13767703 ps
CPU time 0.78 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:43 PM PST 24
Peak memory 201244 kb
Host smart-d09b9207-41bf-4362-9a19-25c8961352d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905225591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2905225591
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1680068662
Short name T469
Test name
Test status
Simulation time 41093035 ps
CPU time 0.83 seconds
Started Jan 24 04:19:39 PM PST 24
Finished Jan 24 04:19:41 PM PST 24
Peak memory 201272 kb
Host smart-19abd963-6193-4a0e-95b2-302770a57e46
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680068662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1680068662
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.4223773749
Short name T637
Test name
Test status
Simulation time 15916856 ps
CPU time 0.77 seconds
Started Jan 24 06:46:56 PM PST 24
Finished Jan 24 06:46:58 PM PST 24
Peak memory 201320 kb
Host smart-496e856e-1795-471e-92fe-eb5c2d84e420
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223773749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.4223773749
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.929934917
Short name T108
Test name
Test status
Simulation time 1421204377 ps
CPU time 6.66 seconds
Started Jan 24 04:19:20 PM PST 24
Finished Jan 24 04:19:28 PM PST 24
Peak memory 201364 kb
Host smart-5325e232-3683-4b5c-994e-3dbffc200735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929934917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.929934917
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3560519936
Short name T658
Test name
Test status
Simulation time 144099498 ps
CPU time 1.47 seconds
Started Jan 24 04:19:20 PM PST 24
Finished Jan 24 04:19:22 PM PST 24
Peak memory 201440 kb
Host smart-6b473fee-6aa1-4186-8e44-abc78c890c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560519936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3560519936
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1421119081
Short name T386
Test name
Test status
Simulation time 23884553 ps
CPU time 0.86 seconds
Started Jan 24 04:19:29 PM PST 24
Finished Jan 24 04:19:32 PM PST 24
Peak memory 201312 kb
Host smart-45349c1a-582e-4bc7-aa1f-fdc5318c8510
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421119081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1421119081
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.665221611
Short name T832
Test name
Test status
Simulation time 72313016 ps
CPU time 1.02 seconds
Started Jan 24 04:19:42 PM PST 24
Finished Jan 24 04:19:44 PM PST 24
Peak memory 201336 kb
Host smart-37453d6e-b652-462f-a685-2aa996e98b23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665221611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.clkmgr_lc_clk_byp_req_intersig_mubi.665221611
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1142275096
Short name T884
Test name
Test status
Simulation time 25267351 ps
CPU time 0.86 seconds
Started Jan 24 04:19:31 PM PST 24
Finished Jan 24 04:19:33 PM PST 24
Peak memory 201292 kb
Host smart-061c2168-d2a8-44c3-9202-f387904776aa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142275096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1142275096
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.763756077
Short name T911
Test name
Test status
Simulation time 14722884 ps
CPU time 0.77 seconds
Started Jan 24 04:19:32 PM PST 24
Finished Jan 24 04:19:33 PM PST 24
Peak memory 201180 kb
Host smart-97c5e1ef-7060-4402-9478-342204ada921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763756077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.763756077
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.916869550
Short name T682
Test name
Test status
Simulation time 800067730 ps
CPU time 3.36 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:45 PM PST 24
Peak memory 201440 kb
Host smart-5ab35fa8-1ad7-4195-980d-c9e0e6a472b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916869550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.916869550
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.468179182
Short name T929
Test name
Test status
Simulation time 96880141 ps
CPU time 1.03 seconds
Started Jan 24 04:19:15 PM PST 24
Finished Jan 24 04:19:17 PM PST 24
Peak memory 201328 kb
Host smart-9b7cba26-4cb8-40e7-8f23-a43d98e420df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468179182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.468179182
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.10578751
Short name T409
Test name
Test status
Simulation time 225060493 ps
CPU time 1.62 seconds
Started Jan 24 04:19:41 PM PST 24
Finished Jan 24 04:19:45 PM PST 24
Peak memory 201280 kb
Host smart-35f39db8-a8a1-4ade-9bc0-96f369e36a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_stress_all.10578751
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2914913924
Short name T414
Test name
Test status
Simulation time 25918401379 ps
CPU time 242.64 seconds
Started Jan 24 04:50:07 PM PST 24
Finished Jan 24 04:54:10 PM PST 24
Peak memory 210064 kb
Host smart-ad167d67-ff28-4c98-89b5-01aa80dcd946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2914913924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2914913924
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.1037127574
Short name T102
Test name
Test status
Simulation time 13277430 ps
CPU time 0.73 seconds
Started Jan 24 04:19:32 PM PST 24
Finished Jan 24 04:19:34 PM PST 24
Peak memory 201152 kb
Host smart-973283f0-15a2-4a85-885f-c4fd56171b9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037127574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1037127574
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.3488111820
Short name T319
Test name
Test status
Simulation time 19919685 ps
CPU time 0.81 seconds
Started Jan 24 04:19:57 PM PST 24
Finished Jan 24 04:19:59 PM PST 24
Peak memory 201284 kb
Host smart-792a0e8c-82d6-48e2-8e07-8201c14e2820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488111820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.3488111820
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3003974110
Short name T330
Test name
Test status
Simulation time 62795829 ps
CPU time 1.02 seconds
Started Jan 24 04:19:56 PM PST 24
Finished Jan 24 04:19:58 PM PST 24
Peak memory 201252 kb
Host smart-d38d3884-91ad-4d36-994b-3e5259f8f1f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003974110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3003974110
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.2710256785
Short name T730
Test name
Test status
Simulation time 14544886 ps
CPU time 0.76 seconds
Started Jan 24 04:46:58 PM PST 24
Finished Jan 24 04:47:00 PM PST 24
Peak memory 200128 kb
Host smart-5fe1784d-aa8e-4abe-9d0c-73790e572ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710256785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.2710256785
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.573959063
Short name T497
Test name
Test status
Simulation time 102956300 ps
CPU time 1.11 seconds
Started Jan 24 04:19:59 PM PST 24
Finished Jan 24 04:20:02 PM PST 24
Peak memory 201240 kb
Host smart-2777f0dd-7ef1-4a90-b7de-8f41859285c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573959063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_div_intersig_mubi.573959063
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.493575791
Short name T457
Test name
Test status
Simulation time 20319627 ps
CPU time 0.81 seconds
Started Jan 24 04:19:41 PM PST 24
Finished Jan 24 04:19:43 PM PST 24
Peak memory 201304 kb
Host smart-65b75a46-6f48-4fe8-a456-21b3d3e7d913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493575791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.493575791
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.191518703
Short name T382
Test name
Test status
Simulation time 330673645 ps
CPU time 1.99 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:43 PM PST 24
Peak memory 201300 kb
Host smart-01d401e7-811d-44f7-a0b5-47c39d0481a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191518703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.191518703
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.3092525319
Short name T941
Test name
Test status
Simulation time 257704703 ps
CPU time 2.01 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:43 PM PST 24
Peak memory 201376 kb
Host smart-4545b9e4-c426-43f3-ae8b-c966d62e2152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092525319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.3092525319
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2947990435
Short name T504
Test name
Test status
Simulation time 32864701 ps
CPU time 0.96 seconds
Started Jan 24 04:19:49 PM PST 24
Finished Jan 24 04:19:51 PM PST 24
Peak memory 201316 kb
Host smart-a04b7220-2001-4716-839e-088ea427fa6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947990435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.2947990435
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2798096213
Short name T287
Test name
Test status
Simulation time 28158142 ps
CPU time 0.92 seconds
Started Jan 24 04:31:02 PM PST 24
Finished Jan 24 04:31:12 PM PST 24
Peak memory 201256 kb
Host smart-5554283a-0e27-488b-bd79-110dab85a652
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798096213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.2798096213
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2677344855
Short name T709
Test name
Test status
Simulation time 48647109 ps
CPU time 0.96 seconds
Started Jan 24 04:19:53 PM PST 24
Finished Jan 24 04:19:55 PM PST 24
Peak memory 201336 kb
Host smart-29c9e531-e714-45fc-aa32-7427e85c5aae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677344855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.2677344855
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.213058317
Short name T856
Test name
Test status
Simulation time 14701876 ps
CPU time 0.73 seconds
Started Jan 24 05:53:55 PM PST 24
Finished Jan 24 05:53:56 PM PST 24
Peak memory 201160 kb
Host smart-ee3a575f-5f6f-4422-85a0-a4e747398549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213058317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.213058317
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.2576479142
Short name T275
Test name
Test status
Simulation time 156168870 ps
CPU time 1.46 seconds
Started Jan 24 04:24:37 PM PST 24
Finished Jan 24 04:24:40 PM PST 24
Peak memory 201220 kb
Host smart-f03ff65c-31d0-4b4d-87af-28e7f9439ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576479142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2576479142
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.4238252338
Short name T456
Test name
Test status
Simulation time 31100034 ps
CPU time 0.84 seconds
Started Jan 24 04:19:40 PM PST 24
Finished Jan 24 04:19:42 PM PST 24
Peak memory 201248 kb
Host smart-5022f550-9667-4139-a30b-104c53ac0649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238252338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.4238252338
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.783592226
Short name T548
Test name
Test status
Simulation time 8322921774 ps
CPU time 54.64 seconds
Started Jan 24 04:19:56 PM PST 24
Finished Jan 24 04:20:52 PM PST 24
Peak memory 201676 kb
Host smart-280cc34c-225c-4531-ad84-8a6eb7fc0a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783592226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.783592226
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3834753679
Short name T874
Test name
Test status
Simulation time 94944813105 ps
CPU time 817.87 seconds
Started Jan 24 04:20:02 PM PST 24
Finished Jan 24 04:33:42 PM PST 24
Peak memory 208860 kb
Host smart-5cb269bd-d54e-43ca-a718-41d0337a54c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3834753679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3834753679
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2423084038
Short name T101
Test name
Test status
Simulation time 101834505 ps
CPU time 1.13 seconds
Started Jan 24 04:19:52 PM PST 24
Finished Jan 24 04:19:54 PM PST 24
Peak memory 201256 kb
Host smart-80693a9e-ec9a-428e-906a-893f8bbcf15d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423084038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2423084038
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2098626021
Short name T478
Test name
Test status
Simulation time 17013186 ps
CPU time 0.81 seconds
Started Jan 24 04:20:06 PM PST 24
Finished Jan 24 04:20:08 PM PST 24
Peak memory 201304 kb
Host smart-da73892f-3ea9-4175-a310-30e28efd085c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098626021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2098626021
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.288811492
Short name T419
Test name
Test status
Simulation time 79396055 ps
CPU time 1.04 seconds
Started Jan 24 05:01:49 PM PST 24
Finished Jan 24 05:02:11 PM PST 24
Peak memory 201292 kb
Host smart-9d0eee28-2c9e-4d19-8241-f09d74ff2863
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288811492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.288811492
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2826989233
Short name T723
Test name
Test status
Simulation time 14231728 ps
CPU time 0.71 seconds
Started Jan 24 04:20:02 PM PST 24
Finished Jan 24 04:20:04 PM PST 24
Peak memory 199916 kb
Host smart-5be50cf8-032d-4d68-8619-96fb444e44f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826989233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2826989233
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.1457673165
Short name T489
Test name
Test status
Simulation time 23130864 ps
CPU time 0.87 seconds
Started Jan 24 04:44:59 PM PST 24
Finished Jan 24 04:45:06 PM PST 24
Peak memory 201320 kb
Host smart-b62ca83f-3f93-4897-a1b2-1330d8d3da91
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457673165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.1457673165
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.3518820629
Short name T63
Test name
Test status
Simulation time 20737867 ps
CPU time 0.81 seconds
Started Jan 24 04:19:57 PM PST 24
Finished Jan 24 04:19:59 PM PST 24
Peak memory 201320 kb
Host smart-78b888cd-7d15-485a-b7f4-8ada7947d2bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518820629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3518820629
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2228603803
Short name T644
Test name
Test status
Simulation time 266039866 ps
CPU time 1.56 seconds
Started Jan 24 04:20:02 PM PST 24
Finished Jan 24 04:20:05 PM PST 24
Peak memory 200700 kb
Host smart-097b9020-a784-45f6-8208-529b24049a26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228603803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2228603803
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.2501266119
Short name T725
Test name
Test status
Simulation time 139114266 ps
CPU time 1.52 seconds
Started Jan 24 04:19:58 PM PST 24
Finished Jan 24 04:20:01 PM PST 24
Peak memory 201372 kb
Host smart-e1a99161-d64d-4515-81b5-d1a6b57c5f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501266119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.2501266119
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.720296139
Short name T936
Test name
Test status
Simulation time 23468760 ps
CPU time 0.87 seconds
Started Jan 24 04:19:56 PM PST 24
Finished Jan 24 04:19:58 PM PST 24
Peak memory 201248 kb
Host smart-d7206a29-b38d-4d31-82b4-aca9334d98a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720296139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.720296139
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.805709445
Short name T384
Test name
Test status
Simulation time 238251326 ps
CPU time 1.49 seconds
Started Jan 24 04:45:27 PM PST 24
Finished Jan 24 04:45:29 PM PST 24
Peak memory 201292 kb
Host smart-caaeb21f-a2af-44e6-b72c-d7535b215a54
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805709445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.clkmgr_lc_clk_byp_req_intersig_mubi.805709445
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1841772475
Short name T766
Test name
Test status
Simulation time 108725000 ps
CPU time 1.03 seconds
Started Jan 24 04:19:56 PM PST 24
Finished Jan 24 04:19:58 PM PST 24
Peak memory 201336 kb
Host smart-9e0f4ca8-7042-4111-8e90-da2d3b056faa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841772475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1841772475
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.2641400476
Short name T388
Test name
Test status
Simulation time 42205266 ps
CPU time 0.83 seconds
Started Jan 24 04:34:08 PM PST 24
Finished Jan 24 04:34:15 PM PST 24
Peak memory 201168 kb
Host smart-6f002137-f3cb-4cc7-821a-069279da3820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641400476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2641400476
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.2027455764
Short name T967
Test name
Test status
Simulation time 538450424 ps
CPU time 3.34 seconds
Started Jan 24 04:20:02 PM PST 24
Finished Jan 24 04:20:07 PM PST 24
Peak memory 200052 kb
Host smart-c7e0e325-b76a-4915-95fd-070a8081a43e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027455764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2027455764
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.452727126
Short name T789
Test name
Test status
Simulation time 23225626 ps
CPU time 0.89 seconds
Started Jan 24 04:19:56 PM PST 24
Finished Jan 24 04:19:58 PM PST 24
Peak memory 201324 kb
Host smart-28ac50cd-577c-414f-9efa-526c15a487b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452727126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.452727126
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1008061081
Short name T770
Test name
Test status
Simulation time 4567685875 ps
CPU time 23.5 seconds
Started Jan 24 04:19:57 PM PST 24
Finished Jan 24 04:20:22 PM PST 24
Peak memory 201672 kb
Host smart-aa9f1660-5eda-4410-b653-7a0c2ccc545b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008061081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1008061081
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.3345955618
Short name T705
Test name
Test status
Simulation time 179116995259 ps
CPU time 926.21 seconds
Started Jan 24 04:19:58 PM PST 24
Finished Jan 24 04:35:26 PM PST 24
Peak memory 218132 kb
Host smart-4be0623f-5450-40f9-9e0f-b545875a29b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3345955618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3345955618
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.3524093809
Short name T451
Test name
Test status
Simulation time 95064577 ps
CPU time 1.13 seconds
Started Jan 24 04:19:57 PM PST 24
Finished Jan 24 04:20:00 PM PST 24
Peak memory 201316 kb
Host smart-8ab92499-eebd-4893-a70a-1835baac1838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524093809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3524093809
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1483652388
Short name T790
Test name
Test status
Simulation time 42590167 ps
CPU time 0.79 seconds
Started Jan 24 04:20:31 PM PST 24
Finished Jan 24 04:20:33 PM PST 24
Peak memory 201284 kb
Host smart-ad56f51a-9579-4a8d-aa0d-3a2c613d8006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483652388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1483652388
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1606241223
Short name T574
Test name
Test status
Simulation time 44580546 ps
CPU time 0.88 seconds
Started Jan 24 04:20:22 PM PST 24
Finished Jan 24 04:20:24 PM PST 24
Peak memory 201304 kb
Host smart-2b959e69-abde-41ec-bc5b-6392ace2ece2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606241223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.1606241223
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.920465732
Short name T932
Test name
Test status
Simulation time 33858788 ps
CPU time 0.73 seconds
Started Jan 24 04:20:19 PM PST 24
Finished Jan 24 04:20:21 PM PST 24
Peak memory 200124 kb
Host smart-e1304d00-fb67-4254-8d71-921eb348bf61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920465732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.920465732
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.484614949
Short name T338
Test name
Test status
Simulation time 72797416 ps
CPU time 1.04 seconds
Started Jan 24 04:20:22 PM PST 24
Finished Jan 24 04:20:24 PM PST 24
Peak memory 201300 kb
Host smart-60a88860-c885-4c10-9c24-00f11cc0fe12
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484614949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_div_intersig_mubi.484614949
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.490267801
Short name T290
Test name
Test status
Simulation time 69603551 ps
CPU time 0.96 seconds
Started Jan 24 04:20:03 PM PST 24
Finished Jan 24 04:20:06 PM PST 24
Peak memory 201256 kb
Host smart-3a11fa46-93b1-48a3-8b7d-5b593f943480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490267801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.490267801
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.3307870605
Short name T507
Test name
Test status
Simulation time 1542803384 ps
CPU time 7.02 seconds
Started Jan 24 04:20:04 PM PST 24
Finished Jan 24 04:20:12 PM PST 24
Peak memory 201352 kb
Host smart-3096a5da-5a6e-48fa-880a-38b71ed3600d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307870605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3307870605
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.2422665273
Short name T906
Test name
Test status
Simulation time 513370960 ps
CPU time 2.64 seconds
Started Jan 24 04:20:04 PM PST 24
Finished Jan 24 04:20:08 PM PST 24
Peak memory 201444 kb
Host smart-5fd8bbc1-e2ed-4753-b613-1cf1f854dfc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422665273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.2422665273
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3397548741
Short name T441
Test name
Test status
Simulation time 16088394 ps
CPU time 0.73 seconds
Started Jan 24 04:20:30 PM PST 24
Finished Jan 24 04:20:33 PM PST 24
Peak memory 201160 kb
Host smart-9f6fbb2c-0dbf-4fc4-b109-42e3244410d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397548741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.3397548741
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2055081719
Short name T823
Test name
Test status
Simulation time 55504466 ps
CPU time 0.85 seconds
Started Jan 24 04:20:21 PM PST 24
Finished Jan 24 04:20:23 PM PST 24
Peak memory 201252 kb
Host smart-f12d88fe-2b47-4521-9034-6c3346ba0d10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055081719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.2055081719
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.3747854999
Short name T608
Test name
Test status
Simulation time 91461390 ps
CPU time 0.96 seconds
Started Jan 24 04:20:24 PM PST 24
Finished Jan 24 04:20:27 PM PST 24
Peak memory 201312 kb
Host smart-de84676b-56e8-4d84-a922-b4cb66c755f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747854999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.3747854999
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2243679592
Short name T531
Test name
Test status
Simulation time 31033857 ps
CPU time 0.83 seconds
Started Jan 24 04:40:09 PM PST 24
Finished Jan 24 04:40:11 PM PST 24
Peak memory 201164 kb
Host smart-0b55b610-c9a1-48c8-9b67-b5d9e5b216ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243679592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2243679592
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2063791663
Short name T364
Test name
Test status
Simulation time 1252310774 ps
CPU time 7.08 seconds
Started Jan 24 04:20:22 PM PST 24
Finished Jan 24 04:20:30 PM PST 24
Peak memory 201488 kb
Host smart-981b36e5-fb15-450c-b953-f4d559debc34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063791663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2063791663
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.1975832938
Short name T813
Test name
Test status
Simulation time 48803027 ps
CPU time 0.94 seconds
Started Jan 24 04:20:06 PM PST 24
Finished Jan 24 04:20:09 PM PST 24
Peak memory 201288 kb
Host smart-e2f4dcf6-180b-4e12-a475-199e03276cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975832938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1975832938
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.2582518723
Short name T783
Test name
Test status
Simulation time 5957967683 ps
CPU time 24.89 seconds
Started Jan 24 04:20:20 PM PST 24
Finished Jan 24 04:20:46 PM PST 24
Peak memory 201736 kb
Host smart-87522fda-03d6-446d-bff0-5752cceb0278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582518723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.2582518723
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.4121746279
Short name T154
Test name
Test status
Simulation time 112898900756 ps
CPU time 1013.74 seconds
Started Jan 24 04:20:26 PM PST 24
Finished Jan 24 04:37:21 PM PST 24
Peak memory 210048 kb
Host smart-bad1d6c9-1dba-40fa-804f-129136ff53c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4121746279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.4121746279
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.1625008646
Short name T623
Test name
Test status
Simulation time 13901462 ps
CPU time 0.78 seconds
Started Jan 24 04:20:39 PM PST 24
Finished Jan 24 04:20:41 PM PST 24
Peak memory 201320 kb
Host smart-db4e8764-3c05-4492-82b0-9b98923b3ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625008646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.1625008646
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3159387485
Short name T496
Test name
Test status
Simulation time 45628627 ps
CPU time 0.96 seconds
Started Jan 24 05:40:49 PM PST 24
Finished Jan 24 05:40:50 PM PST 24
Peak memory 201304 kb
Host smart-0c760911-ad8c-4332-9493-51adf723eab4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159387485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.3159387485
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.464395069
Short name T889
Test name
Test status
Simulation time 36547474 ps
CPU time 0.78 seconds
Started Jan 24 04:20:36 PM PST 24
Finished Jan 24 04:20:38 PM PST 24
Peak memory 200116 kb
Host smart-9ff9c867-1fea-41f0-8612-fc615d9bff36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464395069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.464395069
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.1958345073
Short name T538
Test name
Test status
Simulation time 18037264 ps
CPU time 0.77 seconds
Started Jan 24 04:20:31 PM PST 24
Finished Jan 24 04:20:34 PM PST 24
Peak memory 201268 kb
Host smart-e6fedeac-b8fc-43fe-86c4-cba3c5b6d701
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958345073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.1958345073
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.154031427
Short name T636
Test name
Test status
Simulation time 83226794 ps
CPU time 1.01 seconds
Started Jan 24 04:20:36 PM PST 24
Finished Jan 24 04:20:39 PM PST 24
Peak memory 201308 kb
Host smart-6e43fbd7-0f32-4668-a599-08103f8eac0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154031427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.154031427
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.323115495
Short name T616
Test name
Test status
Simulation time 340880921 ps
CPU time 2.06 seconds
Started Jan 24 04:20:35 PM PST 24
Finished Jan 24 04:20:39 PM PST 24
Peak memory 201320 kb
Host smart-0425e6ad-2f03-4a54-9ff2-5aafbad58e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323115495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.323115495
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.2203182923
Short name T718
Test name
Test status
Simulation time 2397969491 ps
CPU time 8.85 seconds
Started Jan 24 04:20:36 PM PST 24
Finished Jan 24 04:20:46 PM PST 24
Peak memory 201732 kb
Host smart-bf1968b9-1053-4659-a9e3-11e01f8c9431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203182923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.2203182923
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.457691812
Short name T327
Test name
Test status
Simulation time 62344950 ps
CPU time 1.22 seconds
Started Jan 24 04:35:00 PM PST 24
Finished Jan 24 04:35:08 PM PST 24
Peak memory 201284 kb
Host smart-64bf4d9c-dc10-48d6-8b7d-539540845227
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457691812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.457691812
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.939973409
Short name T802
Test name
Test status
Simulation time 24111994 ps
CPU time 0.8 seconds
Started Jan 24 04:20:30 PM PST 24
Finished Jan 24 04:20:33 PM PST 24
Peak memory 201292 kb
Host smart-6610345e-9825-4887-8a34-d6184f6d5245
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939973409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.clkmgr_lc_clk_byp_req_intersig_mubi.939973409
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3910479783
Short name T865
Test name
Test status
Simulation time 51153099 ps
CPU time 1 seconds
Started Jan 24 05:30:17 PM PST 24
Finished Jan 24 05:30:19 PM PST 24
Peak memory 201292 kb
Host smart-b26fa8d2-e620-4ae5-a74d-339660145fd7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910479783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3910479783
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.3671834633
Short name T424
Test name
Test status
Simulation time 23761537 ps
CPU time 0.74 seconds
Started Jan 24 04:20:32 PM PST 24
Finished Jan 24 04:20:35 PM PST 24
Peak memory 201176 kb
Host smart-a0ff59d9-c911-49d5-a004-a36fd7a10f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671834633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3671834633
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3215823756
Short name T950
Test name
Test status
Simulation time 797148108 ps
CPU time 3.34 seconds
Started Jan 24 04:20:34 PM PST 24
Finished Jan 24 04:20:39 PM PST 24
Peak memory 201436 kb
Host smart-78ee1d90-9d63-4da4-9813-40fd7f64e8ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215823756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3215823756
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.1914639354
Short name T365
Test name
Test status
Simulation time 93859387 ps
CPU time 1 seconds
Started Jan 24 04:20:30 PM PST 24
Finished Jan 24 04:20:33 PM PST 24
Peak memory 201264 kb
Host smart-17c9e0cc-fab5-40bb-8fb7-ae13a14d4d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914639354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1914639354
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.2818963520
Short name T491
Test name
Test status
Simulation time 387700446 ps
CPU time 3.92 seconds
Started Jan 24 04:20:47 PM PST 24
Finished Jan 24 04:20:51 PM PST 24
Peak memory 201612 kb
Host smart-394d4895-e94e-4ac5-97b2-9761313633e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818963520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.2818963520
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.635339714
Short name T398
Test name
Test status
Simulation time 33969475117 ps
CPU time 540.72 seconds
Started Jan 24 04:20:42 PM PST 24
Finished Jan 24 04:29:43 PM PST 24
Peak memory 210428 kb
Host smart-62728c46-d75a-4c11-93ac-7b912e624039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=635339714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.635339714
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.3777469550
Short name T448
Test name
Test status
Simulation time 143936538 ps
CPU time 1.35 seconds
Started Jan 24 04:20:29 PM PST 24
Finished Jan 24 04:20:33 PM PST 24
Peak memory 201280 kb
Host smart-ed42236c-4d41-4019-b0b6-098a3f092dba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777469550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3777469550
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.2937457554
Short name T576
Test name
Test status
Simulation time 26702307 ps
CPU time 0.82 seconds
Started Jan 24 04:21:00 PM PST 24
Finished Jan 24 04:21:02 PM PST 24
Peak memory 201172 kb
Host smart-400175c8-24a4-47fb-80fd-709573fb1403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937457554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.2937457554
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.246865061
Short name T445
Test name
Test status
Simulation time 33051555 ps
CPU time 0.78 seconds
Started Jan 24 04:20:51 PM PST 24
Finished Jan 24 04:20:52 PM PST 24
Peak memory 201304 kb
Host smart-b014fe71-8ed6-491d-b1be-bd5c14342314
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246865061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.246865061
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.222606282
Short name T611
Test name
Test status
Simulation time 17834560 ps
CPU time 0.78 seconds
Started Jan 24 04:20:50 PM PST 24
Finished Jan 24 04:20:52 PM PST 24
Peak memory 200156 kb
Host smart-b84c196e-b9f2-4f80-97e9-bce48d237e28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222606282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.222606282
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.1825187984
Short name T396
Test name
Test status
Simulation time 34838421 ps
CPU time 0.84 seconds
Started Jan 24 04:20:51 PM PST 24
Finished Jan 24 04:20:53 PM PST 24
Peak memory 201292 kb
Host smart-2a98182a-5670-4aca-bb77-3e4ba8b42ab2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825187984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.1825187984
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.3215926787
Short name T863
Test name
Test status
Simulation time 23535174 ps
CPU time 0.9 seconds
Started Jan 24 04:20:42 PM PST 24
Finished Jan 24 04:20:44 PM PST 24
Peak memory 201280 kb
Host smart-64dcd905-e62e-4683-9277-ab580d0a91fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215926787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3215926787
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1561392290
Short name T573
Test name
Test status
Simulation time 2247122731 ps
CPU time 9.07 seconds
Started Jan 24 04:20:50 PM PST 24
Finished Jan 24 04:21:00 PM PST 24
Peak memory 201676 kb
Host smart-4fb83393-8fb2-467c-965d-b8466a68ef14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561392290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1561392290
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.96274012
Short name T729
Test name
Test status
Simulation time 1102162416 ps
CPU time 8.47 seconds
Started Jan 24 04:20:54 PM PST 24
Finished Jan 24 04:21:04 PM PST 24
Peak memory 201412 kb
Host smart-deeb8de6-4a02-4e7a-9be0-a20de47e817c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96274012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_tim
eout.96274012
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2659392595
Short name T778
Test name
Test status
Simulation time 50252055 ps
CPU time 0.98 seconds
Started Jan 24 04:20:53 PM PST 24
Finished Jan 24 04:20:55 PM PST 24
Peak memory 201284 kb
Host smart-1515895c-133d-4d2e-ab18-f8362ee9cbae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659392595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.2659392595
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3059235801
Short name T816
Test name
Test status
Simulation time 63012397 ps
CPU time 0.97 seconds
Started Jan 24 05:46:08 PM PST 24
Finished Jan 24 05:46:09 PM PST 24
Peak memory 201288 kb
Host smart-59b3bf03-5ab8-4f87-9dad-0677b7f82c35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059235801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3059235801
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3185356670
Short name T834
Test name
Test status
Simulation time 28298679 ps
CPU time 0.78 seconds
Started Jan 24 05:30:58 PM PST 24
Finished Jan 24 05:30:59 PM PST 24
Peak memory 201300 kb
Host smart-c4e5bb30-94d6-4b7b-90b4-78330e3cca87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185356670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3185356670
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.4196774085
Short name T808
Test name
Test status
Simulation time 26053382 ps
CPU time 0.76 seconds
Started Jan 24 04:20:54 PM PST 24
Finished Jan 24 04:20:55 PM PST 24
Peak memory 201120 kb
Host smart-646e74d6-28e6-429f-a0e7-06f2abb73293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196774085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.4196774085
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.1046365266
Short name T689
Test name
Test status
Simulation time 161900278 ps
CPU time 1.23 seconds
Started Jan 24 04:20:42 PM PST 24
Finished Jan 24 04:20:44 PM PST 24
Peak memory 201212 kb
Host smart-05c8a537-77f7-4f3e-8d70-dad74326c67a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046365266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1046365266
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.137367300
Short name T726
Test name
Test status
Simulation time 149202056 ps
CPU time 1.16 seconds
Started Jan 24 04:20:58 PM PST 24
Finished Jan 24 04:21:01 PM PST 24
Peak memory 201100 kb
Host smart-197aa7af-73ab-42ce-a125-e2f218f91755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137367300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.137367300
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.1945346616
Short name T917
Test name
Test status
Simulation time 201967567386 ps
CPU time 1375.67 seconds
Started Jan 24 04:38:01 PM PST 24
Finished Jan 24 05:00:57 PM PST 24
Peak memory 210004 kb
Host smart-58fee08a-f479-48c2-a11f-fc7525145e49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1945346616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1945346616
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.4004463931
Short name T572
Test name
Test status
Simulation time 68531398 ps
CPU time 1.12 seconds
Started Jan 24 04:20:51 PM PST 24
Finished Jan 24 04:20:53 PM PST 24
Peak memory 201256 kb
Host smart-d3281fce-2a10-43cb-b271-4bbc83657a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004463931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.4004463931
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.171123196
Short name T317
Test name
Test status
Simulation time 118384807 ps
CPU time 1.06 seconds
Started Jan 24 04:21:23 PM PST 24
Finished Jan 24 04:21:38 PM PST 24
Peak memory 201308 kb
Host smart-a737f128-8085-4b8e-9ef1-66f28046e657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171123196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkm
gr_alert_test.171123196
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.3195171518
Short name T458
Test name
Test status
Simulation time 13310823 ps
CPU time 0.73 seconds
Started Jan 24 04:40:11 PM PST 24
Finished Jan 24 04:40:13 PM PST 24
Peak memory 201300 kb
Host smart-b31e3ac4-c189-43bd-8b10-80bb415a68c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195171518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.3195171518
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.1158476561
Short name T137
Test name
Test status
Simulation time 23492573 ps
CPU time 0.71 seconds
Started Jan 24 04:21:00 PM PST 24
Finished Jan 24 04:21:02 PM PST 24
Peak memory 201192 kb
Host smart-9809ee46-1441-4fd2-afcd-e72b1d4831bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158476561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1158476561
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.230991691
Short name T668
Test name
Test status
Simulation time 21794458 ps
CPU time 0.88 seconds
Started Jan 24 04:21:14 PM PST 24
Finished Jan 24 04:21:18 PM PST 24
Peak memory 201300 kb
Host smart-b078431d-2896-4b24-8a50-7254623fa4e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230991691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.clkmgr_div_intersig_mubi.230991691
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2413952215
Short name T846
Test name
Test status
Simulation time 72808629 ps
CPU time 0.9 seconds
Started Jan 24 04:21:01 PM PST 24
Finished Jan 24 04:21:04 PM PST 24
Peak memory 201300 kb
Host smart-9ca01103-28d9-4b9a-b3a9-50b2746ba9f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413952215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2413952215
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.241544277
Short name T873
Test name
Test status
Simulation time 1757363878 ps
CPU time 13.5 seconds
Started Jan 24 04:21:00 PM PST 24
Finished Jan 24 04:21:15 PM PST 24
Peak memory 201504 kb
Host smart-39b912dd-ca3e-4d42-852d-189965260f13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241544277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.241544277
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2214283151
Short name T575
Test name
Test status
Simulation time 1576524356 ps
CPU time 10.55 seconds
Started Jan 24 04:20:58 PM PST 24
Finished Jan 24 04:21:09 PM PST 24
Peak memory 201436 kb
Host smart-933be671-1cb5-422f-b2e2-ca46ee2cc59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214283151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2214283151
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3017637802
Short name T324
Test name
Test status
Simulation time 96182856 ps
CPU time 1.1 seconds
Started Jan 24 06:06:12 PM PST 24
Finished Jan 24 06:06:14 PM PST 24
Peak memory 201304 kb
Host smart-9ec59526-3442-4da3-9c02-ecd88c2e0385
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017637802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.3017637802
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.4043899202
Short name T811
Test name
Test status
Simulation time 20135512 ps
CPU time 0.81 seconds
Started Jan 24 04:21:13 PM PST 24
Finished Jan 24 04:21:16 PM PST 24
Peak memory 201292 kb
Host smart-f8830a20-e318-40c9-bd99-1fd31250fc50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043899202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.4043899202
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3953489728
Short name T852
Test name
Test status
Simulation time 25489184 ps
CPU time 0.88 seconds
Started Jan 24 04:21:16 PM PST 24
Finished Jan 24 04:21:26 PM PST 24
Peak memory 201236 kb
Host smart-a609409a-feb1-4f23-8fa9-c7fc7cde171e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953489728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.3953489728
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.2889384488
Short name T593
Test name
Test status
Simulation time 17728685 ps
CPU time 0.74 seconds
Started Jan 24 04:20:55 PM PST 24
Finished Jan 24 04:20:57 PM PST 24
Peak memory 201120 kb
Host smart-d5411522-d6f9-47f2-82e6-6f139c944c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889384488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2889384488
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.2708679534
Short name T918
Test name
Test status
Simulation time 542329331 ps
CPU time 2.7 seconds
Started Jan 24 04:21:11 PM PST 24
Finished Jan 24 04:21:15 PM PST 24
Peak memory 201316 kb
Host smart-4c1ec16e-11d1-449f-ab11-823a81f0ead6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708679534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2708679534
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.2074751111
Short name T830
Test name
Test status
Simulation time 16325890 ps
CPU time 0.85 seconds
Started Jan 24 04:21:00 PM PST 24
Finished Jan 24 04:21:02 PM PST 24
Peak memory 201244 kb
Host smart-9400cf11-9e3c-4e88-9ba9-aa81976a4ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074751111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2074751111
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.3643489192
Short name T298
Test name
Test status
Simulation time 392428642 ps
CPU time 2.67 seconds
Started Jan 24 04:21:22 PM PST 24
Finished Jan 24 04:21:39 PM PST 24
Peak memory 201420 kb
Host smart-abeb41a0-1d2d-4ca4-8213-5a3459e43c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643489192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.3643489192
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3283357015
Short name T159
Test name
Test status
Simulation time 57853285524 ps
CPU time 349.1 seconds
Started Jan 24 04:21:14 PM PST 24
Finished Jan 24 04:27:06 PM PST 24
Peak memory 210004 kb
Host smart-733e0649-444c-4f0c-83b0-63547cb4f87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3283357015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3283357015
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.2382360922
Short name T348
Test name
Test status
Simulation time 17639129 ps
CPU time 0.78 seconds
Started Jan 24 04:20:58 PM PST 24
Finished Jan 24 04:20:59 PM PST 24
Peak memory 201276 kb
Host smart-60780971-006f-4dd3-86a4-916a51cf00c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382360922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2382360922
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.291877928
Short name T618
Test name
Test status
Simulation time 75034149 ps
CPU time 0.95 seconds
Started Jan 24 04:21:29 PM PST 24
Finished Jan 24 04:21:45 PM PST 24
Peak memory 201208 kb
Host smart-3ff80aa5-7506-4d55-bc49-fa8386a9af3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291877928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkm
gr_alert_test.291877928
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.155401076
Short name T21
Test name
Test status
Simulation time 15905047 ps
CPU time 0.83 seconds
Started Jan 24 04:21:29 PM PST 24
Finished Jan 24 04:21:45 PM PST 24
Peak memory 201344 kb
Host smart-d15cfd6f-5342-4a00-b308-38be15f55259
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155401076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.155401076
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.2288350182
Short name T578
Test name
Test status
Simulation time 18763673 ps
CPU time 0.74 seconds
Started Jan 24 04:21:23 PM PST 24
Finished Jan 24 04:21:38 PM PST 24
Peak memory 200128 kb
Host smart-fac607c7-be70-4fce-9942-8948b9a11490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288350182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2288350182
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3556145863
Short name T370
Test name
Test status
Simulation time 23833015 ps
CPU time 0.89 seconds
Started Jan 24 04:21:32 PM PST 24
Finished Jan 24 04:21:48 PM PST 24
Peak memory 201256 kb
Host smart-ec303183-894f-4675-b177-598e7c95582b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556145863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3556145863
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.3458787352
Short name T963
Test name
Test status
Simulation time 55393730 ps
CPU time 0.9 seconds
Started Jan 24 04:21:22 PM PST 24
Finished Jan 24 04:21:38 PM PST 24
Peak memory 201324 kb
Host smart-7e302a25-f996-4602-aca7-66c1baa5ede7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458787352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3458787352
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.3682182465
Short name T528
Test name
Test status
Simulation time 1098028494 ps
CPU time 7.81 seconds
Started Jan 24 04:45:11 PM PST 24
Finished Jan 24 04:45:22 PM PST 24
Peak memory 201408 kb
Host smart-a78814b6-b6b4-483a-84a5-76709c71ebed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682182465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.3682182465
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3359429763
Short name T869
Test name
Test status
Simulation time 19162804 ps
CPU time 0.79 seconds
Started Jan 24 04:29:09 PM PST 24
Finished Jan 24 04:29:11 PM PST 24
Peak memory 201204 kb
Host smart-c3a22b97-78af-4f69-bd8e-28b26ee370c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359429763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.3359429763
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2853711596
Short name T56
Test name
Test status
Simulation time 22227744 ps
CPU time 0.88 seconds
Started Jan 24 04:21:26 PM PST 24
Finished Jan 24 04:21:40 PM PST 24
Peak memory 201304 kb
Host smart-cdc786f0-f982-4fc5-9b0f-cc1a374e34b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853711596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2853711596
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.722779971
Short name T922
Test name
Test status
Simulation time 32527152 ps
CPU time 0.79 seconds
Started Jan 24 04:21:23 PM PST 24
Finished Jan 24 04:21:38 PM PST 24
Peak memory 201276 kb
Host smart-05e93729-60a9-4f61-b5db-649ee8ca7d51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722779971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.722779971
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3886465442
Short name T278
Test name
Test status
Simulation time 35642461 ps
CPU time 0.78 seconds
Started Jan 24 04:21:21 PM PST 24
Finished Jan 24 04:21:38 PM PST 24
Peak memory 201244 kb
Host smart-3f97022a-d1c0-48a1-9034-5a189fc21804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886465442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3886465442
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3776224018
Short name T412
Test name
Test status
Simulation time 311053108 ps
CPU time 2.18 seconds
Started Jan 24 04:21:27 PM PST 24
Finished Jan 24 04:21:44 PM PST 24
Peak memory 201264 kb
Host smart-0bc65f6f-57e1-4a09-95fd-e9d7778a8593
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776224018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3776224018
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.3534526252
Short name T652
Test name
Test status
Simulation time 28705387 ps
CPU time 0.87 seconds
Started Jan 24 04:50:56 PM PST 24
Finished Jan 24 04:50:57 PM PST 24
Peak memory 201244 kb
Host smart-cc90d74f-dc77-44af-9857-862a87c7177a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534526252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3534526252
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.93347251
Short name T13
Test name
Test status
Simulation time 23778232735 ps
CPU time 354.8 seconds
Started Jan 24 04:21:36 PM PST 24
Finished Jan 24 04:27:44 PM PST 24
Peak memory 210100 kb
Host smart-1912784d-0869-431c-bc2a-0164ca3bf03b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=93347251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.93347251
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3961164282
Short name T527
Test name
Test status
Simulation time 38103232 ps
CPU time 0.78 seconds
Started Jan 24 04:29:59 PM PST 24
Finished Jan 24 04:30:05 PM PST 24
Peak memory 201312 kb
Host smart-b1afd003-dead-4f10-8d7d-ee5078710a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961164282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3961164282
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.1421697336
Short name T624
Test name
Test status
Simulation time 30433082 ps
CPU time 0.79 seconds
Started Jan 24 04:43:03 PM PST 24
Finished Jan 24 04:43:05 PM PST 24
Peak memory 201296 kb
Host smart-035c2898-48c2-4cd6-9e92-3c3a4410b4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421697336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.1421697336
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.227155100
Short name T552
Test name
Test status
Simulation time 24567399 ps
CPU time 0.86 seconds
Started Jan 24 04:21:36 PM PST 24
Finished Jan 24 04:21:51 PM PST 24
Peak memory 201256 kb
Host smart-be9dd292-ceea-4beb-bb89-6bffed9d8029
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227155100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.227155100
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.1624694091
Short name T17
Test name
Test status
Simulation time 65908479 ps
CPU time 0.81 seconds
Started Jan 24 04:21:38 PM PST 24
Finished Jan 24 04:21:55 PM PST 24
Peak memory 200104 kb
Host smart-f395dcbf-da9c-4ece-870e-b805413ae703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624694091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1624694091
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.4219336736
Short name T907
Test name
Test status
Simulation time 29539715 ps
CPU time 0.91 seconds
Started Jan 24 04:21:46 PM PST 24
Finished Jan 24 04:22:02 PM PST 24
Peak memory 201324 kb
Host smart-510bf5ca-e910-4cb6-8726-bb7223d1c97c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219336736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.4219336736
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.1472201279
Short name T945
Test name
Test status
Simulation time 18906835 ps
CPU time 0.82 seconds
Started Jan 24 04:21:32 PM PST 24
Finished Jan 24 04:21:48 PM PST 24
Peak memory 201236 kb
Host smart-40ef347a-1ba2-457f-abf4-45f84365ac09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472201279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1472201279
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3438855904
Short name T26
Test name
Test status
Simulation time 318700067 ps
CPU time 2.81 seconds
Started Jan 24 04:21:36 PM PST 24
Finished Jan 24 04:21:52 PM PST 24
Peak memory 201312 kb
Host smart-0b224e2f-ff4d-4074-beab-9f33f6bbb856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438855904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3438855904
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.2899872379
Short name T357
Test name
Test status
Simulation time 1586154110 ps
CPU time 8.59 seconds
Started Jan 24 04:21:33 PM PST 24
Finished Jan 24 04:21:56 PM PST 24
Peak memory 201408 kb
Host smart-e59a949f-eade-4ce7-85f1-f2b5da433692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899872379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.2899872379
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.844807127
Short name T851
Test name
Test status
Simulation time 76796320 ps
CPU time 1.08 seconds
Started Jan 24 04:21:39 PM PST 24
Finished Jan 24 04:21:56 PM PST 24
Peak memory 201332 kb
Host smart-1a0fc3c1-289b-4966-93b4-eb732f6a82e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844807127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_idle_intersig_mubi.844807127
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.3286805949
Short name T579
Test name
Test status
Simulation time 234785735 ps
CPU time 1.41 seconds
Started Jan 24 04:21:40 PM PST 24
Finished Jan 24 04:21:56 PM PST 24
Peak memory 201292 kb
Host smart-23dc43c8-aebb-4e61-8cda-964d87f7083d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286805949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.3286805949
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3312763131
Short name T413
Test name
Test status
Simulation time 34378500 ps
CPU time 0.76 seconds
Started Jan 24 04:45:28 PM PST 24
Finished Jan 24 04:45:29 PM PST 24
Peak memory 201312 kb
Host smart-924e953e-384d-4a5f-951d-aefb40b3e8f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312763131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.3312763131
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.962206138
Short name T282
Test name
Test status
Simulation time 20773573 ps
CPU time 0.78 seconds
Started Jan 24 04:21:30 PM PST 24
Finished Jan 24 04:21:46 PM PST 24
Peak memory 201288 kb
Host smart-6686e217-a783-4ec1-9a3a-435838bdc8e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962206138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.962206138
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1449628742
Short name T452
Test name
Test status
Simulation time 138707987 ps
CPU time 1.19 seconds
Started Jan 24 04:21:48 PM PST 24
Finished Jan 24 04:22:04 PM PST 24
Peak memory 201284 kb
Host smart-c83743e5-92fe-499b-a131-86e400c10d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449628742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1449628742
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.964264447
Short name T656
Test name
Test status
Simulation time 51524300 ps
CPU time 0.92 seconds
Started Jan 24 04:21:34 PM PST 24
Finished Jan 24 04:21:50 PM PST 24
Peak memory 201244 kb
Host smart-d5364f09-4c5c-46fa-9213-e3f983b2078c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964264447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.964264447
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.2272287194
Short name T662
Test name
Test status
Simulation time 2136313589 ps
CPU time 8.23 seconds
Started Jan 24 05:31:36 PM PST 24
Finished Jan 24 05:31:44 PM PST 24
Peak memory 201604 kb
Host smart-b83361ef-3179-4286-9b7d-68c2fa757e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272287194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.2272287194
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.1721139730
Short name T892
Test name
Test status
Simulation time 26663832204 ps
CPU time 185.96 seconds
Started Jan 24 04:21:57 PM PST 24
Finished Jan 24 04:25:15 PM PST 24
Peak memory 210004 kb
Host smart-5306791a-648f-4ae4-9a5f-5a4ce4d8a926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1721139730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.1721139730
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.2385813265
Short name T550
Test name
Test status
Simulation time 32501633 ps
CPU time 0.97 seconds
Started Jan 24 04:21:39 PM PST 24
Finished Jan 24 04:21:55 PM PST 24
Peak memory 201296 kb
Host smart-5ed1b042-f22b-4cc8-ba8c-e7aad293e110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385813265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2385813265
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1380947997
Short name T344
Test name
Test status
Simulation time 15168357 ps
CPU time 0.75 seconds
Started Jan 24 04:12:17 PM PST 24
Finished Jan 24 04:12:25 PM PST 24
Peak memory 201204 kb
Host smart-51565389-f3d7-43e9-8c2a-d89f1e752b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380947997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1380947997
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.3737742541
Short name T779
Test name
Test status
Simulation time 37085746 ps
CPU time 0.9 seconds
Started Jan 24 04:12:07 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201264 kb
Host smart-1e728cb5-eb11-4071-af40-35a5f4a1cf98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737742541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.3737742541
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.2595841930
Short name T454
Test name
Test status
Simulation time 12686346 ps
CPU time 0.7 seconds
Started Jan 24 04:12:11 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201184 kb
Host smart-f4ea3e29-6084-42ef-9fbf-3ce6b618ede6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595841930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.2595841930
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1811488891
Short name T410
Test name
Test status
Simulation time 294640833 ps
CPU time 1.56 seconds
Started Jan 24 04:12:24 PM PST 24
Finished Jan 24 04:12:28 PM PST 24
Peak memory 201288 kb
Host smart-49991ce5-4e4d-4cc3-b2cc-af835f89dd30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811488891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1811488891
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1583620216
Short name T292
Test name
Test status
Simulation time 25066649 ps
CPU time 0.76 seconds
Started Jan 24 04:12:09 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201312 kb
Host smart-1762d01d-6fe8-4ecf-86db-bbf2e7899f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583620216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1583620216
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.3229100498
Short name T482
Test name
Test status
Simulation time 204545291 ps
CPU time 1.99 seconds
Started Jan 24 04:12:10 PM PST 24
Finished Jan 24 04:12:18 PM PST 24
Peak memory 201368 kb
Host smart-e2f939e2-6078-4f93-a26a-2703e310d8b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229100498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3229100498
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.907758315
Short name T913
Test name
Test status
Simulation time 1310457048 ps
CPU time 4.35 seconds
Started Jan 24 04:12:11 PM PST 24
Finished Jan 24 04:12:20 PM PST 24
Peak memory 201436 kb
Host smart-44e833cd-669b-48de-8e93-06c81b8198a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907758315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.907758315
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.4159324262
Short name T842
Test name
Test status
Simulation time 55978296 ps
CPU time 0.86 seconds
Started Jan 24 04:12:10 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201164 kb
Host smart-25da342b-76b0-47f3-ba3d-80967c6400af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159324262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.4159324262
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.4104069541
Short name T629
Test name
Test status
Simulation time 15385342 ps
CPU time 0.73 seconds
Started Jan 24 04:12:08 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201240 kb
Host smart-64e64829-0995-41ab-aabb-2c9b3a9594cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104069541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.4104069541
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2063501998
Short name T791
Test name
Test status
Simulation time 27220472 ps
CPU time 0.88 seconds
Started Jan 24 04:12:10 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201304 kb
Host smart-511bb320-5446-45eb-b247-37d4697ad1bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063501998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2063501998
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.4262065895
Short name T139
Test name
Test status
Simulation time 258550651 ps
CPU time 1.42 seconds
Started Jan 24 04:12:10 PM PST 24
Finished Jan 24 04:12:18 PM PST 24
Peak memory 201172 kb
Host smart-05d5cff5-85d0-4549-83a3-aac39751f753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262065895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.4262065895
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2022696047
Short name T902
Test name
Test status
Simulation time 628041149 ps
CPU time 4 seconds
Started Jan 24 04:12:22 PM PST 24
Finished Jan 24 04:12:30 PM PST 24
Peak memory 201420 kb
Host smart-f178695e-6cbf-496e-9316-2e118b8a2a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022696047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2022696047
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.2783415322
Short name T55
Test name
Test status
Simulation time 396674834 ps
CPU time 3.19 seconds
Started Jan 24 04:12:21 PM PST 24
Finished Jan 24 04:12:29 PM PST 24
Peak memory 217420 kb
Host smart-ec0c6730-06b0-4aac-a2dd-c9f5f017b233
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783415322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.2783415322
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.2886002154
Short name T641
Test name
Test status
Simulation time 44603535 ps
CPU time 1.05 seconds
Started Jan 24 04:12:08 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201252 kb
Host smart-7ff3a97a-dd36-4f25-a8f2-7c348e26588c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886002154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2886002154
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2117108738
Short name T781
Test name
Test status
Simulation time 3205147920 ps
CPU time 22.79 seconds
Started Jan 24 04:12:18 PM PST 24
Finished Jan 24 04:12:48 PM PST 24
Peak memory 201716 kb
Host smart-18333d04-904a-4b3f-a422-4a2662a45cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117108738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2117108738
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.291232075
Short name T27
Test name
Test status
Simulation time 34584288943 ps
CPU time 361.76 seconds
Started Jan 24 04:12:28 PM PST 24
Finished Jan 24 04:18:31 PM PST 24
Peak memory 210120 kb
Host smart-dd777f4c-7495-434e-b02f-106956e198b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=291232075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.291232075
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.697135540
Short name T861
Test name
Test status
Simulation time 28311093 ps
CPU time 0.94 seconds
Started Jan 24 04:12:11 PM PST 24
Finished Jan 24 04:12:17 PM PST 24
Peak memory 201244 kb
Host smart-2bbb79f8-620f-4fb8-893f-9b3d605bfa61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697135540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.697135540
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.2184407430
Short name T580
Test name
Test status
Simulation time 28457350 ps
CPU time 0.76 seconds
Started Jan 24 04:22:04 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 201172 kb
Host smart-d4e55bd5-0a47-4709-87a8-9d4526c2231b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184407430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.2184407430
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.974971919
Short name T352
Test name
Test status
Simulation time 165571863 ps
CPU time 1.13 seconds
Started Jan 24 04:22:02 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 201288 kb
Host smart-9bc9d80d-58a4-47a9-8892-0c323d8e8437
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974971919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.974971919
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1348362706
Short name T464
Test name
Test status
Simulation time 14909306 ps
CPU time 0.71 seconds
Started Jan 24 04:21:57 PM PST 24
Finished Jan 24 04:22:09 PM PST 24
Peak memory 200104 kb
Host smart-f2c3d7dc-24ca-4991-9ebc-1a0d79383b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348362706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1348362706
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.3885488693
Short name T854
Test name
Test status
Simulation time 41163392 ps
CPU time 0.85 seconds
Started Jan 24 04:22:01 PM PST 24
Finished Jan 24 04:22:12 PM PST 24
Peak memory 201288 kb
Host smart-8cc19b70-c0b6-4f73-ab89-a0dcf0b64a39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885488693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.3885488693
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.446653827
Short name T840
Test name
Test status
Simulation time 24442085 ps
CPU time 0.86 seconds
Started Jan 24 04:21:45 PM PST 24
Finished Jan 24 04:22:00 PM PST 24
Peak memory 201260 kb
Host smart-ed3b522c-9816-4739-af48-c4044670d1e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446653827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.446653827
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.560803450
Short name T824
Test name
Test status
Simulation time 2129808214 ps
CPU time 11.5 seconds
Started Jan 24 04:34:04 PM PST 24
Finished Jan 24 04:34:25 PM PST 24
Peak memory 201620 kb
Host smart-2b5f2419-e801-4b55-91f2-aba861ae5711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560803450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.560803450
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.3867812336
Short name T937
Test name
Test status
Simulation time 259867495 ps
CPU time 2.43 seconds
Started Jan 24 04:21:57 PM PST 24
Finished Jan 24 04:22:11 PM PST 24
Peak memory 201400 kb
Host smart-ff5c67f6-97a6-4ebe-b0dd-e827a55f98fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867812336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.3867812336
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.554564099
Short name T743
Test name
Test status
Simulation time 82084663 ps
CPU time 1.06 seconds
Started Jan 24 04:21:56 PM PST 24
Finished Jan 24 04:22:09 PM PST 24
Peak memory 201256 kb
Host smart-e97b7f83-5adb-4bce-9cb2-d67c4a2f4bce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554564099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_idle_intersig_mubi.554564099
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2002686601
Short name T898
Test name
Test status
Simulation time 16100770 ps
CPU time 0.78 seconds
Started Jan 24 04:34:44 PM PST 24
Finished Jan 24 04:34:50 PM PST 24
Peak memory 201284 kb
Host smart-07c56be8-fa6b-4b09-ac69-60ef87d215f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002686601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2002686601
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2064492204
Short name T820
Test name
Test status
Simulation time 17395045 ps
CPU time 0.77 seconds
Started Jan 24 04:21:57 PM PST 24
Finished Jan 24 04:22:10 PM PST 24
Peak memory 201248 kb
Host smart-c4ef3ac6-b494-414a-b6cf-b5d9695f7d8e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064492204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2064492204
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.430768816
Short name T418
Test name
Test status
Simulation time 32204603 ps
CPU time 0.76 seconds
Started Jan 24 04:21:57 PM PST 24
Finished Jan 24 04:22:09 PM PST 24
Peak memory 201232 kb
Host smart-dd477cef-5bea-46e5-a835-17b052f7b2f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430768816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.430768816
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.2642485740
Short name T638
Test name
Test status
Simulation time 1317838959 ps
CPU time 4.94 seconds
Started Jan 24 04:22:08 PM PST 24
Finished Jan 24 04:22:19 PM PST 24
Peak memory 201508 kb
Host smart-c3c7f8a2-e402-4779-8634-13881b07ba78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642485740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2642485740
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.3448558738
Short name T692
Test name
Test status
Simulation time 90449878 ps
CPU time 1.04 seconds
Started Jan 24 04:21:47 PM PST 24
Finished Jan 24 04:22:03 PM PST 24
Peak memory 201304 kb
Host smart-c74eb13a-ab4d-4e41-83b5-8b9fe917b08b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448558738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3448558738
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.3957843634
Short name T621
Test name
Test status
Simulation time 991870851 ps
CPU time 7.52 seconds
Started Jan 24 04:22:09 PM PST 24
Finished Jan 24 04:22:22 PM PST 24
Peak memory 201432 kb
Host smart-b60a63fe-46dc-4e1f-86bd-750c3aec9942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957843634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.3957843634
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.3993256727
Short name T443
Test name
Test status
Simulation time 187790626976 ps
CPU time 937.42 seconds
Started Jan 24 04:32:49 PM PST 24
Finished Jan 24 04:48:27 PM PST 24
Peak memory 210068 kb
Host smart-7f5f2abd-b8a9-47ae-bbbb-0797f9c19497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3993256727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3993256727
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2625248458
Short name T444
Test name
Test status
Simulation time 119498158 ps
CPU time 1.22 seconds
Started Jan 24 04:21:58 PM PST 24
Finished Jan 24 04:22:10 PM PST 24
Peak memory 201248 kb
Host smart-7643ecab-2d6d-4769-adce-fae25799815e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625248458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2625248458
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.704835533
Short name T535
Test name
Test status
Simulation time 18058699 ps
CPU time 0.71 seconds
Started Jan 24 04:22:40 PM PST 24
Finished Jan 24 04:22:45 PM PST 24
Peak memory 201224 kb
Host smart-81f8985c-160b-442e-af12-871435db02f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704835533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm
gr_alert_test.704835533
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.48700179
Short name T728
Test name
Test status
Simulation time 44940764 ps
CPU time 0.85 seconds
Started Jan 24 04:22:39 PM PST 24
Finished Jan 24 04:22:44 PM PST 24
Peak memory 201316 kb
Host smart-d110ff31-5ec0-49e5-a400-2d064671f13b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48700179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_clk_handshake_intersig_mubi.48700179
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3296215325
Short name T58
Test name
Test status
Simulation time 51420827 ps
CPU time 0.8 seconds
Started Jan 24 04:22:31 PM PST 24
Finished Jan 24 04:22:34 PM PST 24
Peak memory 201188 kb
Host smart-9c93b069-c2fc-4d04-8e9a-86e559d485a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296215325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3296215325
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.3038963684
Short name T339
Test name
Test status
Simulation time 62617225 ps
CPU time 0.96 seconds
Started Jan 24 04:22:37 PM PST 24
Finished Jan 24 04:22:42 PM PST 24
Peak memory 201320 kb
Host smart-e9557bc9-3ace-473d-ae1f-4d298726cd63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038963684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.3038963684
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.140415281
Short name T847
Test name
Test status
Simulation time 48405070 ps
CPU time 0.85 seconds
Started Jan 24 04:22:02 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 201324 kb
Host smart-21939505-9e45-4fc4-adc0-02c6f3c4b46e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140415281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.140415281
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1983444642
Short name T439
Test name
Test status
Simulation time 922210383 ps
CPU time 7.18 seconds
Started Jan 24 04:22:03 PM PST 24
Finished Jan 24 04:22:20 PM PST 24
Peak memory 201268 kb
Host smart-55574e16-bf91-4046-a48d-b145980c4fc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983444642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1983444642
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.2072923247
Short name T554
Test name
Test status
Simulation time 1467332300 ps
CPU time 7.56 seconds
Started Jan 24 04:22:14 PM PST 24
Finished Jan 24 04:22:24 PM PST 24
Peak memory 201436 kb
Host smart-2e89446d-7882-4f31-bada-49508e1d2c84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072923247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.2072923247
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1516622074
Short name T933
Test name
Test status
Simulation time 27885582 ps
CPU time 0.87 seconds
Started Jan 24 04:22:26 PM PST 24
Finished Jan 24 04:22:28 PM PST 24
Peak memory 201308 kb
Host smart-83c9502f-cc9f-4957-ad75-55f2108f6505
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516622074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1516622074
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2529757724
Short name T659
Test name
Test status
Simulation time 50615505 ps
CPU time 0.82 seconds
Started Jan 24 04:22:40 PM PST 24
Finished Jan 24 04:22:45 PM PST 24
Peak memory 201288 kb
Host smart-4b73d4d7-9632-4efb-856e-9b9d62834ce9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529757724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2529757724
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1801688405
Short name T700
Test name
Test status
Simulation time 17884229 ps
CPU time 0.79 seconds
Started Jan 24 04:22:25 PM PST 24
Finished Jan 24 04:22:27 PM PST 24
Peak memory 201300 kb
Host smart-2c51bd88-02a0-4e29-8e14-d8aa0422ad2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801688405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.1801688405
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3836671826
Short name T810
Test name
Test status
Simulation time 14121373 ps
CPU time 0.76 seconds
Started Jan 24 04:22:17 PM PST 24
Finished Jan 24 04:22:21 PM PST 24
Peak memory 201112 kb
Host smart-e1e8e1b1-ed47-4402-8438-7afc5f8ae625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836671826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3836671826
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1029018833
Short name T831
Test name
Test status
Simulation time 1059679310 ps
CPU time 6.1 seconds
Started Jan 24 04:22:38 PM PST 24
Finished Jan 24 04:22:48 PM PST 24
Peak memory 201464 kb
Host smart-69cb5411-9c2f-42e9-a6c0-2a21feeaef2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029018833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1029018833
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.343295408
Short name T106
Test name
Test status
Simulation time 36747089 ps
CPU time 0.85 seconds
Started Jan 24 04:22:02 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 201244 kb
Host smart-8b435550-945f-4e4d-b32a-0fc407c44987
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343295408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.343295408
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.4056367871
Short name T402
Test name
Test status
Simulation time 2299077477 ps
CPU time 17.3 seconds
Started Jan 24 04:22:47 PM PST 24
Finished Jan 24 04:23:10 PM PST 24
Peak memory 201744 kb
Host smart-07e987a3-055b-4721-8a92-e0a83e9fc6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056367871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.4056367871
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.331961345
Short name T149
Test name
Test status
Simulation time 152040497257 ps
CPU time 853.96 seconds
Started Jan 24 04:22:49 PM PST 24
Finished Jan 24 04:37:09 PM PST 24
Peak memory 210076 kb
Host smart-9ada6d99-654d-4054-8236-e91e0ec14614
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=331961345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.331961345
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.2115337028
Short name T390
Test name
Test status
Simulation time 71804716 ps
CPU time 0.95 seconds
Started Jan 24 04:22:10 PM PST 24
Finished Jan 24 04:22:16 PM PST 24
Peak memory 201312 kb
Host smart-3d4a87f1-8bf7-41cf-9b67-448141ce29c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115337028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2115337028
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.3731846063
Short name T833
Test name
Test status
Simulation time 23252744 ps
CPU time 0.85 seconds
Started Jan 24 04:22:47 PM PST 24
Finished Jan 24 04:22:54 PM PST 24
Peak memory 201296 kb
Host smart-0c844919-0e87-470b-9340-0bb7d2f5b915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731846063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.3731846063
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2980246548
Short name T340
Test name
Test status
Simulation time 92161180 ps
CPU time 1.07 seconds
Started Jan 24 04:22:42 PM PST 24
Finished Jan 24 04:22:48 PM PST 24
Peak memory 201260 kb
Host smart-b8adbe16-a374-417a-881a-0109f8b596c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980246548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2980246548
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2447756034
Short name T707
Test name
Test status
Simulation time 15603209 ps
CPU time 0.69 seconds
Started Jan 24 04:22:52 PM PST 24
Finished Jan 24 04:22:57 PM PST 24
Peak memory 201224 kb
Host smart-a9336cda-fc93-4284-88c0-ebea12264062
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447756034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2447756034
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.4123174199
Short name T423
Test name
Test status
Simulation time 31590896 ps
CPU time 0.8 seconds
Started Jan 24 04:22:52 PM PST 24
Finished Jan 24 04:22:57 PM PST 24
Peak memory 201320 kb
Host smart-b61a23ad-752b-4ac1-aaf1-29b89cbd3826
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123174199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.4123174199
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.3048417416
Short name T322
Test name
Test status
Simulation time 60936311 ps
CPU time 1.05 seconds
Started Jan 24 04:22:35 PM PST 24
Finished Jan 24 04:22:39 PM PST 24
Peak memory 201324 kb
Host smart-a23940c9-f03a-4ae2-ad23-7ac4fbef16e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048417416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3048417416
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.1260230530
Short name T4
Test name
Test status
Simulation time 197040072 ps
CPU time 1.89 seconds
Started Jan 24 04:22:35 PM PST 24
Finished Jan 24 04:22:41 PM PST 24
Peak memory 201328 kb
Host smart-65f0cedd-2461-483d-aa64-3130542392a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260230530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1260230530
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.1026677565
Short name T562
Test name
Test status
Simulation time 1226063225 ps
CPU time 6.47 seconds
Started Jan 24 04:22:47 PM PST 24
Finished Jan 24 04:23:00 PM PST 24
Peak memory 201452 kb
Host smart-d9438bb1-8758-4cfa-913c-6721418fc137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026677565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.1026677565
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3541039956
Short name T519
Test name
Test status
Simulation time 69135912 ps
CPU time 1.14 seconds
Started Jan 24 04:22:43 PM PST 24
Finished Jan 24 04:22:48 PM PST 24
Peak memory 201304 kb
Host smart-ee665661-30b2-450c-9112-31c1261fa456
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541039956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3541039956
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3281453070
Short name T306
Test name
Test status
Simulation time 16153697 ps
CPU time 0.76 seconds
Started Jan 24 04:22:43 PM PST 24
Finished Jan 24 04:22:49 PM PST 24
Peak memory 201288 kb
Host smart-69971201-3eb8-4f86-9275-ea25bad88dec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281453070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3281453070
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2676825229
Short name T480
Test name
Test status
Simulation time 75663959 ps
CPU time 1.01 seconds
Started Jan 24 04:22:46 PM PST 24
Finished Jan 24 04:22:52 PM PST 24
Peak memory 201304 kb
Host smart-3b219de9-2e34-4b1f-88b2-537d311dffac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676825229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.2676825229
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.3385274187
Short name T547
Test name
Test status
Simulation time 28801253 ps
CPU time 0.77 seconds
Started Jan 24 04:22:38 PM PST 24
Finished Jan 24 04:22:43 PM PST 24
Peak memory 201260 kb
Host smart-d6053c67-d159-4ad2-add0-d7c070e38f83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385274187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3385274187
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.1980223162
Short name T291
Test name
Test status
Simulation time 194943815 ps
CPU time 1.27 seconds
Started Jan 24 04:22:46 PM PST 24
Finished Jan 24 04:22:52 PM PST 24
Peak memory 201252 kb
Host smart-7a5fb0c1-fabc-40bb-9d81-5a4e2dcddc9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980223162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1980223162
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.1139974101
Short name T739
Test name
Test status
Simulation time 19757185 ps
CPU time 0.82 seconds
Started Jan 24 04:22:39 PM PST 24
Finished Jan 24 04:22:44 PM PST 24
Peak memory 201312 kb
Host smart-49ea2667-1d94-4d39-be7e-74026aaeac87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139974101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1139974101
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1592627561
Short name T716
Test name
Test status
Simulation time 6057353266 ps
CPU time 39.79 seconds
Started Jan 24 04:22:46 PM PST 24
Finished Jan 24 04:23:30 PM PST 24
Peak memory 201680 kb
Host smart-7456866a-30ec-4305-b097-80959d710a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592627561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1592627561
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.658299720
Short name T436
Test name
Test status
Simulation time 22393388594 ps
CPU time 415.96 seconds
Started Jan 24 04:22:46 PM PST 24
Finished Jan 24 04:29:47 PM PST 24
Peak memory 217872 kb
Host smart-9e1fba80-fd2c-41b2-b189-06b31a18e0eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=658299720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.658299720
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.3459597573
Short name T540
Test name
Test status
Simulation time 12484280 ps
CPU time 0.7 seconds
Started Jan 24 04:22:44 PM PST 24
Finished Jan 24 04:22:49 PM PST 24
Peak memory 201292 kb
Host smart-921b45e7-6726-48cf-b695-38a76a16f0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459597573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3459597573
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3543694115
Short name T920
Test name
Test status
Simulation time 72051370 ps
CPU time 1.06 seconds
Started Jan 24 04:23:11 PM PST 24
Finished Jan 24 04:23:21 PM PST 24
Peak memory 201264 kb
Host smart-7c0f9bcb-d54f-41a5-af0d-8b676402946d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543694115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3543694115
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3143350248
Short name T588
Test name
Test status
Simulation time 22773834 ps
CPU time 0.82 seconds
Started Jan 24 04:23:04 PM PST 24
Finished Jan 24 04:23:15 PM PST 24
Peak memory 201304 kb
Host smart-3cdc8256-9d33-4ac9-932e-f61cb47c5b6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143350248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.3143350248
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1348007955
Short name T792
Test name
Test status
Simulation time 17721541 ps
CPU time 0.72 seconds
Started Jan 24 04:22:57 PM PST 24
Finished Jan 24 04:23:01 PM PST 24
Peak memory 200108 kb
Host smart-9ee36f75-f4b8-40dd-9d48-ee7905db1dde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348007955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1348007955
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3909473403
Short name T807
Test name
Test status
Simulation time 23982530 ps
CPU time 0.88 seconds
Started Jan 24 04:23:06 PM PST 24
Finished Jan 24 04:23:15 PM PST 24
Peak memory 201316 kb
Host smart-b2b2e138-f9c6-4015-a4a7-33fd25709656
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909473403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.3909473403
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.2955362829
Short name T876
Test name
Test status
Simulation time 130611465 ps
CPU time 1.12 seconds
Started Jan 24 04:22:58 PM PST 24
Finished Jan 24 04:23:07 PM PST 24
Peak memory 201324 kb
Host smart-10449bab-b10d-4986-9406-0852e9090d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955362829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2955362829
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.958883420
Short name T421
Test name
Test status
Simulation time 1997531087 ps
CPU time 14.69 seconds
Started Jan 24 04:23:00 PM PST 24
Finished Jan 24 04:23:24 PM PST 24
Peak memory 201544 kb
Host smart-653300da-32e7-48bf-9336-707ce3ac612a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958883420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.958883420
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.552246650
Short name T431
Test name
Test status
Simulation time 501553503 ps
CPU time 4.03 seconds
Started Jan 24 04:23:00 PM PST 24
Finished Jan 24 04:23:14 PM PST 24
Peak memory 201404 kb
Host smart-6d23d856-cef3-4aa9-b656-2d002e46a307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552246650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti
meout.552246650
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1320942265
Short name T374
Test name
Test status
Simulation time 24714198 ps
CPU time 0.87 seconds
Started Jan 24 04:22:59 PM PST 24
Finished Jan 24 04:23:09 PM PST 24
Peak memory 201300 kb
Host smart-eed028ce-f966-4486-8b9a-dbcc1239fe59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320942265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1320942265
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3016431769
Short name T916
Test name
Test status
Simulation time 43162125 ps
CPU time 0.9 seconds
Started Jan 24 04:23:09 PM PST 24
Finished Jan 24 04:23:19 PM PST 24
Peak memory 201336 kb
Host smart-eaee5da0-d9c6-4b46-8467-565796ac5eab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016431769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3016431769
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.218407000
Short name T836
Test name
Test status
Simulation time 64867017 ps
CPU time 0.94 seconds
Started Jan 24 04:23:09 PM PST 24
Finished Jan 24 04:23:19 PM PST 24
Peak memory 201336 kb
Host smart-cbcff412-0cfa-478a-93dc-5f1969e5dc7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218407000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.218407000
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2679053795
Short name T903
Test name
Test status
Simulation time 39907823 ps
CPU time 0.78 seconds
Started Jan 24 04:22:57 PM PST 24
Finished Jan 24 04:23:01 PM PST 24
Peak memory 201128 kb
Host smart-2d428b63-4d9f-4a91-b1df-c871b78bdbfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679053795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2679053795
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.3453631825
Short name T694
Test name
Test status
Simulation time 1196047191 ps
CPU time 6.58 seconds
Started Jan 24 04:23:07 PM PST 24
Finished Jan 24 04:23:22 PM PST 24
Peak memory 201440 kb
Host smart-4aa3c848-deb7-44ee-b359-e48f11772969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453631825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3453631825
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.1690650322
Short name T904
Test name
Test status
Simulation time 19337641 ps
CPU time 0.89 seconds
Started Jan 24 04:22:52 PM PST 24
Finished Jan 24 04:22:57 PM PST 24
Peak memory 201324 kb
Host smart-508d10e9-7970-49ec-9ca0-9e6274d21541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690650322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.1690650322
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.2516372298
Short name T859
Test name
Test status
Simulation time 2616055239 ps
CPU time 14.5 seconds
Started Jan 24 04:23:03 PM PST 24
Finished Jan 24 04:23:28 PM PST 24
Peak memory 201716 kb
Host smart-81c5d9c0-3866-4fcb-9506-30e3e3d2e37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516372298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.2516372298
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.2007260206
Short name T140
Test name
Test status
Simulation time 31488343676 ps
CPU time 470.77 seconds
Started Jan 24 04:23:15 PM PST 24
Finished Jan 24 04:31:14 PM PST 24
Peak memory 218208 kb
Host smart-099ff958-0704-4e8a-a8de-8a05e1a7e402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2007260206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2007260206
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.698083570
Short name T928
Test name
Test status
Simulation time 59085463 ps
CPU time 0.91 seconds
Started Jan 24 04:22:57 PM PST 24
Finished Jan 24 04:23:05 PM PST 24
Peak memory 201180 kb
Host smart-f2470a6e-e2c1-49ec-9b45-9b4347d316a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698083570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.698083570
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.690610314
Short name T745
Test name
Test status
Simulation time 43936033 ps
CPU time 0.81 seconds
Started Jan 24 04:23:29 PM PST 24
Finished Jan 24 04:23:31 PM PST 24
Peak memory 201260 kb
Host smart-c10219d7-08ca-4e15-ae83-a791b0305870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690610314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.690610314
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3746615836
Short name T305
Test name
Test status
Simulation time 94875329 ps
CPU time 1.09 seconds
Started Jan 24 04:23:11 PM PST 24
Finished Jan 24 04:23:21 PM PST 24
Peak memory 201344 kb
Host smart-fe11df9e-ee40-4058-8f11-d9ff8712c916
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746615836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.3746615836
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2526967292
Short name T606
Test name
Test status
Simulation time 47875949 ps
CPU time 0.77 seconds
Started Jan 24 04:23:06 PM PST 24
Finished Jan 24 04:23:15 PM PST 24
Peak memory 200112 kb
Host smart-9d143229-28f8-47d2-b665-6b546b22a705
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526967292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2526967292
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.148346447
Short name T471
Test name
Test status
Simulation time 47475596 ps
CPU time 0.81 seconds
Started Jan 24 04:23:14 PM PST 24
Finished Jan 24 04:23:23 PM PST 24
Peak memory 201320 kb
Host smart-9a900637-ebe4-4773-bc2a-3376c3498ded
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148346447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_div_intersig_mubi.148346447
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.1924323954
Short name T162
Test name
Test status
Simulation time 87743387 ps
CPU time 1.07 seconds
Started Jan 24 04:23:06 PM PST 24
Finished Jan 24 04:23:15 PM PST 24
Peak memory 201196 kb
Host smart-7d3ab6f7-d4e5-4bfc-ac30-97bd2cb0c965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924323954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1924323954
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1388207406
Short name T784
Test name
Test status
Simulation time 568868344 ps
CPU time 3.54 seconds
Started Jan 24 04:23:11 PM PST 24
Finished Jan 24 04:23:24 PM PST 24
Peak memory 201352 kb
Host smart-3e2b03c6-04a7-4421-aaa2-e2c3805acfd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388207406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1388207406
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.1642302855
Short name T866
Test name
Test status
Simulation time 1099728397 ps
CPU time 5.73 seconds
Started Jan 24 04:23:08 PM PST 24
Finished Jan 24 04:23:23 PM PST 24
Peak memory 201420 kb
Host smart-da9ad1e6-5543-4d68-a68e-eef942ea3369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642302855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.1642302855
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.597903144
Short name T804
Test name
Test status
Simulation time 21272505 ps
CPU time 0.86 seconds
Started Jan 24 04:23:07 PM PST 24
Finished Jan 24 04:23:16 PM PST 24
Peak memory 201196 kb
Host smart-f07d1a65-a831-41bb-a630-f9e9f553023d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597903144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.597903144
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1803045748
Short name T598
Test name
Test status
Simulation time 27285466 ps
CPU time 0.8 seconds
Started Jan 24 04:23:10 PM PST 24
Finished Jan 24 04:23:20 PM PST 24
Peak memory 201332 kb
Host smart-50c8ba00-6615-4893-98dc-2c8037a8d0a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803045748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1803045748
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.841179421
Short name T812
Test name
Test status
Simulation time 36867016 ps
CPU time 0.82 seconds
Started Jan 24 04:23:08 PM PST 24
Finished Jan 24 04:23:17 PM PST 24
Peak memory 201304 kb
Host smart-a3bf14b6-48e5-4936-b556-328645c7c573
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841179421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.841179421
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.1740766540
Short name T401
Test name
Test status
Simulation time 21609868 ps
CPU time 0.76 seconds
Started Jan 24 04:23:11 PM PST 24
Finished Jan 24 04:23:21 PM PST 24
Peak memory 201176 kb
Host smart-c83c6faf-f26b-48b9-9b51-7c5a6897dd49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740766540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1740766540
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.1859809320
Short name T375
Test name
Test status
Simulation time 527612458 ps
CPU time 2.23 seconds
Started Jan 24 05:07:51 PM PST 24
Finished Jan 24 05:07:55 PM PST 24
Peak memory 201268 kb
Host smart-209c5dbd-7ec0-46d4-a8f4-a6c97a879def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859809320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1859809320
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.3472452902
Short name T615
Test name
Test status
Simulation time 21071603 ps
CPU time 0.83 seconds
Started Jan 24 04:23:06 PM PST 24
Finished Jan 24 04:23:15 PM PST 24
Peak memory 201248 kb
Host smart-5de4cee9-7101-4a52-99b7-940387eee57a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472452902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3472452902
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3202411338
Short name T895
Test name
Test status
Simulation time 2431232475 ps
CPU time 13.08 seconds
Started Jan 24 04:23:15 PM PST 24
Finished Jan 24 04:23:36 PM PST 24
Peak memory 201728 kb
Host smart-9e09ce14-c82a-4663-9cb4-23626d9c2b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202411338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3202411338
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.1939806846
Short name T406
Test name
Test status
Simulation time 361751549753 ps
CPU time 1260.4 seconds
Started Jan 24 04:41:42 PM PST 24
Finished Jan 24 05:02:44 PM PST 24
Peak memory 210052 kb
Host smart-559423d8-2538-4101-8795-ba7b764b2dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1939806846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1939806846
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.1756689669
Short name T296
Test name
Test status
Simulation time 32777549 ps
CPU time 1.02 seconds
Started Jan 24 04:23:04 PM PST 24
Finished Jan 24 04:23:14 PM PST 24
Peak memory 201280 kb
Host smart-945805e1-90b1-4017-898c-d8630d621dcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756689669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1756689669
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.60926606
Short name T613
Test name
Test status
Simulation time 23582782 ps
CPU time 0.82 seconds
Started Jan 24 05:16:24 PM PST 24
Finished Jan 24 05:16:26 PM PST 24
Peak memory 201248 kb
Host smart-99e7c39f-c3b5-48ff-8bcc-535d6e66984d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60926606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmg
r_alert_test.60926606
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2935352023
Short name T602
Test name
Test status
Simulation time 21481512 ps
CPU time 0.82 seconds
Started Jan 24 04:23:43 PM PST 24
Finished Jan 24 04:23:46 PM PST 24
Peak memory 201296 kb
Host smart-67900f78-1014-4887-bff8-ea2a70d8be16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935352023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.2935352023
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1203767916
Short name T786
Test name
Test status
Simulation time 15286936 ps
CPU time 0.7 seconds
Started Jan 24 04:23:39 PM PST 24
Finished Jan 24 04:23:41 PM PST 24
Peak memory 200060 kb
Host smart-e90b4178-f6f7-4050-8fac-eff6ac25d773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203767916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1203767916
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.80531192
Short name T302
Test name
Test status
Simulation time 85027971 ps
CPU time 1.01 seconds
Started Jan 24 04:23:28 PM PST 24
Finished Jan 24 04:23:30 PM PST 24
Peak memory 201276 kb
Host smart-b78f5128-bb3c-4519-9ba9-931732eeff30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80531192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.80531192
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3630435988
Short name T819
Test name
Test status
Simulation time 1275107347 ps
CPU time 9.67 seconds
Started Jan 24 04:23:44 PM PST 24
Finished Jan 24 04:23:55 PM PST 24
Peak memory 201368 kb
Host smart-bf4088d0-e214-4d3b-84fb-9abdd398fe2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630435988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3630435988
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.2533186366
Short name T426
Test name
Test status
Simulation time 156355154 ps
CPU time 1.21 seconds
Started Jan 24 04:23:39 PM PST 24
Finished Jan 24 04:23:42 PM PST 24
Peak memory 201424 kb
Host smart-0c8ffc50-4104-4b3b-b031-e76e9b91d995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533186366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.2533186366
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.3850217756
Short name T435
Test name
Test status
Simulation time 18958530 ps
CPU time 0.8 seconds
Started Jan 24 04:23:44 PM PST 24
Finished Jan 24 04:23:47 PM PST 24
Peak memory 201300 kb
Host smart-bcdb1741-4f1c-4451-a95e-ab48688a4e1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850217756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.3850217756
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1105612787
Short name T399
Test name
Test status
Simulation time 62306347 ps
CPU time 0.91 seconds
Started Jan 24 04:23:43 PM PST 24
Finished Jan 24 04:23:46 PM PST 24
Peak memory 201300 kb
Host smart-b2537149-9766-4606-a4a0-7c88806bb05d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105612787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1105612787
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2853815711
Short name T648
Test name
Test status
Simulation time 52664637 ps
CPU time 0.92 seconds
Started Jan 24 04:23:40 PM PST 24
Finished Jan 24 04:23:43 PM PST 24
Peak memory 201284 kb
Host smart-a57c04d8-e14d-4fed-9840-f0e4eef0deba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853815711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.2853815711
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2782136017
Short name T581
Test name
Test status
Simulation time 42008903 ps
CPU time 0.81 seconds
Started Jan 24 04:23:40 PM PST 24
Finished Jan 24 04:23:43 PM PST 24
Peak memory 201220 kb
Host smart-b361b4a7-360d-46aa-8060-7cfd9a0a654d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782136017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2782136017
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2873388071
Short name T757
Test name
Test status
Simulation time 77010518 ps
CPU time 0.97 seconds
Started Jan 24 04:23:43 PM PST 24
Finished Jan 24 04:23:46 PM PST 24
Peak memory 201308 kb
Host smart-b573660c-07cb-4c25-926d-2aa401a3ff67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873388071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2873388071
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1392531113
Short name T891
Test name
Test status
Simulation time 75428195 ps
CPU time 1.01 seconds
Started Jan 24 04:23:29 PM PST 24
Finished Jan 24 04:23:32 PM PST 24
Peak memory 201260 kb
Host smart-518df3de-184e-462e-8374-59074e3c211d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392531113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1392531113
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_trans.2609571737
Short name T817
Test name
Test status
Simulation time 28086985 ps
CPU time 0.94 seconds
Started Jan 24 04:23:39 PM PST 24
Finished Jan 24 04:23:42 PM PST 24
Peak memory 201284 kb
Host smart-3ca3fbd6-f981-4010-a119-a48a8441e5c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609571737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2609571737
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.954707196
Short name T389
Test name
Test status
Simulation time 19549964 ps
CPU time 0.79 seconds
Started Jan 24 04:24:09 PM PST 24
Finished Jan 24 04:24:12 PM PST 24
Peak memory 201252 kb
Host smart-b322def0-1d1a-4fa6-af4e-89870045ac09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954707196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.954707196
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.617828229
Short name T432
Test name
Test status
Simulation time 118544095 ps
CPU time 1.09 seconds
Started Jan 24 04:24:11 PM PST 24
Finished Jan 24 04:24:14 PM PST 24
Peak memory 201304 kb
Host smart-6468a155-b716-4224-a61b-16bd7c226c2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617828229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.617828229
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1954275194
Short name T651
Test name
Test status
Simulation time 42994663 ps
CPU time 0.77 seconds
Started Jan 24 04:23:51 PM PST 24
Finished Jan 24 04:23:53 PM PST 24
Peak memory 201196 kb
Host smart-0ba0ae92-4f03-4e14-bb4e-e52ee7056e99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954275194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1954275194
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.488823512
Short name T304
Test name
Test status
Simulation time 47772615 ps
CPU time 0.92 seconds
Started Jan 24 04:24:06 PM PST 24
Finished Jan 24 04:24:09 PM PST 24
Peak memory 201280 kb
Host smart-de191aae-2b30-4a29-ac40-a5e0b3dd22e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488823512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.488823512
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.1541958110
Short name T295
Test name
Test status
Simulation time 74995804 ps
CPU time 1.02 seconds
Started Jan 24 04:23:49 PM PST 24
Finished Jan 24 04:23:52 PM PST 24
Peak memory 201320 kb
Host smart-80744f2e-3d34-4a76-8edd-e02248ed7310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541958110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1541958110
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.131105227
Short name T349
Test name
Test status
Simulation time 1838099060 ps
CPU time 6.6 seconds
Started Jan 24 04:23:48 PM PST 24
Finished Jan 24 04:23:57 PM PST 24
Peak memory 201356 kb
Host smart-0c05cab4-66eb-4442-a6b5-4fe744cc2e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131105227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.131105227
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.659431202
Short name T632
Test name
Test status
Simulation time 378221412 ps
CPU time 3.18 seconds
Started Jan 24 04:41:58 PM PST 24
Finished Jan 24 04:42:07 PM PST 24
Peak memory 201432 kb
Host smart-edc40279-baf3-436e-beac-01e25cd2cdff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659431202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_ti
meout.659431202
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.295973517
Short name T438
Test name
Test status
Simulation time 58479223 ps
CPU time 0.91 seconds
Started Jan 24 04:23:53 PM PST 24
Finished Jan 24 04:23:56 PM PST 24
Peak memory 201304 kb
Host smart-4ae7d7d6-ccf1-478f-9eec-3a18b4f436a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295973517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_idle_intersig_mubi.295973517
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.2236616725
Short name T775
Test name
Test status
Simulation time 14855528 ps
CPU time 0.74 seconds
Started Jan 24 04:23:52 PM PST 24
Finished Jan 24 04:23:54 PM PST 24
Peak memory 201324 kb
Host smart-487fb92f-3e64-4e9b-92ee-33831a9b5eda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236616725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.2236616725
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3464083153
Short name T944
Test name
Test status
Simulation time 28947009 ps
CPU time 0.8 seconds
Started Jan 24 04:23:52 PM PST 24
Finished Jan 24 04:23:54 PM PST 24
Peak memory 201268 kb
Host smart-d37f9129-4f63-472b-9379-fef911ccccf1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464083153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3464083153
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.76656568
Short name T634
Test name
Test status
Simulation time 34920010 ps
CPU time 0.77 seconds
Started Jan 24 05:27:48 PM PST 24
Finished Jan 24 05:27:53 PM PST 24
Peak memory 201184 kb
Host smart-6fe6ef67-a1c9-4798-a2de-2c453e6994b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76656568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.76656568
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.1308971790
Short name T620
Test name
Test status
Simulation time 459161059 ps
CPU time 1.89 seconds
Started Jan 24 04:24:06 PM PST 24
Finished Jan 24 04:24:10 PM PST 24
Peak memory 201256 kb
Host smart-f32ac4de-e244-4ec3-8c58-ed83978d4f9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308971790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1308971790
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.3130002409
Short name T957
Test name
Test status
Simulation time 1955067730 ps
CPU time 10.42 seconds
Started Jan 24 04:24:12 PM PST 24
Finished Jan 24 04:24:24 PM PST 24
Peak memory 201632 kb
Host smart-b050653e-6526-40d8-be92-4fc6b9814e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130002409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.3130002409
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2913916942
Short name T529
Test name
Test status
Simulation time 21600422806 ps
CPU time 331.26 seconds
Started Jan 24 04:24:10 PM PST 24
Finished Jan 24 04:29:43 PM PST 24
Peak memory 218212 kb
Host smart-f793d498-b7a3-4b92-9eca-d7c62f9110cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2913916942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2913916942
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.1792784258
Short name T360
Test name
Test status
Simulation time 41059681 ps
CPU time 1.08 seconds
Started Jan 24 04:23:49 PM PST 24
Finished Jan 24 04:23:52 PM PST 24
Peak memory 201316 kb
Host smart-eb81acc7-a73d-43af-b201-61d1b4cf4d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792784258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1792784258
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.712550292
Short name T609
Test name
Test status
Simulation time 19494682 ps
CPU time 0.7 seconds
Started Jan 24 04:24:14 PM PST 24
Finished Jan 24 04:24:18 PM PST 24
Peak memory 201252 kb
Host smart-35fb0681-a0b9-4a09-ab76-1b99cbce2762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712550292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkm
gr_alert_test.712550292
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3405641182
Short name T311
Test name
Test status
Simulation time 38498894 ps
CPU time 0.8 seconds
Started Jan 24 04:24:11 PM PST 24
Finished Jan 24 04:24:13 PM PST 24
Peak memory 201244 kb
Host smart-8f87bcea-30bc-41a2-9a8f-cdec20351df0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405641182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3405641182
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1345434025
Short name T520
Test name
Test status
Simulation time 39212003 ps
CPU time 0.79 seconds
Started Jan 24 04:24:16 PM PST 24
Finished Jan 24 04:24:19 PM PST 24
Peak memory 200104 kb
Host smart-99878673-9207-4070-851f-f8ee2a7675b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345434025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1345434025
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.385041640
Short name T720
Test name
Test status
Simulation time 22521439 ps
CPU time 0.81 seconds
Started Jan 24 04:24:13 PM PST 24
Finished Jan 24 04:24:16 PM PST 24
Peak memory 201248 kb
Host smart-0a7f082a-679a-43a3-be91-ee16ed12ac10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385041640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.385041640
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3991943566
Short name T690
Test name
Test status
Simulation time 17641584 ps
CPU time 0.77 seconds
Started Jan 24 04:24:10 PM PST 24
Finished Jan 24 04:24:13 PM PST 24
Peak memory 201324 kb
Host smart-1f0e8626-44cf-43d5-8811-1c81e20aac9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991943566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3991943566
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.2080374962
Short name T484
Test name
Test status
Simulation time 1657712932 ps
CPU time 7.42 seconds
Started Jan 24 04:24:03 PM PST 24
Finished Jan 24 04:24:13 PM PST 24
Peak memory 201368 kb
Host smart-ed3a1564-af9e-459f-917b-45b31aff7571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080374962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2080374962
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.3455179021
Short name T391
Test name
Test status
Simulation time 1583931311 ps
CPU time 8.38 seconds
Started Jan 24 04:24:04 PM PST 24
Finished Jan 24 04:24:14 PM PST 24
Peak memory 201388 kb
Host smart-0dae63da-a82c-4ba2-82cd-63beb606cb27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455179021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.3455179021
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1046372077
Short name T60
Test name
Test status
Simulation time 50751269 ps
CPU time 1.06 seconds
Started Jan 24 04:48:42 PM PST 24
Finished Jan 24 04:48:46 PM PST 24
Peak memory 201332 kb
Host smart-5bf16245-6d92-4261-908b-2765afdf3b87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046372077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1046372077
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3946365963
Short name T395
Test name
Test status
Simulation time 64290755 ps
CPU time 0.85 seconds
Started Jan 24 04:24:14 PM PST 24
Finished Jan 24 04:24:19 PM PST 24
Peak memory 201288 kb
Host smart-9df7f9f4-8c47-47f1-845e-8792f9dd8112
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946365963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3946365963
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3856222418
Short name T343
Test name
Test status
Simulation time 18772266 ps
CPU time 0.8 seconds
Started Jan 24 04:24:17 PM PST 24
Finished Jan 24 04:24:22 PM PST 24
Peak memory 201292 kb
Host smart-74b83295-55b2-4661-8df6-b730bd37e202
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856222418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.3856222418
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2514957660
Short name T605
Test name
Test status
Simulation time 32002202 ps
CPU time 0.77 seconds
Started Jan 24 04:24:04 PM PST 24
Finished Jan 24 04:24:07 PM PST 24
Peak memory 201236 kb
Host smart-038bf66b-c7b2-4d66-a0d8-c8f116f05777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514957660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2514957660
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.1480308805
Short name T862
Test name
Test status
Simulation time 394640481 ps
CPU time 2.53 seconds
Started Jan 24 04:24:13 PM PST 24
Finished Jan 24 04:24:18 PM PST 24
Peak memory 201252 kb
Host smart-d6972923-31ee-47e7-a93a-e225e3059f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480308805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1480308805
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.104139695
Short name T796
Test name
Test status
Simulation time 21675386 ps
CPU time 0.91 seconds
Started Jan 24 04:24:13 PM PST 24
Finished Jan 24 04:24:17 PM PST 24
Peak memory 201324 kb
Host smart-9042bbed-ebff-4886-8ffb-c8a722dadae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104139695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.104139695
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2287550200
Short name T323
Test name
Test status
Simulation time 3239371447 ps
CPU time 11 seconds
Started Jan 24 04:24:19 PM PST 24
Finished Jan 24 04:24:35 PM PST 24
Peak memory 201724 kb
Host smart-9df26e3d-53ed-409d-9e8f-275b561c2329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287550200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2287550200
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3869370080
Short name T153
Test name
Test status
Simulation time 49205364459 ps
CPU time 530.94 seconds
Started Jan 24 04:24:19 PM PST 24
Finished Jan 24 04:33:16 PM PST 24
Peak memory 211036 kb
Host smart-fa013c1c-a1a4-4737-8adc-dc34362ce90a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3869370080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.3869370080
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.3741852564
Short name T277
Test name
Test status
Simulation time 18139655 ps
CPU time 0.77 seconds
Started Jan 24 04:24:09 PM PST 24
Finished Jan 24 04:24:11 PM PST 24
Peak memory 201208 kb
Host smart-1bef0614-5048-48ea-913a-b74cdb4f591a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741852564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3741852564
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.431320905
Short name T849
Test name
Test status
Simulation time 15124010 ps
CPU time 0.75 seconds
Started Jan 24 04:24:35 PM PST 24
Finished Jan 24 04:24:37 PM PST 24
Peak memory 201240 kb
Host smart-5040ceeb-8666-460f-ba63-61a0c7f65199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431320905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.431320905
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.855549403
Short name T764
Test name
Test status
Simulation time 83392755 ps
CPU time 1.09 seconds
Started Jan 24 04:24:34 PM PST 24
Finished Jan 24 04:24:36 PM PST 24
Peak memory 201280 kb
Host smart-dbb49a07-c617-462a-9566-9cb8c50f7317
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855549403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.855549403
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3723478162
Short name T679
Test name
Test status
Simulation time 11996246 ps
CPU time 0.69 seconds
Started Jan 24 04:24:22 PM PST 24
Finished Jan 24 04:24:27 PM PST 24
Peak memory 201188 kb
Host smart-84318733-7f8a-4e91-b956-2afe181b01ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723478162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3723478162
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.3800032659
Short name T437
Test name
Test status
Simulation time 26044520 ps
CPU time 0.86 seconds
Started Jan 24 04:24:35 PM PST 24
Finished Jan 24 04:24:37 PM PST 24
Peak memory 201300 kb
Host smart-5558132b-a72b-42f6-a5a9-4466ad9fc1fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800032659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.3800032659
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.766444437
Short name T551
Test name
Test status
Simulation time 29505903 ps
CPU time 0.8 seconds
Started Jan 24 04:24:13 PM PST 24
Finished Jan 24 04:24:17 PM PST 24
Peak memory 201296 kb
Host smart-b9a9338f-8d06-48a4-a190-d6f8cce8b681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766444437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.766444437
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1048383752
Short name T881
Test name
Test status
Simulation time 1874883782 ps
CPU time 14.7 seconds
Started Jan 24 04:43:14 PM PST 24
Finished Jan 24 04:43:30 PM PST 24
Peak memory 201556 kb
Host smart-d6156efe-aaf7-471c-b5bc-946935c40f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048383752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1048383752
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3623254813
Short name T595
Test name
Test status
Simulation time 2175731361 ps
CPU time 15.74 seconds
Started Jan 24 04:24:16 PM PST 24
Finished Jan 24 04:24:34 PM PST 24
Peak memory 201732 kb
Host smart-71d0acde-6350-4ae4-9931-4cfdc60eda81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623254813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3623254813
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.229326791
Short name T954
Test name
Test status
Simulation time 21194953 ps
CPU time 0.82 seconds
Started Jan 24 04:24:28 PM PST 24
Finished Jan 24 04:24:31 PM PST 24
Peak memory 200200 kb
Host smart-ed3ec3cc-0995-43a2-9bbe-aef94e1af70c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229326791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_idle_intersig_mubi.229326791
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3399455604
Short name T331
Test name
Test status
Simulation time 34763411 ps
CPU time 0.89 seconds
Started Jan 24 04:24:28 PM PST 24
Finished Jan 24 04:24:31 PM PST 24
Peak memory 200380 kb
Host smart-fcb0bf6f-05ef-465e-85ad-8d03c15282c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399455604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3399455604
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.4208006835
Short name T563
Test name
Test status
Simulation time 13356179 ps
CPU time 0.72 seconds
Started Jan 24 04:24:27 PM PST 24
Finished Jan 24 04:24:30 PM PST 24
Peak memory 201176 kb
Host smart-f5ffc8d5-7713-4abc-82c3-782617a7033a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208006835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.4208006835
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.1073003424
Short name T956
Test name
Test status
Simulation time 52271295 ps
CPU time 0.84 seconds
Started Jan 24 04:24:13 PM PST 24
Finished Jan 24 04:24:16 PM PST 24
Peak memory 201208 kb
Host smart-683cffb4-8bde-4e1e-b992-b9f91d5dd501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073003424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1073003424
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2171750820
Short name T567
Test name
Test status
Simulation time 15980927 ps
CPU time 0.82 seconds
Started Jan 24 04:34:09 PM PST 24
Finished Jan 24 04:34:15 PM PST 24
Peak memory 201260 kb
Host smart-9be223d5-cd1f-499c-81f3-b915549d415e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171750820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2171750820
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.1202260169
Short name T940
Test name
Test status
Simulation time 4749254149 ps
CPU time 19.95 seconds
Started Jan 24 04:24:36 PM PST 24
Finished Jan 24 04:24:58 PM PST 24
Peak memory 201756 kb
Host smart-760e36fd-6574-4b44-9a98-0ebfc89b4991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202260169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.1202260169
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.3374629139
Short name T767
Test name
Test status
Simulation time 34948002387 ps
CPU time 591.31 seconds
Started Jan 24 04:24:33 PM PST 24
Finished Jan 24 04:34:25 PM PST 24
Peak memory 211012 kb
Host smart-98b60921-660a-4922-8e52-b4a09364e009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3374629139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.3374629139
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.449802241
Short name T646
Test name
Test status
Simulation time 116936504 ps
CPU time 1.21 seconds
Started Jan 24 04:24:27 PM PST 24
Finished Jan 24 04:24:31 PM PST 24
Peak memory 201252 kb
Host smart-e8a2654e-daaa-48c5-9acf-fd8cfc33604a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449802241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.449802241
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1308071629
Short name T505
Test name
Test status
Simulation time 101785812 ps
CPU time 1.02 seconds
Started Jan 24 04:24:51 PM PST 24
Finished Jan 24 04:24:53 PM PST 24
Peak memory 201236 kb
Host smart-c7ab4057-0889-41f1-8849-d15b5990cd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308071629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1308071629
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1017411529
Short name T400
Test name
Test status
Simulation time 21243839 ps
CPU time 0.75 seconds
Started Jan 24 06:16:23 PM PST 24
Finished Jan 24 06:16:25 PM PST 24
Peak memory 201328 kb
Host smart-50a20faa-beb8-492c-b28b-92c9dccc5266
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017411529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1017411529
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.3465368263
Short name T135
Test name
Test status
Simulation time 18233831 ps
CPU time 0.7 seconds
Started Jan 24 04:24:39 PM PST 24
Finished Jan 24 04:24:41 PM PST 24
Peak memory 200120 kb
Host smart-78593819-60fa-42e5-94b6-c81f034f7a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465368263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3465368263
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.472161915
Short name T511
Test name
Test status
Simulation time 99122822 ps
CPU time 1.05 seconds
Started Jan 24 06:00:34 PM PST 24
Finished Jan 24 06:00:36 PM PST 24
Peak memory 201308 kb
Host smart-a5054ba9-2909-4a6e-9862-3c89ee79265a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472161915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_div_intersig_mubi.472161915
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.590167806
Short name T660
Test name
Test status
Simulation time 136760215 ps
CPU time 1.15 seconds
Started Jan 24 04:24:34 PM PST 24
Finished Jan 24 04:24:37 PM PST 24
Peak memory 201296 kb
Host smart-937a6d50-9f74-420f-801e-c4fb60018430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590167806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.590167806
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.3228509823
Short name T342
Test name
Test status
Simulation time 682248980 ps
CPU time 5.41 seconds
Started Jan 24 04:24:36 PM PST 24
Finished Jan 24 04:24:44 PM PST 24
Peak memory 201236 kb
Host smart-ef0f3e27-0183-47ea-9ab7-db8fe817c9a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228509823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3228509823
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2355682215
Short name T628
Test name
Test status
Simulation time 1473182112 ps
CPU time 6.12 seconds
Started Jan 24 04:24:43 PM PST 24
Finished Jan 24 04:24:51 PM PST 24
Peak memory 201424 kb
Host smart-77449809-e350-45ea-be28-f50f271ba94f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355682215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2355682215
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1918352236
Short name T962
Test name
Test status
Simulation time 52329142 ps
CPU time 0.98 seconds
Started Jan 24 04:24:41 PM PST 24
Finished Jan 24 04:24:44 PM PST 24
Peak memory 201300 kb
Host smart-d28effbe-8f42-440d-9f11-d81e15297eb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918352236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.1918352236
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2661695599
Short name T919
Test name
Test status
Simulation time 63636053 ps
CPU time 0.95 seconds
Started Jan 24 04:24:43 PM PST 24
Finished Jan 24 04:24:47 PM PST 24
Peak memory 201292 kb
Host smart-24a1cde7-071a-4824-a4cc-53862f6962cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661695599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2661695599
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.4284182744
Short name T300
Test name
Test status
Simulation time 74607817 ps
CPU time 1 seconds
Started Jan 24 04:24:41 PM PST 24
Finished Jan 24 04:24:43 PM PST 24
Peak memory 201292 kb
Host smart-8638242e-e43d-40fc-bb74-0ca278369ce7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284182744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.4284182744
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.3435421212
Short name T617
Test name
Test status
Simulation time 14850744 ps
CPU time 0.71 seconds
Started Jan 24 04:24:43 PM PST 24
Finished Jan 24 04:24:47 PM PST 24
Peak memory 201116 kb
Host smart-d2dbd5f5-09b9-4ac0-ae65-09650efb1cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435421212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3435421212
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.2382596386
Short name T734
Test name
Test status
Simulation time 1153072842 ps
CPU time 4.33 seconds
Started Jan 24 04:24:49 PM PST 24
Finished Jan 24 04:24:56 PM PST 24
Peak memory 201508 kb
Host smart-72259226-1a37-473d-bec2-6c1cc8db6b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382596386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2382596386
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.2627659911
Short name T809
Test name
Test status
Simulation time 15857199 ps
CPU time 0.85 seconds
Started Jan 24 04:24:36 PM PST 24
Finished Jan 24 04:24:39 PM PST 24
Peak memory 201080 kb
Host smart-bc29a94b-0130-4882-9a78-5c1ca1af4544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627659911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2627659911
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1891405511
Short name T316
Test name
Test status
Simulation time 4490316563 ps
CPU time 31.63 seconds
Started Jan 24 04:24:53 PM PST 24
Finished Jan 24 04:25:26 PM PST 24
Peak memory 201656 kb
Host smart-3de51ac1-1fab-421d-83f9-874582649e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891405511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1891405511
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.3173305053
Short name T717
Test name
Test status
Simulation time 42444790 ps
CPU time 0.93 seconds
Started Jan 24 04:24:42 PM PST 24
Finished Jan 24 04:24:45 PM PST 24
Peak memory 201244 kb
Host smart-779b320b-62d1-435d-9a70-a4f2a20c1740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173305053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3173305053
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.3305108128
Short name T747
Test name
Test status
Simulation time 16934592 ps
CPU time 0.83 seconds
Started Jan 24 04:12:30 PM PST 24
Finished Jan 24 04:12:32 PM PST 24
Peak memory 201276 kb
Host smart-efa9bd7c-f7dd-4e59-baec-5a2a47795b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305108128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.3305108128
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3627834622
Short name T927
Test name
Test status
Simulation time 26988313 ps
CPU time 0.91 seconds
Started Jan 24 04:12:33 PM PST 24
Finished Jan 24 04:12:35 PM PST 24
Peak memory 201208 kb
Host smart-473cde45-f4be-44f3-89e2-ae6a35ca68ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627834622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.3627834622
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.2498085360
Short name T132
Test name
Test status
Simulation time 15135986 ps
CPU time 0.7 seconds
Started Jan 24 04:12:21 PM PST 24
Finished Jan 24 04:12:26 PM PST 24
Peak memory 201164 kb
Host smart-bfcf93bf-c9de-4e32-9632-0fe86449d758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498085360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2498085360
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3198939446
Short name T724
Test name
Test status
Simulation time 67735172 ps
CPU time 0.99 seconds
Started Jan 24 04:12:26 PM PST 24
Finished Jan 24 04:12:30 PM PST 24
Peak memory 201308 kb
Host smart-579fd622-ee99-4f2e-8dfe-d157d5fdc770
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198939446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.3198939446
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.2622528262
Short name T926
Test name
Test status
Simulation time 20469019 ps
CPU time 0.83 seconds
Started Jan 24 04:12:27 PM PST 24
Finished Jan 24 04:12:30 PM PST 24
Peak memory 201308 kb
Host smart-1c141b19-a534-42a0-bfe4-38d362710894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622528262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2622528262
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2273095348
Short name T938
Test name
Test status
Simulation time 2251337452 ps
CPU time 12.17 seconds
Started Jan 24 04:12:19 PM PST 24
Finished Jan 24 04:12:38 PM PST 24
Peak memory 201652 kb
Host smart-29461d59-48f4-4576-8b55-d68cc41f996f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273095348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2273095348
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.3039833624
Short name T345
Test name
Test status
Simulation time 1343587009 ps
CPU time 7.25 seconds
Started Jan 24 04:12:24 PM PST 24
Finished Jan 24 04:12:34 PM PST 24
Peak memory 201404 kb
Host smart-b6c17132-45d2-42ce-b40d-3b1f92602dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039833624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.3039833624
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.426995270
Short name T103
Test name
Test status
Simulation time 53986285 ps
CPU time 0.98 seconds
Started Jan 24 04:12:30 PM PST 24
Finished Jan 24 04:12:33 PM PST 24
Peak memory 201292 kb
Host smart-cdebd729-7cb9-4d7b-b877-7730793a8f6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426995270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.clkmgr_idle_intersig_mubi.426995270
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1178331742
Short name T499
Test name
Test status
Simulation time 84956056 ps
CPU time 1.04 seconds
Started Jan 24 06:43:32 PM PST 24
Finished Jan 24 06:43:34 PM PST 24
Peak memory 201308 kb
Host smart-bd8091ea-c395-47e8-b2a0-6641e03e6468
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178331742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.1178331742
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.50826383
Short name T472
Test name
Test status
Simulation time 16853756 ps
CPU time 0.74 seconds
Started Jan 24 04:12:28 PM PST 24
Finished Jan 24 04:12:30 PM PST 24
Peak memory 201284 kb
Host smart-96e72a65-2034-4db2-a283-9520fad06488
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50826383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_lc_ctrl_intersig_mubi.50826383
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.1005864208
Short name T740
Test name
Test status
Simulation time 38884955 ps
CPU time 0.79 seconds
Started Jan 24 04:12:17 PM PST 24
Finished Jan 24 04:12:25 PM PST 24
Peak memory 201176 kb
Host smart-5ad01f80-2bad-4cbb-ae1a-c20a239dedc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005864208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.1005864208
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.2347475769
Short name T883
Test name
Test status
Simulation time 894139645 ps
CPU time 3.51 seconds
Started Jan 24 05:56:04 PM PST 24
Finished Jan 24 05:56:09 PM PST 24
Peak memory 201560 kb
Host smart-a62de6d1-3e5e-4d6c-9b7f-694f0a2b2bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347475769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2347475769
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.1201663786
Short name T890
Test name
Test status
Simulation time 56600962 ps
CPU time 0.99 seconds
Started Jan 24 04:12:19 PM PST 24
Finished Jan 24 04:12:26 PM PST 24
Peak memory 201252 kb
Host smart-024b547f-0583-44a0-b3f0-34ee83dd3229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201663786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.1201663786
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.2926857351
Short name T633
Test name
Test status
Simulation time 4190578702 ps
CPU time 17.55 seconds
Started Jan 24 04:21:09 PM PST 24
Finished Jan 24 04:21:28 PM PST 24
Peak memory 201720 kb
Host smart-b6a7c6db-bf0c-49de-9e8a-7cee9ab3a19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926857351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.2926857351
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3258512850
Short name T541
Test name
Test status
Simulation time 28165975547 ps
CPU time 382.59 seconds
Started Jan 24 04:12:32 PM PST 24
Finished Jan 24 04:18:56 PM PST 24
Peak memory 209988 kb
Host smart-d6762adb-c6f0-4423-8232-63fb08a43af7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3258512850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3258512850
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2384953967
Short name T549
Test name
Test status
Simulation time 23477533 ps
CPU time 0.9 seconds
Started Jan 24 04:12:19 PM PST 24
Finished Jan 24 04:12:26 PM PST 24
Peak memory 201300 kb
Host smart-61ed7004-4c48-46c1-9d55-356ea1565ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384953967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2384953967
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.968497616
Short name T710
Test name
Test status
Simulation time 18650122 ps
CPU time 0.78 seconds
Started Jan 24 04:12:48 PM PST 24
Finished Jan 24 04:12:50 PM PST 24
Peak memory 201320 kb
Host smart-5811c1a0-fd4b-461d-8c6b-46ae18240760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968497616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.968497616
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3613460454
Short name T320
Test name
Test status
Simulation time 45109524 ps
CPU time 0.86 seconds
Started Jan 24 04:12:55 PM PST 24
Finished Jan 24 04:12:57 PM PST 24
Peak memory 201288 kb
Host smart-e0369e60-573f-4f12-87de-cfbbdd94bf3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613460454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.3613460454
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.3211227410
Short name T558
Test name
Test status
Simulation time 33472202 ps
CPU time 0.74 seconds
Started Jan 24 05:09:52 PM PST 24
Finished Jan 24 05:10:00 PM PST 24
Peak memory 200128 kb
Host smart-3ed5ef34-534c-47cf-b5e3-68273bd5378e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211227410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3211227410
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.250161446
Short name T640
Test name
Test status
Simulation time 33805736 ps
CPU time 0.87 seconds
Started Jan 24 04:45:12 PM PST 24
Finished Jan 24 04:45:15 PM PST 24
Peak memory 201296 kb
Host smart-ae64c7e3-837f-460e-868f-edca466c6fb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250161446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_div_intersig_mubi.250161446
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.4135190291
Short name T604
Test name
Test status
Simulation time 27702513 ps
CPU time 0.82 seconds
Started Jan 24 04:37:01 PM PST 24
Finished Jan 24 04:37:04 PM PST 24
Peak memory 201304 kb
Host smart-6996546e-1b0c-4d7c-91fe-d998af458cdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135190291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.4135190291
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.289331844
Short name T867
Test name
Test status
Simulation time 1464599944 ps
CPU time 6.46 seconds
Started Jan 24 05:21:17 PM PST 24
Finished Jan 24 05:21:24 PM PST 24
Peak memory 201320 kb
Host smart-7b355228-52c1-4bf8-910f-075ccbcf86d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289331844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.289331844
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.4196949841
Short name T568
Test name
Test status
Simulation time 1579905426 ps
CPU time 11.27 seconds
Started Jan 24 04:41:13 PM PST 24
Finished Jan 24 04:41:31 PM PST 24
Peak memory 201432 kb
Host smart-0a3ae354-60a4-45d0-9d2c-56e23f9e5e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196949841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.4196949841
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3778329885
Short name T347
Test name
Test status
Simulation time 15952427 ps
CPU time 0.79 seconds
Started Jan 24 04:40:16 PM PST 24
Finished Jan 24 04:40:18 PM PST 24
Peak memory 201196 kb
Host smart-04d46c79-1acf-43c3-ac4f-d7bbdf22947d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778329885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3778329885
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2573564770
Short name T336
Test name
Test status
Simulation time 29739008 ps
CPU time 0.8 seconds
Started Jan 24 04:12:49 PM PST 24
Finished Jan 24 04:12:52 PM PST 24
Peak memory 201240 kb
Host smart-04465c82-66e8-4547-bf2d-4994b6caf4a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573564770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2573564770
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1661132395
Short name T607
Test name
Test status
Simulation time 45924179 ps
CPU time 0.82 seconds
Started Jan 24 04:12:45 PM PST 24
Finished Jan 24 04:12:47 PM PST 24
Peak memory 201276 kb
Host smart-f4ac3b0c-3d81-4913-bc68-fe83503c4494
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661132395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1661132395
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1233547387
Short name T510
Test name
Test status
Simulation time 12363076 ps
CPU time 0.81 seconds
Started Jan 24 04:43:14 PM PST 24
Finished Jan 24 04:43:16 PM PST 24
Peak memory 201176 kb
Host smart-a40c0ec1-a723-49c1-af6c-544d76ece235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233547387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1233547387
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3473827609
Short name T748
Test name
Test status
Simulation time 983518451 ps
CPU time 4.63 seconds
Started Jan 24 05:29:33 PM PST 24
Finished Jan 24 05:29:38 PM PST 24
Peak memory 201512 kb
Host smart-67855053-c2a2-4f70-b146-cfc20f8319d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473827609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3473827609
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1677547523
Short name T773
Test name
Test status
Simulation time 46656847 ps
CPU time 0.94 seconds
Started Jan 24 04:12:33 PM PST 24
Finished Jan 24 04:12:35 PM PST 24
Peak memory 201148 kb
Host smart-20369a8c-9f64-4c16-a819-2f6e8e70b7a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677547523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1677547523
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.48869193
Short name T455
Test name
Test status
Simulation time 5811851019 ps
CPU time 40.54 seconds
Started Jan 24 04:12:56 PM PST 24
Finished Jan 24 04:13:37 PM PST 24
Peak memory 201784 kb
Host smart-f4466dd7-cc3b-4018-b611-39c3f5d9d74c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48869193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_stress_all.48869193
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.3433472874
Short name T422
Test name
Test status
Simulation time 56887309694 ps
CPU time 547.91 seconds
Started Jan 24 04:25:32 PM PST 24
Finished Jan 24 04:34:43 PM PST 24
Peak memory 218216 kb
Host smart-9f0e9d5a-93bd-415a-af5f-2cdbac5375ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3433472874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.3433472874
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1714096029
Short name T763
Test name
Test status
Simulation time 28725366 ps
CPU time 0.95 seconds
Started Jan 24 04:12:38 PM PST 24
Finished Jan 24 04:12:40 PM PST 24
Peak memory 201252 kb
Host smart-a16e4d29-b3a5-480a-84fe-82871779e3f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714096029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1714096029
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3986343682
Short name T294
Test name
Test status
Simulation time 54942313 ps
CPU time 0.92 seconds
Started Jan 24 04:13:16 PM PST 24
Finished Jan 24 04:13:20 PM PST 24
Peak memory 201264 kb
Host smart-f0f3123c-1634-4d4a-98a9-e4d943395846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986343682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3986343682
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2956968531
Short name T754
Test name
Test status
Simulation time 15250663 ps
CPU time 0.75 seconds
Started Jan 24 04:13:16 PM PST 24
Finished Jan 24 04:13:20 PM PST 24
Peak memory 201320 kb
Host smart-2981bd5e-f98b-4d88-b829-93f228436979
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956968531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.2956968531
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2709289726
Short name T133
Test name
Test status
Simulation time 78648213 ps
CPU time 0.85 seconds
Started Jan 24 04:31:50 PM PST 24
Finished Jan 24 04:31:53 PM PST 24
Peak memory 200080 kb
Host smart-6a0367ee-5563-4032-b6cc-6b828a8d1159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709289726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2709289726
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3723907104
Short name T145
Test name
Test status
Simulation time 64634705 ps
CPU time 0.95 seconds
Started Jan 24 04:13:15 PM PST 24
Finished Jan 24 04:13:18 PM PST 24
Peak memory 201296 kb
Host smart-c9f53c34-cfad-4e62-9798-c3ef87f9ff25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723907104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3723907104
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3058566041
Short name T521
Test name
Test status
Simulation time 16742695 ps
CPU time 0.75 seconds
Started Jan 24 04:12:53 PM PST 24
Finished Jan 24 04:12:55 PM PST 24
Peak memory 201256 kb
Host smart-48123964-39a7-4193-95a0-71d1c96f7eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058566041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3058566041
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.2954658759
Short name T753
Test name
Test status
Simulation time 1548369611 ps
CPU time 5.89 seconds
Started Jan 24 04:23:11 PM PST 24
Finished Jan 24 04:23:26 PM PST 24
Peak memory 201376 kb
Host smart-0d755419-dafe-45ba-a708-9a48bc360af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954658759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2954658759
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.826239141
Short name T163
Test name
Test status
Simulation time 35755147 ps
CPU time 1 seconds
Started Jan 24 04:13:02 PM PST 24
Finished Jan 24 04:13:04 PM PST 24
Peak memory 201236 kb
Host smart-c6e3faa3-91a5-4df1-851e-b863c0ab6d4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826239141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.826239141
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3288799291
Short name T481
Test name
Test status
Simulation time 42915061 ps
CPU time 0.82 seconds
Started Jan 24 04:13:17 PM PST 24
Finished Jan 24 04:13:20 PM PST 24
Peak memory 201296 kb
Host smart-407fc626-4a1a-49db-bba0-d462c98437f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288799291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3288799291
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3083918338
Short name T780
Test name
Test status
Simulation time 71410944 ps
CPU time 1.03 seconds
Started Jan 24 04:13:03 PM PST 24
Finished Jan 24 04:13:05 PM PST 24
Peak memory 201276 kb
Host smart-d9f917ce-86f6-41b7-aecc-91b6f0c0e823
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083918338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3083918338
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.1434216832
Short name T687
Test name
Test status
Simulation time 31800914 ps
CPU time 0.81 seconds
Started Jan 24 04:24:01 PM PST 24
Finished Jan 24 04:24:03 PM PST 24
Peak memory 201180 kb
Host smart-a3e8e26c-898d-4ef7-b634-ea16945f592e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434216832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1434216832
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.4167485743
Short name T704
Test name
Test status
Simulation time 158530473 ps
CPU time 1.3 seconds
Started Jan 24 04:13:14 PM PST 24
Finished Jan 24 04:13:17 PM PST 24
Peak memory 201260 kb
Host smart-6d59bdb6-a902-40f1-8fc7-a58f5154fb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167485743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4167485743
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.4164942073
Short name T857
Test name
Test status
Simulation time 182361543 ps
CPU time 1.32 seconds
Started Jan 24 04:13:00 PM PST 24
Finished Jan 24 04:13:03 PM PST 24
Peak memory 201260 kb
Host smart-d2b66afd-4eba-4417-a0d3-84b675067a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164942073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.4164942073
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.4155001359
Short name T351
Test name
Test status
Simulation time 5572130496 ps
CPU time 40.17 seconds
Started Jan 24 04:13:15 PM PST 24
Finished Jan 24 04:13:58 PM PST 24
Peak memory 201716 kb
Host smart-8a8f6937-039b-465d-b201-41bde8b22326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155001359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.4155001359
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.2327779326
Short name T337
Test name
Test status
Simulation time 19584411869 ps
CPU time 195.04 seconds
Started Jan 24 04:13:14 PM PST 24
Finished Jan 24 04:16:31 PM PST 24
Peak memory 217472 kb
Host smart-61efca38-2c9f-4cdc-bbec-358dbcb93b5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2327779326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2327779326
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.2763307622
Short name T828
Test name
Test status
Simulation time 50950372 ps
CPU time 0.92 seconds
Started Jan 24 04:13:21 PM PST 24
Finished Jan 24 04:13:24 PM PST 24
Peak memory 201264 kb
Host smart-77dea3bd-41bd-4bf2-9f14-26e88aef6109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763307622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.2763307622
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2338744721
Short name T474
Test name
Test status
Simulation time 83849857 ps
CPU time 1.09 seconds
Started Jan 24 04:13:27 PM PST 24
Finished Jan 24 04:13:29 PM PST 24
Peak memory 201304 kb
Host smart-a2cd91f6-6629-4164-a3c8-5cc16af0d7de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338744721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.2338744721
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2692098751
Short name T835
Test name
Test status
Simulation time 17486228 ps
CPU time 0.75 seconds
Started Jan 24 04:13:13 PM PST 24
Finished Jan 24 04:13:16 PM PST 24
Peak memory 200120 kb
Host smart-42f7d373-be5c-49a2-ae6b-4d76b13725a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692098751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2692098751
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1052177999
Short name T825
Test name
Test status
Simulation time 92513906 ps
CPU time 1.06 seconds
Started Jan 24 04:13:22 PM PST 24
Finished Jan 24 04:13:24 PM PST 24
Peak memory 201308 kb
Host smart-13b14a29-f4ce-4909-ba9e-ce33742a383a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052177999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.1052177999
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.617526920
Short name T626
Test name
Test status
Simulation time 86364759 ps
CPU time 1.05 seconds
Started Jan 24 04:13:18 PM PST 24
Finished Jan 24 04:13:21 PM PST 24
Peak memory 201312 kb
Host smart-0256c0bb-173a-4ae6-ab30-442770c48408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617526920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.617526920
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.712645605
Short name T860
Test name
Test status
Simulation time 500436093 ps
CPU time 2.55 seconds
Started Jan 24 04:13:14 PM PST 24
Finished Jan 24 04:13:18 PM PST 24
Peak memory 201356 kb
Host smart-955a003c-0819-433f-86e5-916a7fc07874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712645605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.712645605
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.3682957559
Short name T959
Test name
Test status
Simulation time 2417385962 ps
CPU time 16.58 seconds
Started Jan 24 04:13:15 PM PST 24
Finished Jan 24 04:13:34 PM PST 24
Peak memory 201744 kb
Host smart-4ebd0b31-ce29-40b6-a0de-b7aa93d2a204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682957559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.3682957559
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1779902683
Short name T293
Test name
Test status
Simulation time 16009623 ps
CPU time 0.75 seconds
Started Jan 24 04:13:14 PM PST 24
Finished Jan 24 04:13:17 PM PST 24
Peak memory 201216 kb
Host smart-0f1016e8-e484-41c5-bea6-62cd11277f9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779902683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1779902683
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1230178567
Short name T665
Test name
Test status
Simulation time 21596885 ps
CPU time 0.77 seconds
Started Jan 24 04:13:23 PM PST 24
Finished Jan 24 04:13:25 PM PST 24
Peak memory 201304 kb
Host smart-2aed0545-29d9-47f1-9ee0-39d317efea8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230178567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1230178567
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2055871863
Short name T512
Test name
Test status
Simulation time 68770537 ps
CPU time 0.98 seconds
Started Jan 24 04:13:17 PM PST 24
Finished Jan 24 04:13:21 PM PST 24
Peak memory 201296 kb
Host smart-5450a905-0c8c-400d-9e22-6cdeb1b27c59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055871863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.2055871863
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.503160649
Short name T449
Test name
Test status
Simulation time 51581064 ps
CPU time 0.82 seconds
Started Jan 24 04:13:11 PM PST 24
Finished Jan 24 04:13:13 PM PST 24
Peak memory 201120 kb
Host smart-a7a3fb2b-d7b8-4e5f-9ec6-b74613cd8a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503160649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.503160649
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.958080131
Short name T625
Test name
Test status
Simulation time 816274356 ps
CPU time 4.71 seconds
Started Jan 24 04:13:29 PM PST 24
Finished Jan 24 04:13:35 PM PST 24
Peak memory 201528 kb
Host smart-28d56de5-6fe3-4706-967e-6afab5df5a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958080131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.958080131
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2393635435
Short name T814
Test name
Test status
Simulation time 157715440 ps
CPU time 1.18 seconds
Started Jan 24 04:13:10 PM PST 24
Finished Jan 24 04:13:13 PM PST 24
Peak memory 201260 kb
Host smart-6364496d-f56e-4107-b7d5-1724b9c1c5a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393635435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2393635435
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.1385320707
Short name T111
Test name
Test status
Simulation time 3037817474 ps
CPU time 12.9 seconds
Started Jan 24 04:13:22 PM PST 24
Finished Jan 24 04:13:36 PM PST 24
Peak memory 201688 kb
Host smart-31043e37-981c-48b3-9b45-6a9ebf232a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385320707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.1385320707
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.3041303255
Short name T524
Test name
Test status
Simulation time 52848500495 ps
CPU time 763.49 seconds
Started Jan 24 04:13:21 PM PST 24
Finished Jan 24 04:26:06 PM PST 24
Peak memory 212916 kb
Host smart-0e2d6d11-f4ee-4b47-8ba2-e9af09730d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3041303255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.3041303255
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2819868507
Short name T635
Test name
Test status
Simulation time 43506473 ps
CPU time 1.05 seconds
Started Jan 24 04:13:16 PM PST 24
Finished Jan 24 04:13:20 PM PST 24
Peak memory 201316 kb
Host smart-96665786-898e-436f-b92f-ae5eb383bf4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819868507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2819868507
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3146836963
Short name T513
Test name
Test status
Simulation time 31540273 ps
CPU time 1.04 seconds
Started Jan 24 04:13:37 PM PST 24
Finished Jan 24 04:13:39 PM PST 24
Peak memory 201308 kb
Host smart-4579f63e-9b38-40de-b009-6f5303eb9715
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146836963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3146836963
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.4078737907
Short name T45
Test name
Test status
Simulation time 41719726 ps
CPU time 0.77 seconds
Started Jan 24 04:13:31 PM PST 24
Finished Jan 24 04:13:33 PM PST 24
Peak memory 200120 kb
Host smart-c2adff4b-c922-4d63-9e48-d641206a244d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078737907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4078737907
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3713550786
Short name T677
Test name
Test status
Simulation time 35830394 ps
CPU time 0.92 seconds
Started Jan 24 04:13:33 PM PST 24
Finished Jan 24 04:13:36 PM PST 24
Peak memory 201284 kb
Host smart-d9826bfc-fe4d-470f-9599-04e64788bfa1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713550786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3713550786
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.673838224
Short name T356
Test name
Test status
Simulation time 17816211 ps
CPU time 0.77 seconds
Started Jan 24 04:13:19 PM PST 24
Finished Jan 24 04:13:22 PM PST 24
Peak memory 201316 kb
Host smart-0e794da8-392c-4165-a415-76bd0ec99ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673838224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.673838224
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.3171825132
Short name T397
Test name
Test status
Simulation time 2010815534 ps
CPU time 10.98 seconds
Started Jan 24 04:13:20 PM PST 24
Finished Jan 24 04:13:33 PM PST 24
Peak memory 201552 kb
Host smart-77becab6-4675-4234-81f4-4d561ee4c4bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171825132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.3171825132
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.4075251346
Short name T721
Test name
Test status
Simulation time 2498162976 ps
CPU time 8.44 seconds
Started Jan 24 04:13:30 PM PST 24
Finished Jan 24 04:13:39 PM PST 24
Peak memory 201676 kb
Host smart-b2862496-5f66-4ba6-a30d-4767b2f9fd2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075251346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.4075251346
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1442477334
Short name T164
Test name
Test status
Simulation time 38607700 ps
CPU time 0.91 seconds
Started Jan 24 04:13:35 PM PST 24
Finished Jan 24 04:13:37 PM PST 24
Peak memory 201304 kb
Host smart-acfeb064-5dc8-47ad-892d-b70996ce8213
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442477334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.1442477334
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1230815788
Short name T564
Test name
Test status
Simulation time 50859586 ps
CPU time 0.82 seconds
Started Jan 24 04:13:37 PM PST 24
Finished Jan 24 04:13:39 PM PST 24
Peak memory 201292 kb
Host smart-ac5745d1-cd32-4b47-934a-31c9a5a4da25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230815788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1230815788
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2608588029
Short name T146
Test name
Test status
Simulation time 27104234 ps
CPU time 0.99 seconds
Started Jan 24 04:13:32 PM PST 24
Finished Jan 24 04:13:34 PM PST 24
Peak memory 201252 kb
Host smart-63723881-db1e-4af1-97d0-40501727f555
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608588029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.2608588029
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.780465892
Short name T29
Test name
Test status
Simulation time 42117246 ps
CPU time 0.88 seconds
Started Jan 24 04:13:30 PM PST 24
Finished Jan 24 04:13:31 PM PST 24
Peak memory 200500 kb
Host smart-0f2a84e6-fca0-480c-917e-bf23ca29dfcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780465892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.780465892
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.3208061413
Short name T896
Test name
Test status
Simulation time 462218030 ps
CPU time 2.96 seconds
Started Jan 24 04:13:33 PM PST 24
Finished Jan 24 04:13:38 PM PST 24
Peak memory 201304 kb
Host smart-ed93cf25-d009-479c-8b3c-8be810d221a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208061413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3208061413
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.83082415
Short name T286
Test name
Test status
Simulation time 16395645 ps
CPU time 0.78 seconds
Started Jan 24 04:13:23 PM PST 24
Finished Jan 24 04:13:25 PM PST 24
Peak memory 201140 kb
Host smart-65a0d699-c947-40ab-bdaf-3637384313c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83082415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.83082415
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.3961430893
Short name T821
Test name
Test status
Simulation time 4111197096 ps
CPU time 20.97 seconds
Started Jan 24 06:42:38 PM PST 24
Finished Jan 24 06:42:59 PM PST 24
Peak memory 201720 kb
Host smart-24c0a96d-fafe-4086-8f07-202d20b2ff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961430893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.3961430893
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3265400231
Short name T539
Test name
Test status
Simulation time 154855862787 ps
CPU time 1052.26 seconds
Started Jan 24 04:13:37 PM PST 24
Finished Jan 24 04:31:10 PM PST 24
Peak memory 210104 kb
Host smart-6fdf1897-c897-481d-a16e-406426c7f793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3265400231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3265400231
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.1717972153
Short name T411
Test name
Test status
Simulation time 51174346 ps
CPU time 0.85 seconds
Started Jan 24 04:13:30 PM PST 24
Finished Jan 24 04:13:31 PM PST 24
Peak memory 201168 kb
Host smart-483a0062-4b57-4493-a509-f2910471af8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717972153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1717972153
Directory /workspace/9.clkmgr_trans/latest
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