Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276553692

1

T4

94570

T6

2520

T7

2086

auto[1]

402998

1

T4

986

T24

964

T25

980

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276570712

1

T4

94730

T6

2520

T7

2086

auto[1]

385978

1

T4

826

T23

68

T24

504

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276477988

1

T4

94630

T6

2520

T7

2086

auto[1]

478702

1

T4

926

T23

64

T24

724

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255662122

1

T4

93852

T6

2520

T7

2086

auto[1]

21294568

1

T4

1704

T23

2346

T24

1282

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168466418

1

T4

84006

T6

2474

T7

1594

auto[1]

108490272

1

T4

11550

T6

46

T7

492

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

147397992

1

T4

81930

T6

2474

T7

1594

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

107940132

1

T4

11302

T6

46

T7

492

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27530

1

T4

80

T24

58

T25

60

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6980

1

T24

10

T1

16

T17

28

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

20502610

1

T4

906

T23

2112

T24

640

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

431808

1

T4

66

T23

170

T25

192

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50290

1

T4

40

T24

150

T25

154

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14366

1

T25

74

T1

516

T17

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51842

1

T4

12

T23

12

T24

42

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1496

1

T4

16

T2

2

T107

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11908

1

T4

76

T24

154

T1

236

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2986

1

T4

70

T2

38

T107

70

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10662

1

T4

58

T24

18

T1

206

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2828

1

T23

8

T1

148

T17

52

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19884

1

T4

74

T24

76

T1

242

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4674

1

T1

104

T2

64

T3

74

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53608

1

T4

36

T24

60

T25

100

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4010

1

T24

22

T25

60

T1

26

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32490

1

T4

240

T24

62

T25

214

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7598

1

T24

138

T105

160

T3

212

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

28800

1

T4

22

T23

16

T24

40

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7250

1

T25

32

T1

394

T17

22

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51750

1

T4

108

T24

188

T25

262

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13498

1

T1

514

T17

78

T20

46

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57964

1

T4

4

T23

8

T24

44

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6192

1

T1

46

T17

10

T20

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46970

1

T4

86

T25

72

T1

510

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12424

1

T1

136

T17

48

T2

78

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43738

1

T4

192

T23

32

T24

42

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12760

1

T4

26

T23

8

T1

380

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

78380

1

T4

142

T24

128

T25

144

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21270

1

T4

70

T1

432

T2

74