Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336396400

1

T5

3732

T6

2942

T7

2294

auto[1]

449316

1

T5

404

T6

70

T7

322

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336425670

1

T5

3884

T6

2686

T7

2296

auto[1]

420046

1

T5

252

T6

326

T7

320

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

336319388

1

T5

3468

T6

2588

T7

2368

auto[1]

526328

1

T5

668

T6

424

T7

248

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307445066

1

T5

922

T6

284

T7

2530

auto[1]

29400650

1

T5

3214

T6

2728

T7

86

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197138540

1

T5

3968

T6

2604

T7

748

auto[1]

139707176

1

T5

168

T6

408

T7

1868

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

174021352

1

T5

520

T6

186

T7

482

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133069598

1

T5

22

T6

22

T7

1656

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

33384

1

T5

26

T7

26

T24

42

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8822

1

T24

14

T1

4

T3

66

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

22487564

1

T5

2792

T6

1984

T22

1452

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6516260

1

T5

92

T6

292

T7

78

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56316

1

T5

16

T22

30

T24

28

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12656

1

T1

28

T3

242

T11

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54578

1

T24

6

T1

54

T3

50

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1430

1

T7

30

T1

16

T3

52

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13068

1

T24

96

T1

52

T3

228

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2428

1

T7

88

T3

100

T142

44

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11606

1

T6

104

T24

94

T1

66

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3042

1

T7

8

T1

50

T3

24

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21780

1

T24

70

T1

198

T3

306

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5504

1

T1

198

T3

116

T11

66

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

55828

1

T5

84

T6

34

T7

16

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4910

1

T24

22

T1

42

T3

74

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36200

1

T5

134

T7

38

T24

80

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8862

1

T24

80

T1

102

T101

82

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32934

1

T5

46

T6

104

T22

36

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7948

1

T6

64

T24

36

T1

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59912

1

T5

152

T22

110

T24

78

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13124

1

T1

58

T3

182

T101

76

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65690

1

T5

60

T6

42

T7

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4980

1

T7

8

T1

18

T3

88

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52454

1

T5

76

T7

170

T24

328

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11482

1

T1

38

T3

174

T11

54

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46632

1

T5

62

T6

80

T24

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12048

1

T5

54

T6

30

T24

34

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

89242

1

T6

70

T1

808

T3

1420

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

24082

1

T1

156

T3

616

T11

54