Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294821590 1 T8 3726 T4 7214 T9 2002
auto[1] 435454 1 T9 128 T29 624 T34 1004


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294780936 1 T8 3726 T4 7214 T9 2070
auto[1] 476108 1 T9 60 T29 360 T5 2708


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294705862 1 T8 3726 T4 7214 T9 2004
auto[1] 551182 1 T9 126 T29 406 T34 1072


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 279034880 1 T8 3726 T4 7214 T9 2130
auto[1] 16222164 1 T34 3668 T38 2834 T40 2688


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 164575640 1 T8 698 T4 7214 T9 2130
auto[1] 130681404 1 T8 3028 T29 520 T30 2788


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 150658428 1 T8 698 T4 7214 T9 1998
auto[0] auto[0] auto[0] auto[0] auto[1] 127958270 1 T8 3028 T29 358 T30 2788
auto[0] auto[0] auto[0] auto[1] auto[0] 31342 1 T9 6 T29 148 T34 20
auto[0] auto[0] auto[0] auto[1] auto[1] 8440 1 T34 8 T2 126 T110 26
auto[0] auto[0] auto[1] auto[0] auto[0] 13237568 1 T34 296 T38 378 T40 2586
auto[0] auto[0] auto[1] auto[0] auto[1] 2602858 1 T34 2496 T38 2052 T1 258
auto[0] auto[0] auto[1] auto[1] auto[0] 55990 1 T34 76 T38 16 T1 160
auto[0] auto[0] auto[1] auto[1] auto[1] 13106 1 T34 84 T38 12 T1 32
auto[0] auto[1] auto[0] auto[0] auto[0] 78990 1 T29 38 T5 2708 T20 12
auto[0] auto[1] auto[0] auto[0] auto[1] 2000 1 T29 16 T34 52 T2 8
auto[0] auto[1] auto[0] auto[1] auto[0] 13328 1 T29 172 T2 344 T12 344
auto[0] auto[1] auto[0] auto[1] auto[1] 4304 1 T2 120 T12 80 T14 60
auto[0] auto[1] auto[1] auto[0] auto[0] 11304 1 T40 16 T1 78 T20 42
auto[0] auto[1] auto[1] auto[0] auto[1] 2754 1 T38 8 T1 10 T2 40
auto[0] auto[1] auto[1] auto[1] auto[0] 22250 1 T40 86 T1 186 T20 138
auto[0] auto[1] auto[1] auto[1] auto[1] 4930 1 T38 44 T1 64 T2 160
auto[1] auto[0] auto[0] auto[0] auto[0] 57466 1 T9 2 T29 22 T34 46
auto[1] auto[0] auto[0] auto[0] auto[1] 4304 1 T29 36 T2 52 T110 2
auto[1] auto[0] auto[0] auto[1] auto[0] 32844 1 T9 64 T29 158 T34 72
auto[1] auto[0] auto[0] auto[1] auto[1] 7928 1 T29 56 T2 164 T110 52
auto[1] auto[0] auto[1] auto[0] auto[0] 33052 1 T34 34 T38 14 T1 62
auto[1] auto[0] auto[1] auto[0] auto[1] 8042 1 T34 54 T38 20 T1 32
auto[1] auto[0] auto[1] auto[1] auto[0] 57892 1 T34 202 T38 36 T1 142
auto[1] auto[0] auto[1] auto[1] auto[1] 13406 1 T34 184 T38 42 T2 458
auto[1] auto[1] auto[0] auto[0] auto[0] 105206 1 T9 2 T29 26 T34 20
auto[1] auto[1] auto[0] auto[0] auto[1] 6640 1 T29 18 T34 58 T1 22
auto[1] auto[1] auto[0] auto[1] auto[0] 52120 1 T9 58 T29 54 T34 56
auto[1] auto[1] auto[0] auto[1] auto[1] 13270 1 T29 36 T34 104 T2 218
auto[1] auto[1] auto[1] auto[0] auto[0] 43170 1 T34 10 T38 56 T1 112
auto[1] auto[1] auto[1] auto[0] auto[1] 11538 1 T34 34 T1 14 T20 92
auto[1] auto[1] auto[1] auto[1] auto[0] 84690 1 T34 50 T38 156 T1 366
auto[1] auto[1] auto[1] auto[1] auto[1] 19614 1 T34 148 T2 238 T108 90

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