Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320307018

1

T5

2154

T6

3682

T7

1904

auto[1]

434364

1

T5

368

T6

924

T23

294

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320305624

1

T5

2116

T6

3790

T7

1904

auto[1]

435758

1

T5

406

T6

816

T23

188

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320252436

1

T5

2142

T6

3670

T7

1904

auto[1]

488946

1

T5

380

T6

936

T23

252

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300200752

1

T5

2522

T6

4460

T7

1904

auto[1]

20540630

1

T6

146

T23

2832

T24

2318

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174174600

1

T5

2350

T6

4338

T7

184

auto[1]

146566782

1

T5

172

T6

268

T7

1720

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

156798204

1

T5

1972

T6

3108

T7

184

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

143059744

1

T5

68

T6

160

T7

1720

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32930

1

T5

56

T6

122

T1

214

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9588

1

T5

20

T6

32

T25

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

16776696

1

T6

52

T23

2400

T24

506

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3380900

1

T23

96

T24

1622

T25

138

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52180

1

T6

20

T23

30

T25

60

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13464

1

T24

26

T25

4

T1

120

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

68114

1

T5

26

T6

44

T24

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1636

1

T15

2

T3

8

T152

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12576

1

T6

132

T19

44

T2

100

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3800

1

T15

58

T3

84

T31

206

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12436

1

T23

2

T15

12

T17

22

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3296

1

T25

22

T1

84

T2

24

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21500

1

T23

60

T15

162

T17

38

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5372

1

T25

46

T1

146

T2

110

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

21898

1

T6

92

T24

8

T25

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4846

1

T24

8

T17

8

T2

70

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34772

1

T6

204

T15

98

T17

90

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9236

1

T17

54

T2

340

T158

48

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31400

1

T23

26

T1

572

T15

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8362

1

T24

2

T1

34

T19

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

56352

1

T23

100

T1

598

T15

110

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15052

1

T24

62

T1

68

T19

176

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

73942

1

T5

72

T6

202

T24

62

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6468

1

T5

16

T6

12

T23

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49700

1

T5

224

T6

288

T1

172

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13298

1

T5

68

T6

64

T25

48

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47014

1

T6

12

T23

14

T24

52

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12062

1

T24

8

T25

2

T17

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

84886

1

T6

62

T23

104

T24

40

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19658

1

T25

38

T17

52

T19

208