Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295808414

1

T5

3560

T6

2424

T1

102437

auto[1]

412130

1

T5

1038

T1

318

T2

5538

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295782638

1

T5

3734

T6

2424

T1

102450

auto[1]

437906

1

T5

864

T1

182

T2

4372

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295744048

1

T5

3582

T6

2424

T1

102428

auto[1]

476496

1

T5

1016

T1

410

T2

6198

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272360176

1

T5

1216

T6

2424

T1

102254

auto[1]

23860368

1

T5

3382

T1

2146

T2

14510

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169390184

1

T5

4286

T6

2404

T1

823634

auto[1]

126830360

1

T5

312

T6

20

T1

201056

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

151458364

1

T5

586

T6

2404

T1

821284

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

120539928

1

T6

20

T1

201028

T2

391249

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31012

1

T5

96

T1

30

T2

218

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6556

1

T2

192

T16

32

T18

16

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

17316346

1

T5

2364

T1

1920

T2

9194

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6180406

1

T5

182

T2

152

T16

2030

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51928

1

T5

106

T2

914

T18

30

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12338

1

T5

6

T2

8

T16

42

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

93246

1

T5

34

T2

128

T18

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1538

1

T1

10

T104

18

T3

190

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11634

1

T5

158

T2

92

T18

66

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2514

1

T104

50

T3

216

T159

62

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11664

1

T5

26

T1

8

T2

60

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2864

1

T5

24

T16

8

T3

74

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19512

1

T2

70

T3

206

T10

74

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4198

1

T3

84

T10

194

T11

126

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

39854

1

T5

10

T1

4

T2

238

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3948

1

T1

10

T16

4

T18

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32068

1

T5

86

T1

104

T2

642

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6894

1

T16

60

T18

48

T3

74

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

28004

1

T5

122

T1

42

T2

506

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7030

1

T5

14

T2

12

T3

172

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53480

1

T5

76

T1

86

T2

710

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14482

1

T5

86

T2

68

T3

218

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

66486

1

T5

46

T1

20

T2

272

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5766

1

T1

8

T2

196

T16

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48318

1

T5

200

T1

46

T2

386

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12050

1

T2

352

T16

60

T3

378

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42624

1

T5

152

T1

38

T2

904

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10346

1

T2

26

T16

8

T3

334

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

85644

1

T5

224

T1

52

T2

1810

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19502

1

T2

76

T3

460

T10

362