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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80


Total test records in report: 1010
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T802 /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2411573943 Feb 25 12:42:10 PM PST 24 Feb 25 12:42:12 PM PST 24 158293092 ps
T803 /workspace/coverage/default/18.clkmgr_peri.3445122162 Feb 25 12:41:01 PM PST 24 Feb 25 12:41:02 PM PST 24 14640695 ps
T804 /workspace/coverage/default/21.clkmgr_smoke.2009768804 Feb 25 12:40:52 PM PST 24 Feb 25 12:40:53 PM PST 24 15688680 ps
T805 /workspace/coverage/default/47.clkmgr_peri.1672260843 Feb 25 12:42:00 PM PST 24 Feb 25 12:42:01 PM PST 24 79819121 ps
T806 /workspace/coverage/default/17.clkmgr_div_intersig_mubi.2881535699 Feb 25 12:40:40 PM PST 24 Feb 25 12:40:44 PM PST 24 81373020 ps
T807 /workspace/coverage/default/27.clkmgr_trans.1338721759 Feb 25 12:41:08 PM PST 24 Feb 25 12:41:09 PM PST 24 65133050 ps
T808 /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1007139114 Feb 25 12:41:28 PM PST 24 Feb 25 12:41:29 PM PST 24 26981714 ps
T809 /workspace/coverage/default/44.clkmgr_stress_all.1539596525 Feb 25 12:41:59 PM PST 24 Feb 25 12:42:54 PM PST 24 7817473812 ps
T810 /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1254942026 Feb 25 12:40:30 PM PST 24 Feb 25 12:47:59 PM PST 24 65105385500 ps
T811 /workspace/coverage/default/18.clkmgr_alert_test.3550750258 Feb 25 12:40:41 PM PST 24 Feb 25 12:40:44 PM PST 24 36820243 ps
T812 /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.173414058 Feb 25 12:40:59 PM PST 24 Feb 25 12:41:00 PM PST 24 33463348 ps
T813 /workspace/coverage/default/48.clkmgr_frequency.3383366937 Feb 25 12:41:49 PM PST 24 Feb 25 12:41:57 PM PST 24 1925808912 ps
T814 /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1607947618 Feb 25 12:40:17 PM PST 24 Feb 25 12:40:18 PM PST 24 50511343 ps
T815 /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1602596754 Feb 25 12:41:30 PM PST 24 Feb 25 12:41:36 PM PST 24 62156177 ps
T50 /workspace/coverage/default/2.clkmgr_sec_cm.2730113476 Feb 25 12:40:02 PM PST 24 Feb 25 12:40:08 PM PST 24 1160440736 ps
T816 /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3855432998 Feb 25 12:41:19 PM PST 24 Feb 25 12:41:25 PM PST 24 15241360 ps
T817 /workspace/coverage/default/9.clkmgr_frequency.2186759304 Feb 25 12:40:19 PM PST 24 Feb 25 12:40:24 PM PST 24 713566187 ps
T818 /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1081987475 Feb 25 12:40:45 PM PST 24 Feb 25 12:40:46 PM PST 24 33972244 ps
T819 /workspace/coverage/default/9.clkmgr_stress_all.2667359556 Feb 25 12:40:34 PM PST 24 Feb 25 12:40:49 PM PST 24 1964786967 ps
T820 /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3527635146 Feb 25 12:40:04 PM PST 24 Feb 25 12:40:05 PM PST 24 13928445 ps
T821 /workspace/coverage/default/16.clkmgr_smoke.1378012092 Feb 25 12:40:41 PM PST 24 Feb 25 12:40:44 PM PST 24 50294559 ps
T822 /workspace/coverage/default/36.clkmgr_extclk.1142161868 Feb 25 12:41:37 PM PST 24 Feb 25 12:41:38 PM PST 24 27178652 ps
T823 /workspace/coverage/default/14.clkmgr_trans.1476270195 Feb 25 12:40:54 PM PST 24 Feb 25 12:40:55 PM PST 24 18323820 ps
T39 /workspace/coverage/default/4.clkmgr_sec_cm.2011073994 Feb 25 12:40:06 PM PST 24 Feb 25 12:40:08 PM PST 24 153427112 ps
T824 /workspace/coverage/default/27.clkmgr_clk_status.575452098 Feb 25 12:41:00 PM PST 24 Feb 25 12:41:06 PM PST 24 90286710 ps
T825 /workspace/coverage/default/21.clkmgr_alert_test.1224163674 Feb 25 12:40:40 PM PST 24 Feb 25 12:40:43 PM PST 24 15341897 ps
T826 /workspace/coverage/default/2.clkmgr_frequency_timeout.1680890486 Feb 25 12:40:10 PM PST 24 Feb 25 12:40:18 PM PST 24 642153092 ps
T827 /workspace/coverage/default/3.clkmgr_stress_all.2534183319 Feb 25 12:40:10 PM PST 24 Feb 25 12:40:11 PM PST 24 21578672 ps
T828 /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2698907743 Feb 25 12:40:00 PM PST 24 Feb 25 12:40:02 PM PST 24 16106378 ps
T829 /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.4214412967 Feb 25 12:40:41 PM PST 24 Feb 25 12:40:43 PM PST 24 80876702 ps
T830 /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.2158392726 Feb 25 12:39:54 PM PST 24 Feb 25 12:51:00 PM PST 24 112902191963 ps
T831 /workspace/coverage/default/29.clkmgr_smoke.2916203835 Feb 25 12:41:12 PM PST 24 Feb 25 12:41:13 PM PST 24 84242824 ps
T832 /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2309768580 Feb 25 12:40:59 PM PST 24 Feb 25 12:41:00 PM PST 24 15642470 ps
T833 /workspace/coverage/default/41.clkmgr_peri.1017887806 Feb 25 12:41:28 PM PST 24 Feb 25 12:41:29 PM PST 24 16588459 ps
T834 /workspace/coverage/default/4.clkmgr_trans.367945313 Feb 25 12:40:09 PM PST 24 Feb 25 12:40:10 PM PST 24 41559250 ps
T835 /workspace/coverage/default/40.clkmgr_trans.2080397373 Feb 25 12:41:29 PM PST 24 Feb 25 12:41:30 PM PST 24 28828836 ps
T836 /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3758497250 Feb 25 12:41:44 PM PST 24 Feb 25 12:41:45 PM PST 24 22156188 ps
T837 /workspace/coverage/default/13.clkmgr_peri.2642623357 Feb 25 12:40:47 PM PST 24 Feb 25 12:40:48 PM PST 24 16007674 ps
T838 /workspace/coverage/default/40.clkmgr_frequency.298855916 Feb 25 12:41:28 PM PST 24 Feb 25 12:41:32 PM PST 24 597475129 ps
T839 /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.926940155 Feb 25 12:40:28 PM PST 24 Feb 25 12:50:37 PM PST 24 34256240572 ps
T840 /workspace/coverage/default/45.clkmgr_clk_status.4034970840 Feb 25 12:41:50 PM PST 24 Feb 25 12:41:51 PM PST 24 24828420 ps
T841 /workspace/coverage/default/33.clkmgr_frequency_timeout.1456088491 Feb 25 12:41:14 PM PST 24 Feb 25 12:41:26 PM PST 24 2187655794 ps
T842 /workspace/coverage/default/6.clkmgr_clk_status.1962859722 Feb 25 12:40:15 PM PST 24 Feb 25 12:40:16 PM PST 24 26298293 ps
T843 /workspace/coverage/default/24.clkmgr_frequency_timeout.3988405524 Feb 25 12:40:50 PM PST 24 Feb 25 12:40:54 PM PST 24 872331370 ps
T844 /workspace/coverage/default/43.clkmgr_frequency_timeout.2458712656 Feb 25 12:41:44 PM PST 24 Feb 25 12:41:53 PM PST 24 1214631229 ps
T845 /workspace/coverage/default/28.clkmgr_peri.3041651663 Feb 25 12:41:20 PM PST 24 Feb 25 12:41:26 PM PST 24 35520542 ps
T846 /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.4219966866 Feb 25 12:41:20 PM PST 24 Feb 25 12:41:21 PM PST 24 16464337 ps
T847 /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1527067489 Feb 25 12:40:42 PM PST 24 Feb 25 12:40:46 PM PST 24 18263854 ps
T848 /workspace/coverage/default/0.clkmgr_smoke.2319195056 Feb 25 12:39:55 PM PST 24 Feb 25 12:40:02 PM PST 24 28695033 ps
T849 /workspace/coverage/default/2.clkmgr_peri.3649812137 Feb 25 12:40:20 PM PST 24 Feb 25 12:40:21 PM PST 24 14761590 ps
T850 /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3436293220 Feb 25 12:41:29 PM PST 24 Feb 25 12:41:30 PM PST 24 132899027 ps
T851 /workspace/coverage/default/3.clkmgr_extclk.1073176396 Feb 25 12:39:54 PM PST 24 Feb 25 12:39:55 PM PST 24 12765590 ps
T852 /workspace/coverage/default/32.clkmgr_peri.656797944 Feb 25 12:41:33 PM PST 24 Feb 25 12:41:35 PM PST 24 14029946 ps
T853 /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1343106169 Feb 25 12:40:31 PM PST 24 Feb 25 12:40:33 PM PST 24 127757156 ps
T854 /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2662408405 Feb 25 12:41:51 PM PST 24 Feb 25 12:41:52 PM PST 24 83914644 ps
T60 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2941635289 Feb 25 12:30:51 PM PST 24 Feb 25 12:30:58 PM PST 24 137801436 ps
T90 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.133805679 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:05 PM PST 24 68272187 ps
T95 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1465692111 Feb 25 12:30:08 PM PST 24 Feb 25 12:30:09 PM PST 24 24672039 ps
T63 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3826024286 Feb 25 12:30:24 PM PST 24 Feb 25 12:30:26 PM PST 24 62746868 ps
T61 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2708002702 Feb 25 12:30:12 PM PST 24 Feb 25 12:30:20 PM PST 24 170264558 ps
T91 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.953138624 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:17 PM PST 24 107254858 ps
T77 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.828741128 Feb 25 12:30:26 PM PST 24 Feb 25 12:30:28 PM PST 24 20103284 ps
T855 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.872657298 Feb 25 12:30:04 PM PST 24 Feb 25 12:30:06 PM PST 24 221369349 ps
T62 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2907808006 Feb 25 12:30:40 PM PST 24 Feb 25 12:30:42 PM PST 24 100484177 ps
T856 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.404957267 Feb 25 12:31:04 PM PST 24 Feb 25 12:31:05 PM PST 24 22817595 ps
T857 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.4131515261 Feb 25 12:30:20 PM PST 24 Feb 25 12:30:21 PM PST 24 22174260 ps
T858 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2183443916 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:19 PM PST 24 23800646 ps
T92 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1125357771 Feb 25 12:30:41 PM PST 24 Feb 25 12:30:44 PM PST 24 166228788 ps
T64 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1793908742 Feb 25 12:29:59 PM PST 24 Feb 25 12:30:03 PM PST 24 165791236 ps
T78 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.805107 Feb 25 12:31:04 PM PST 24 Feb 25 12:31:07 PM PST 24 42266898 ps
T96 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3766495987 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:39 PM PST 24 132255481 ps
T859 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1025592961 Feb 25 12:30:40 PM PST 24 Feb 25 12:30:41 PM PST 24 28260706 ps
T860 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3621225018 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:52 PM PST 24 297403416 ps
T861 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2612977789 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:38 PM PST 24 241875348 ps
T862 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1142942977 Feb 25 12:30:10 PM PST 24 Feb 25 12:30:11 PM PST 24 19801289 ps
T65 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1999318645 Feb 25 12:30:00 PM PST 24 Feb 25 12:30:01 PM PST 24 83802531 ps
T863 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1627594333 Feb 25 12:30:27 PM PST 24 Feb 25 12:30:29 PM PST 24 17210097 ps
T864 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4128966551 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:22 PM PST 24 42591594 ps
T865 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.13709598 Feb 25 12:30:14 PM PST 24 Feb 25 12:30:18 PM PST 24 457802914 ps
T79 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1421276699 Feb 25 12:30:25 PM PST 24 Feb 25 12:30:26 PM PST 24 20665288 ps
T66 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3089332340 Feb 25 12:30:04 PM PST 24 Feb 25 12:30:08 PM PST 24 444495464 ps
T866 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2557566748 Feb 25 12:30:28 PM PST 24 Feb 25 12:30:30 PM PST 24 24967118 ps
T867 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1856512701 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:44 PM PST 24 28762135 ps
T868 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3315767680 Feb 25 12:30:16 PM PST 24 Feb 25 12:30:18 PM PST 24 365873362 ps
T869 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2063288926 Feb 25 12:30:12 PM PST 24 Feb 25 12:30:27 PM PST 24 3170627530 ps
T93 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1854452214 Feb 25 12:30:20 PM PST 24 Feb 25 12:30:24 PM PST 24 218455722 ps
T80 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1688558333 Feb 25 12:30:08 PM PST 24 Feb 25 12:30:09 PM PST 24 58596541 ps
T870 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.141206980 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 14277668 ps
T871 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2369406281 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:32 PM PST 24 32196633 ps
T872 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1921922792 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:43 PM PST 24 17072091 ps
T67 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1092138275 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:38 PM PST 24 116461334 ps
T873 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.588345320 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:35 PM PST 24 135154812 ps
T81 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2811926211 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:36 PM PST 24 16243127 ps
T874 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2208538316 Feb 25 12:30:12 PM PST 24 Feb 25 12:30:14 PM PST 24 11832640 ps
T101 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1613611082 Feb 25 12:29:59 PM PST 24 Feb 25 12:30:00 PM PST 24 50785497 ps
T875 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3150366371 Feb 25 12:30:06 PM PST 24 Feb 25 12:30:07 PM PST 24 97374569 ps
T876 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.694407637 Feb 25 12:30:24 PM PST 24 Feb 25 12:30:25 PM PST 24 26547850 ps
T877 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1694623920 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:18 PM PST 24 22481386 ps
T878 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1384667798 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 11141130 ps
T879 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1550695297 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:36 PM PST 24 86930163 ps
T880 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2956012996 Feb 25 12:30:18 PM PST 24 Feb 25 12:30:20 PM PST 24 145394770 ps
T94 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1035924590 Feb 25 12:30:06 PM PST 24 Feb 25 12:30:10 PM PST 24 174441390 ps
T881 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1318460812 Feb 25 12:30:09 PM PST 24 Feb 25 12:30:10 PM PST 24 21327431 ps
T68 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1333663848 Feb 25 12:30:11 PM PST 24 Feb 25 12:30:13 PM PST 24 95320376 ps
T882 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.27716369 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 23952318 ps
T883 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1786340562 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 32745091 ps
T121 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3152160531 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:05 PM PST 24 73995436 ps
T884 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.269396809 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:54 PM PST 24 18626354 ps
T157 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1870741424 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:21 PM PST 24 92706850 ps
T885 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.476407048 Feb 25 12:30:11 PM PST 24 Feb 25 12:30:12 PM PST 24 12225998 ps
T886 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.212261087 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:36 PM PST 24 11700115 ps
T887 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1852273986 Feb 25 12:30:06 PM PST 24 Feb 25 12:30:08 PM PST 24 110319079 ps
T126 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.4056133980 Feb 25 12:30:14 PM PST 24 Feb 25 12:30:16 PM PST 24 86236878 ps
T888 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1985518945 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:18 PM PST 24 520807432 ps
T889 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3971633459 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:47 PM PST 24 36606990 ps
T69 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2840913146 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:34 PM PST 24 96098571 ps
T116 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.147640720 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:35 PM PST 24 392722722 ps
T890 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1899055180 Feb 25 12:30:37 PM PST 24 Feb 25 12:30:39 PM PST 24 297939284 ps
T117 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3636475749 Feb 25 12:30:20 PM PST 24 Feb 25 12:30:22 PM PST 24 65884128 ps
T891 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3420025143 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 19410236 ps
T892 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3481513162 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:05 PM PST 24 35608426 ps
T118 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2175354477 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:35 PM PST 24 89989427 ps
T893 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1877346685 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 13852271 ps
T894 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3230457589 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:16 PM PST 24 29260054 ps
T895 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.141737900 Feb 25 12:30:09 PM PST 24 Feb 25 12:30:10 PM PST 24 16659517 ps
T896 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.168059229 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:06 PM PST 24 23286781 ps
T897 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1447729505 Feb 25 12:31:01 PM PST 24 Feb 25 12:31:03 PM PST 24 44838081 ps
T898 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1012228487 Feb 25 12:30:28 PM PST 24 Feb 25 12:30:29 PM PST 24 12123639 ps
T899 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.403358188 Feb 25 12:30:37 PM PST 24 Feb 25 12:30:38 PM PST 24 11397232 ps
T125 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1203135526 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:22 PM PST 24 175055492 ps
T119 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1923371812 Feb 25 12:30:00 PM PST 24 Feb 25 12:30:03 PM PST 24 143975604 ps
T900 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.9032615 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:47 PM PST 24 157110329 ps
T901 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.817463038 Feb 25 12:30:54 PM PST 24 Feb 25 12:30:55 PM PST 24 56157374 ps
T134 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.247853223 Feb 25 12:30:32 PM PST 24 Feb 25 12:30:35 PM PST 24 280859628 ps
T902 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2125028619 Feb 25 12:30:49 PM PST 24 Feb 25 12:30:51 PM PST 24 156050533 ps
T127 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1052994075 Feb 25 12:30:01 PM PST 24 Feb 25 12:30:04 PM PST 24 311230954 ps
T903 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2201350278 Feb 25 12:30:23 PM PST 24 Feb 25 12:30:24 PM PST 24 34698328 ps
T904 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2453007285 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:29 PM PST 24 64757615 ps
T120 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3596349879 Feb 25 12:30:29 PM PST 24 Feb 25 12:30:32 PM PST 24 97550732 ps
T905 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1239166590 Feb 25 12:30:38 PM PST 24 Feb 25 12:30:39 PM PST 24 18596535 ps
T129 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.124153906 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:06 PM PST 24 166148284 ps
T906 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3112971656 Feb 25 12:31:08 PM PST 24 Feb 25 12:31:09 PM PST 24 41866668 ps
T907 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.188410756 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:19 PM PST 24 28712977 ps
T908 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.244244331 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:37 PM PST 24 25052153 ps
T909 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2228883620 Feb 25 12:29:57 PM PST 24 Feb 25 12:29:58 PM PST 24 26556219 ps
T910 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3064132675 Feb 25 12:30:18 PM PST 24 Feb 25 12:30:20 PM PST 24 65738853 ps
T911 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2556428308 Feb 25 12:30:28 PM PST 24 Feb 25 12:30:29 PM PST 24 29614064 ps
T130 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3946446341 Feb 25 12:30:16 PM PST 24 Feb 25 12:30:17 PM PST 24 90180458 ps
T912 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1691063641 Feb 25 12:30:14 PM PST 24 Feb 25 12:30:16 PM PST 24 44355133 ps
T913 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.4159332255 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:36 PM PST 24 11745743 ps
T914 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.298904801 Feb 25 12:30:36 PM PST 24 Feb 25 12:30:37 PM PST 24 38968152 ps
T915 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2050266718 Feb 25 12:30:18 PM PST 24 Feb 25 12:30:19 PM PST 24 41137454 ps
T916 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1706377158 Feb 25 12:30:46 PM PST 24 Feb 25 12:30:53 PM PST 24 12215616 ps
T97 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3481869105 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:21 PM PST 24 63383913 ps
T122 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1834158409 Feb 25 12:30:13 PM PST 24 Feb 25 12:30:15 PM PST 24 248436806 ps
T917 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1617959210 Feb 25 12:30:41 PM PST 24 Feb 25 12:30:42 PM PST 24 26057081 ps
T918 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.900016271 Feb 25 12:30:40 PM PST 24 Feb 25 12:30:42 PM PST 24 61269293 ps
T131 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1833017104 Feb 25 12:30:43 PM PST 24 Feb 25 12:30:45 PM PST 24 49633086 ps
T919 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1384431843 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:34 PM PST 24 324513982 ps
T920 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2897001501 Feb 25 12:30:11 PM PST 24 Feb 25 12:30:13 PM PST 24 26373470 ps
T123 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3865585589 Feb 25 12:30:03 PM PST 24 Feb 25 12:30:15 PM PST 24 101988459 ps
T921 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.80065872 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:23 PM PST 24 233274706 ps
T922 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2343754594 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:20 PM PST 24 45376755 ps
T923 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1768088166 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:36 PM PST 24 12283545 ps
T924 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.615462676 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:25 PM PST 24 716631598 ps
T925 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2267939982 Feb 25 12:30:18 PM PST 24 Feb 25 12:30:20 PM PST 24 100287676 ps
T926 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4254930615 Feb 25 12:30:13 PM PST 24 Feb 25 12:30:30 PM PST 24 2517414634 ps
T927 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2194467817 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:40 PM PST 24 11742370 ps
T928 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3425155927 Feb 25 12:31:06 PM PST 24 Feb 25 12:31:07 PM PST 24 12244629 ps
T929 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.2967495668 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:45 PM PST 24 17853964 ps
T930 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.314426310 Feb 25 12:30:29 PM PST 24 Feb 25 12:30:31 PM PST 24 32077768 ps
T931 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.32172028 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:49 PM PST 24 12789909 ps
T932 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.137638929 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:37 PM PST 24 30490749 ps
T933 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.93913510 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:20 PM PST 24 11133771 ps
T934 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1442184570 Feb 25 12:30:29 PM PST 24 Feb 25 12:30:31 PM PST 24 53408198 ps
T935 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2064505064 Feb 25 12:30:13 PM PST 24 Feb 25 12:30:14 PM PST 24 23825418 ps
T936 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.996892518 Feb 25 12:30:52 PM PST 24 Feb 25 12:30:54 PM PST 24 136799366 ps
T937 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1618331609 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:43 PM PST 24 1009981255 ps
T938 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3043841595 Feb 25 12:30:14 PM PST 24 Feb 25 12:30:17 PM PST 24 40363661 ps
T939 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.28972668 Feb 25 12:31:04 PM PST 24 Feb 25 12:31:07 PM PST 24 97614126 ps
T940 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1560792257 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:37 PM PST 24 32542252 ps
T941 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.746134767 Feb 25 12:30:22 PM PST 24 Feb 25 12:30:24 PM PST 24 116328724 ps
T942 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3124064123 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 41816446 ps
T943 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.24201495 Feb 25 12:30:13 PM PST 24 Feb 25 12:30:14 PM PST 24 35300242 ps
T124 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1242326203 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:33 PM PST 24 151286991 ps
T944 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.107454343 Feb 25 12:30:27 PM PST 24 Feb 25 12:30:30 PM PST 24 253217601 ps
T945 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3408291914 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:46 PM PST 24 373297258 ps
T946 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1452493533 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 82520644 ps
T947 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3288977936 Feb 25 12:30:47 PM PST 24 Feb 25 12:30:48 PM PST 24 33640096 ps
T948 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3231484461 Feb 25 12:30:37 PM PST 24 Feb 25 12:30:38 PM PST 24 37590210 ps
T949 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3537784840 Feb 25 12:30:37 PM PST 24 Feb 25 12:30:38 PM PST 24 15581634 ps
T950 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2209609360 Feb 25 12:30:58 PM PST 24 Feb 25 12:31:02 PM PST 24 486134910 ps
T951 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.424957396 Feb 25 12:30:25 PM PST 24 Feb 25 12:30:28 PM PST 24 261482057 ps
T952 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.165462738 Feb 25 12:30:29 PM PST 24 Feb 25 12:30:31 PM PST 24 86476469 ps
T953 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2157259879 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:36 PM PST 24 45454436 ps
T954 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2666429930 Feb 25 12:30:23 PM PST 24 Feb 25 12:30:24 PM PST 24 16815734 ps
T955 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.576227016 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:41 PM PST 24 35848137 ps
T956 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1236037798 Feb 25 12:30:14 PM PST 24 Feb 25 12:30:15 PM PST 24 49346603 ps
T957 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2278437574 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:45 PM PST 24 71758195 ps
T958 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3376293579 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:32 PM PST 24 12424462 ps
T158 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1973569733 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:36 PM PST 24 123588780 ps
T959 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1708052631 Feb 25 12:30:19 PM PST 24 Feb 25 12:30:21 PM PST 24 52203594 ps
T960 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2461457079 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:58 PM PST 24 141986908 ps
T961 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.918531942 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:36 PM PST 24 32768544 ps
T962 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2552904289 Feb 25 12:30:03 PM PST 24 Feb 25 12:30:05 PM PST 24 26793167 ps
T963 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2147088367 Feb 25 12:30:18 PM PST 24 Feb 25 12:30:19 PM PST 24 26342182 ps
T964 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2350923275 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:35 PM PST 24 27556450 ps
T965 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3064590055 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:40 PM PST 24 22375879 ps
T966 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3712880319 Feb 25 12:30:01 PM PST 24 Feb 25 12:30:02 PM PST 24 18898019 ps
T967 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2623060515 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:09 PM PST 24 22732748 ps
T968 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3458512092 Feb 25 12:30:13 PM PST 24 Feb 25 12:30:18 PM PST 24 391474780 ps
T969 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1233600148 Feb 25 12:30:42 PM PST 24 Feb 25 12:30:44 PM PST 24 23287933 ps
T970 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3817847308 Feb 25 12:30:37 PM PST 24 Feb 25 12:30:39 PM PST 24 96380470 ps
T971 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3255634815 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:17 PM PST 24 106533468 ps
T98 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.742944533 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:19 PM PST 24 74707272 ps
T972 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1173420466 Feb 25 12:30:44 PM PST 24 Feb 25 12:30:45 PM PST 24 51501434 ps
T973 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.59280191 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:52 PM PST 24 14923483 ps
T974 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3615295257 Feb 25 12:30:30 PM PST 24 Feb 25 12:30:33 PM PST 24 29017668 ps
T975 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1683734331 Feb 25 12:30:25 PM PST 24 Feb 25 12:30:26 PM PST 24 25961176 ps
T976 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.345656892 Feb 25 12:30:09 PM PST 24 Feb 25 12:30:10 PM PST 24 92628236 ps
T977 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3467571573 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:05 PM PST 24 19847411 ps
T978 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4275186648 Feb 25 12:30:39 PM PST 24 Feb 25 12:30:41 PM PST 24 88452041 ps
T979 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1557541770 Feb 25 12:31:02 PM PST 24 Feb 25 12:31:05 PM PST 24 67815588 ps
T980 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1968475059 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:22 PM PST 24 101123111 ps
T981 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3863055502 Feb 25 12:30:40 PM PST 24 Feb 25 12:30:44 PM PST 24 452028308 ps
T982 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2779344333 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 24540410 ps
T983 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1482315787 Feb 25 12:30:45 PM PST 24 Feb 25 12:30:46 PM PST 24 18891680 ps
T984 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2355385007 Feb 25 12:30:43 PM PST 24 Feb 25 12:30:44 PM PST 24 20180580 ps
T985 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1891962827 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:17 PM PST 24 77163884 ps
T986 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2761474478 Feb 25 12:30:12 PM PST 24 Feb 25 12:30:13 PM PST 24 29741163 ps
T156 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.4172065024 Feb 25 12:30:16 PM PST 24 Feb 25 12:30:20 PM PST 24 123933852 ps
T987 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.4136225157 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 103938994 ps
T988 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2978253650 Feb 25 12:30:12 PM PST 24 Feb 25 12:30:14 PM PST 24 64781920 ps
T989 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2221711543 Feb 25 12:30:17 PM PST 24 Feb 25 12:30:18 PM PST 24 33501609 ps
T99 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.776097354 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:23 PM PST 24 120697357 ps
T132 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3735873463 Feb 25 12:30:31 PM PST 24 Feb 25 12:30:34 PM PST 24 159603012 ps
T990 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.570414307 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:15 PM PST 24 19318286 ps
T100 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3031861409 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:36 PM PST 24 229915735 ps
T991 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.198131041 Feb 25 12:30:07 PM PST 24 Feb 25 12:30:07 PM PST 24 18010375 ps
T992 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.681787741 Feb 25 12:30:33 PM PST 24 Feb 25 12:30:34 PM PST 24 16284179 ps
T993 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1629968832 Feb 25 12:30:15 PM PST 24 Feb 25 12:30:18 PM PST 24 122565215 ps
T994 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3228189063 Feb 25 12:30:06 PM PST 24 Feb 25 12:30:09 PM PST 24 236443468 ps
T995 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1154907983 Feb 25 12:30:21 PM PST 24 Feb 25 12:30:23 PM PST 24 100539981 ps
T128 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2322985265 Feb 25 12:30:35 PM PST 24 Feb 25 12:30:38 PM PST 24 206340002 ps
T996 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2583205557 Feb 25 12:30:23 PM PST 24 Feb 25 12:30:24 PM PST 24 18619735 ps
T997 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2724478855 Feb 25 12:30:38 PM PST 24 Feb 25 12:30:40 PM PST 24 31512178 ps
T998 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2763391551 Feb 25 12:30:05 PM PST 24 Feb 25 12:30:06 PM PST 24 37415773 ps
T999 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1526614276 Feb 25 12:30:34 PM PST 24 Feb 25 12:30:36 PM PST 24 121783147 ps
T1000 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1288096102 Feb 25 12:31:03 PM PST 24 Feb 25 12:31:06 PM PST 24 119347094 ps
T1001 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1771680872 Feb 25 12:30:55 PM PST 24 Feb 25 12:30:57 PM PST 24 63794447 ps
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