Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311627124 1 T6 4736 T1 461230 T7 1404
auto[1] 459348 1 T1 2828 T17 564 T18 604


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311636732 1 T6 4736 T1 461341 T7 1404
auto[1] 449740 1 T1 1718 T17 396 T18 502


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311547868 1 T6 4736 T1 461272 T7 1404
auto[1] 538604 1 T1 2402 T17 656 T18 750


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 297070050 1 T6 4736 T1 460792 T7 1404
auto[1] 15016422 1 T1 7200 T17 2664 T18 1420


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 179052802 1 T6 4712 T1 251506 T7 1404
auto[1] 133033670 1 T6 24 T1 210006 T17 1762


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167577560 1 T6 4712 T1 250768 T7 1404
auto[0] auto[0] auto[0] auto[0] auto[1] 129135928 1 T6 24 T1 209875 T17 76
auto[0] auto[0] auto[0] auto[1] auto[0] 32010 1 T1 300 T17 16 T19 18
auto[0] auto[0] auto[0] auto[1] auto[1] 10172 1 T1 2 T17 12 T19 124
auto[0] auto[0] auto[1] auto[0] auto[0] 10843184 1 T1 4692 T17 620 T18 402
auto[0] auto[0] auto[1] auto[0] auto[1] 3758428 1 T1 592 T17 1550 T18 246
auto[0] auto[0] auto[1] auto[1] auto[0] 58582 1 T1 162 T17 6 T18 22
auto[0] auto[0] auto[1] auto[1] auto[1] 15598 1 T1 146 T17 8 T18 76
auto[0] auto[1] auto[0] auto[0] auto[0] 57806 1 T1 16 T20 18 T76 16
auto[0] auto[1] auto[0] auto[0] auto[1] 1440 1 T76 2 T12 2 T128 8
auto[0] auto[1] auto[0] auto[1] auto[0] 12196 1 T20 96 T76 44 T64 54
auto[0] auto[1] auto[0] auto[1] auto[1] 2748 1 T76 42 T12 52 T128 66
auto[0] auto[1] auto[1] auto[0] auto[0] 12296 1 T1 62 T18 34 T65 24
auto[0] auto[1] auto[1] auto[0] auto[1] 3024 1 T1 14 T2 18 T3 106
auto[0] auto[1] auto[1] auto[1] auto[0] 20888 1 T1 192 T65 54 T12 130
auto[0] auto[1] auto[1] auto[1] auto[1] 6008 1 T1 112 T2 74 T77 56
auto[1] auto[0] auto[0] auto[0] auto[0] 34164 1 T1 78 T17 2 T18 48
auto[1] auto[0] auto[0] auto[0] auto[1] 4370 1 T1 28 T19 10 T2 2
auto[1] auto[0] auto[0] auto[1] auto[0] 35946 1 T1 224 T17 66 T20 74
auto[1] auto[0] auto[0] auto[1] auto[1] 9658 1 T1 158 T19 80 T2 60
auto[1] auto[0] auto[1] auto[0] auto[0] 32764 1 T1 80 T17 44 T18 16
auto[1] auto[0] auto[1] auto[0] auto[1] 9858 1 T1 24 T17 2 T18 72
auto[1] auto[0] auto[1] auto[1] auto[0] 61210 1 T1 302 T17 102 T18 74
auto[1] auto[0] auto[1] auto[1] auto[1] 17300 1 T1 186 T17 44 T18 72
auto[1] auto[1] auto[0] auto[0] auto[0] 84584 1 T1 88 T17 2 T18 62
auto[1] auto[1] auto[0] auto[0] auto[1] 7900 1 T17 2 T19 28 T2 106
auto[1] auto[1] auto[0] auto[1] auto[0] 50152 1 T1 598 T17 54 T19 154
auto[1] auto[1] auto[0] auto[1] auto[1] 13416 1 T17 50 T19 186 T2 82
auto[1] auto[1] auto[1] auto[0] auto[0] 50886 1 T1 188 T17 64 T18 34
auto[1] auto[1] auto[1] auto[0] auto[1] 12932 1 T1 2 T17 18 T18 12
auto[1] auto[1] auto[1] auto[1] auto[0] 88574 1 T1 402 T17 206 T18 252
auto[1] auto[1] auto[1] auto[1] auto[1] 24890 1 T1 44 T18 108 T19 70

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%