SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
io_div2_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div2_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
shadow_update_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19286 | 1 | T6 | 1 | T1 | 403 | T7 | 1 | ||||
auto[1] | 734 | 1 | T1 | 2 | T2 | 4 | T11 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16344 | 1 | T6 | 1 | T1 | 278 | T7 | 1 | ||||
auto[1] | 3676 | 1 | T1 | 127 | T5 | 5 | T2 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19233 | 1 | T6 | 1 | T1 | 401 | T7 | 1 | ||||
auto[1] | 787 | 1 | T1 | 4 | T2 | 6 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16412 | 1 | T6 | 1 | T1 | 280 | T7 | 1 | ||||
auto[1] | 3608 | 1 | T1 | 125 | T5 | 5 | T2 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19263 | 1 | T6 | 1 | T1 | 402 | T7 | 1 | ||||
auto[1] | 757 | 1 | T1 | 3 | T4 | 1 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16344 | 1 | T6 | 1 | T1 | 278 | T7 | 1 | ||||
auto[1] | 3676 | 1 | T1 | 127 | T5 | 5 | T2 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19221 | 1 | T6 | 1 | T1 | 400 | T7 | 1 | ||||
auto[1] | 799 | 1 | T1 | 5 | T2 | 3 | T11 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19093 | 1 | T6 | 1 | T1 | 375 | T7 | 1 | ||||
auto[1] | 927 | 1 | T1 | 30 | T5 | 4 | T2 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19838 | 1 | T6 | 1 | T1 | 405 | T7 | 1 | ||||
auto[1] | 182 | 1 | T52 | 6 | T53 | 6 | T54 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19265 | 1 | T6 | 1 | T1 | 402 | T7 | 1 | ||||
auto[1] | 755 | 1 | T1 | 3 | T4 | 1 | T2 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19100 | 1 | T6 | 1 | T1 | 376 | T7 | 1 | ||||
auto[1] | 920 | 1 | T1 | 29 | T5 | 1 | T2 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |