| T798 |
/workspace/coverage/default/36.clkmgr_stress_all.3468829635 |
|
|
Feb 28 06:10:35 PM PST 24 |
Feb 28 06:10:51 PM PST 24 |
4507883805 ps |
| T799 |
/workspace/coverage/default/32.clkmgr_div_intersig_mubi.2807321341 |
|
|
Feb 28 06:10:24 PM PST 24 |
Feb 28 06:10:25 PM PST 24 |
23194739 ps |
| T800 |
/workspace/coverage/default/39.clkmgr_frequency.3099212985 |
|
|
Feb 28 06:10:40 PM PST 24 |
Feb 28 06:10:44 PM PST 24 |
680161704 ps |
| T801 |
/workspace/coverage/default/16.clkmgr_div_intersig_mubi.3883475553 |
|
|
Feb 28 06:09:43 PM PST 24 |
Feb 28 06:09:44 PM PST 24 |
21210331 ps |
| T802 |
/workspace/coverage/default/3.clkmgr_extclk.1457143749 |
|
|
Feb 28 06:08:51 PM PST 24 |
Feb 28 06:08:52 PM PST 24 |
26069334 ps |
| T803 |
/workspace/coverage/default/25.clkmgr_regwen.3534028981 |
|
|
Feb 28 06:10:06 PM PST 24 |
Feb 28 06:10:12 PM PST 24 |
1525046726 ps |
| T804 |
/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3953809290 |
|
|
Feb 28 06:09:36 PM PST 24 |
Feb 28 06:09:37 PM PST 24 |
20636468 ps |
| T805 |
/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1022477631 |
|
|
Feb 28 06:09:20 PM PST 24 |
Feb 28 06:22:12 PM PST 24 |
41638390952 ps |
| T806 |
/workspace/coverage/default/13.clkmgr_stress_all.953076024 |
|
|
Feb 28 06:09:34 PM PST 24 |
Feb 28 06:09:37 PM PST 24 |
396905126 ps |
| T807 |
/workspace/coverage/default/34.clkmgr_stress_all.784941625 |
|
|
Feb 28 06:10:30 PM PST 24 |
Feb 28 06:10:42 PM PST 24 |
1648134821 ps |
| T808 |
/workspace/coverage/default/1.clkmgr_frequency_timeout.1681702336 |
|
|
Feb 28 06:08:44 PM PST 24 |
Feb 28 06:08:45 PM PST 24 |
181012856 ps |
| T809 |
/workspace/coverage/default/11.clkmgr_stress_all.1353338833 |
|
|
Feb 28 06:09:26 PM PST 24 |
Feb 28 06:09:45 PM PST 24 |
2475563409 ps |
| T810 |
/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.431196406 |
|
|
Feb 28 06:10:47 PM PST 24 |
Feb 28 06:23:32 PM PST 24 |
124454415080 ps |
| T811 |
/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1805168560 |
|
|
Feb 28 06:09:29 PM PST 24 |
Feb 28 06:09:31 PM PST 24 |
348281401 ps |
| T812 |
/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1681552421 |
|
|
Feb 28 06:10:19 PM PST 24 |
Feb 28 06:10:20 PM PST 24 |
26866768 ps |
| T813 |
/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1137011334 |
|
|
Feb 28 06:10:17 PM PST 24 |
Feb 28 06:10:18 PM PST 24 |
56062389 ps |
| T814 |
/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.1272569967 |
|
|
Feb 28 06:10:17 PM PST 24 |
Feb 28 06:15:40 PM PST 24 |
23284747833 ps |
| T815 |
/workspace/coverage/default/49.clkmgr_stress_all.1012240529 |
|
|
Feb 28 06:11:09 PM PST 24 |
Feb 28 06:11:28 PM PST 24 |
2491280134 ps |
| T816 |
/workspace/coverage/default/0.clkmgr_extclk.414064139 |
|
|
Feb 28 06:08:38 PM PST 24 |
Feb 28 06:08:39 PM PST 24 |
18970683 ps |
| T817 |
/workspace/coverage/default/46.clkmgr_peri.2661211726 |
|
|
Feb 28 06:10:58 PM PST 24 |
Feb 28 06:10:59 PM PST 24 |
12024731 ps |
| T818 |
/workspace/coverage/default/46.clkmgr_stress_all.411140099 |
|
|
Feb 28 06:10:58 PM PST 24 |
Feb 28 06:11:34 PM PST 24 |
4620129059 ps |
| T819 |
/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3228264080 |
|
|
Feb 28 06:08:57 PM PST 24 |
Feb 28 06:08:59 PM PST 24 |
68839201 ps |
| T820 |
/workspace/coverage/default/8.clkmgr_regwen.1301729318 |
|
|
Feb 28 06:09:18 PM PST 24 |
Feb 28 06:09:21 PM PST 24 |
651727826 ps |
| T821 |
/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1969015552 |
|
|
Feb 28 06:10:54 PM PST 24 |
Feb 28 06:10:55 PM PST 24 |
46027114 ps |
| T822 |
/workspace/coverage/default/27.clkmgr_frequency.2471979412 |
|
|
Feb 28 06:10:16 PM PST 24 |
Feb 28 06:10:23 PM PST 24 |
796848457 ps |
| T823 |
/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.712032835 |
|
|
Feb 28 06:10:00 PM PST 24 |
Feb 28 06:10:01 PM PST 24 |
29254592 ps |
| T824 |
/workspace/coverage/default/25.clkmgr_smoke.625226239 |
|
|
Feb 28 06:10:02 PM PST 24 |
Feb 28 06:10:04 PM PST 24 |
77526457 ps |
| T825 |
/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2078435335 |
|
|
Feb 28 06:09:23 PM PST 24 |
Feb 28 06:09:24 PM PST 24 |
24576313 ps |
| T826 |
/workspace/coverage/default/46.clkmgr_smoke.1211965251 |
|
|
Feb 28 06:10:56 PM PST 24 |
Feb 28 06:10:57 PM PST 24 |
21483037 ps |
| T827 |
/workspace/coverage/default/49.clkmgr_trans.913075484 |
|
|
Feb 28 06:11:10 PM PST 24 |
Feb 28 06:11:12 PM PST 24 |
108754444 ps |
| T828 |
/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.255952242 |
|
|
Feb 28 06:09:38 PM PST 24 |
Feb 28 06:14:37 PM PST 24 |
31985549143 ps |
| T829 |
/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.707238726 |
|
|
Feb 28 06:09:27 PM PST 24 |
Feb 28 06:09:28 PM PST 24 |
104628749 ps |
| T830 |
/workspace/coverage/default/40.clkmgr_div_intersig_mubi.957107013 |
|
|
Feb 28 06:10:42 PM PST 24 |
Feb 28 06:10:44 PM PST 24 |
26074769 ps |
| T831 |
/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.750067982 |
|
|
Feb 28 06:08:58 PM PST 24 |
Feb 28 06:08:59 PM PST 24 |
42767603 ps |
| T832 |
/workspace/coverage/default/4.clkmgr_frequency_timeout.132813664 |
|
|
Feb 28 06:08:54 PM PST 24 |
Feb 28 06:08:57 PM PST 24 |
671582284 ps |
| T833 |
/workspace/coverage/default/2.clkmgr_extclk.3742240877 |
|
|
Feb 28 06:08:53 PM PST 24 |
Feb 28 06:08:54 PM PST 24 |
142117246 ps |
| T834 |
/workspace/coverage/default/27.clkmgr_peri.710864798 |
|
|
Feb 28 06:10:10 PM PST 24 |
Feb 28 06:10:11 PM PST 24 |
12824361 ps |
| T835 |
/workspace/coverage/default/25.clkmgr_alert_test.4200549749 |
|
|
Feb 28 06:10:05 PM PST 24 |
Feb 28 06:10:06 PM PST 24 |
15889359 ps |
| T836 |
/workspace/coverage/default/42.clkmgr_smoke.3738564846 |
|
|
Feb 28 06:10:53 PM PST 24 |
Feb 28 06:10:55 PM PST 24 |
228146057 ps |
| T837 |
/workspace/coverage/default/20.clkmgr_alert_test.1820797735 |
|
|
Feb 28 06:09:54 PM PST 24 |
Feb 28 06:09:55 PM PST 24 |
50246140 ps |
| T838 |
/workspace/coverage/default/33.clkmgr_clk_status.2979379337 |
|
|
Feb 28 06:10:28 PM PST 24 |
Feb 28 06:10:29 PM PST 24 |
47042281 ps |
| T839 |
/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.3770517474 |
|
|
Feb 28 06:10:50 PM PST 24 |
Feb 28 06:18:26 PM PST 24 |
23944613578 ps |
| T840 |
/workspace/coverage/default/9.clkmgr_stress_all.1797133718 |
|
|
Feb 28 06:09:20 PM PST 24 |
Feb 28 06:09:42 PM PST 24 |
2898233971 ps |
| T841 |
/workspace/coverage/default/13.clkmgr_div_intersig_mubi.2949848735 |
|
|
Feb 28 06:09:30 PM PST 24 |
Feb 28 06:09:31 PM PST 24 |
40327338 ps |
| T842 |
/workspace/coverage/default/33.clkmgr_trans.3850430945 |
|
|
Feb 28 06:10:27 PM PST 24 |
Feb 28 06:10:28 PM PST 24 |
92108009 ps |
| T843 |
/workspace/coverage/default/32.clkmgr_stress_all.1823641206 |
|
|
Feb 28 06:10:27 PM PST 24 |
Feb 28 06:10:51 PM PST 24 |
5606722915 ps |
| T844 |
/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1292779405 |
|
|
Feb 28 06:09:52 PM PST 24 |
Feb 28 06:09:53 PM PST 24 |
66614974 ps |
| T845 |
/workspace/coverage/default/32.clkmgr_frequency_timeout.1260280915 |
|
|
Feb 28 06:10:19 PM PST 24 |
Feb 28 06:10:22 PM PST 24 |
521919493 ps |
| T846 |
/workspace/coverage/default/30.clkmgr_stress_all.1757793361 |
|
|
Feb 28 06:10:18 PM PST 24 |
Feb 28 06:10:33 PM PST 24 |
3215753304 ps |
| T847 |
/workspace/coverage/default/49.clkmgr_frequency.774219868 |
|
|
Feb 28 06:11:06 PM PST 24 |
Feb 28 06:11:18 PM PST 24 |
2495390645 ps |
| T848 |
/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1819572406 |
|
|
Feb 28 06:10:45 PM PST 24 |
Feb 28 06:10:46 PM PST 24 |
43658298 ps |
| T849 |
/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1128245681 |
|
|
Feb 28 06:09:46 PM PST 24 |
Feb 28 06:09:48 PM PST 24 |
25439675 ps |
| T850 |
/workspace/coverage/default/36.clkmgr_regwen.880499635 |
|
|
Feb 28 06:10:47 PM PST 24 |
Feb 28 06:10:51 PM PST 24 |
826078419 ps |
| T851 |
/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2041917902 |
|
|
Feb 28 06:10:05 PM PST 24 |
Feb 28 06:10:06 PM PST 24 |
18635821 ps |
| T852 |
/workspace/coverage/default/27.clkmgr_regwen.1626175269 |
|
|
Feb 28 06:10:13 PM PST 24 |
Feb 28 06:10:16 PM PST 24 |
780019644 ps |
| T853 |
/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.4016890373 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:47:59 PM PST 24 |
20688666 ps |
| T52 |
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.4068668569 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:26 PM PST 24 |
247474852 ps |
| T53 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2893014673 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
103048028 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4226188340 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:02 PM PST 24 |
24296626 ps |
| T54 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1088758056 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:12 PM PST 24 |
200183158 ps |
| T854 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.363095594 |
|
|
Feb 28 05:47:59 PM PST 24 |
Feb 28 05:48:02 PM PST 24 |
388182247 ps |
| T855 |
/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.692787937 |
|
|
Feb 28 05:47:56 PM PST 24 |
Feb 28 05:47:57 PM PST 24 |
11767389 ps |
| T86 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2294373925 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:22 PM PST 24 |
189650686 ps |
| T856 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2366888981 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
5253021586 ps |
| T857 |
/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3033221761 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:15 PM PST 24 |
17243702 ps |
| T858 |
/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.222638471 |
|
|
Feb 28 05:47:57 PM PST 24 |
Feb 28 05:47:58 PM PST 24 |
16948608 ps |
| T859 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1198088292 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
215135411 ps |
| T70 |
/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.782560 |
|
|
Feb 28 05:48:09 PM PST 24 |
Feb 28 05:48:10 PM PST 24 |
33041318 ps |
| T87 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4117903145 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:21 PM PST 24 |
293589623 ps |
| T860 |
/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3705706942 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
319337856 ps |
| T861 |
/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3801144206 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
27205319 ps |
| T58 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2582121627 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:21 PM PST 24 |
99270550 ps |
| T71 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.2027030467 |
|
|
Feb 28 05:48:08 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
36610173 ps |
| T88 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3059517138 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
65971510 ps |
| T55 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.4111456663 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:22 PM PST 24 |
128572314 ps |
| T56 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.892544363 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
194136336 ps |
| T862 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.406566882 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
207575269 ps |
| T863 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.310608429 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
25926039 ps |
| T72 |
/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3713496351 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
37108955 ps |
| T59 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2918153100 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
105769023 ps |
| T57 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1178429050 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
116408502 ps |
| T864 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3403277460 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
71857723 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3365993641 |
|
|
Feb 28 05:48:01 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
247057575 ps |
| T93 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4099690507 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
194191995 ps |
| T865 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3071885603 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
250156311 ps |
| T866 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.1961380643 |
|
|
Feb 28 05:47:59 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
991950874 ps |
| T867 |
/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2258404956 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
31394845 ps |
| T868 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1348081451 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
93215689 ps |
| T89 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1159832897 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
508691808 ps |
| T869 |
/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1358074603 |
|
|
Feb 28 05:48:25 PM PST 24 |
Feb 28 05:48:26 PM PST 24 |
31285191 ps |
| T870 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1972829354 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:16 PM PST 24 |
16390154 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3944344525 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
244434717 ps |
| T871 |
/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2411860235 |
|
|
Feb 28 05:48:32 PM PST 24 |
Feb 28 05:48:34 PM PST 24 |
13541165 ps |
| T872 |
/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.4227981384 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
16733421 ps |
| T74 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3351853119 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
254112974 ps |
| T873 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3252339943 |
|
|
Feb 28 05:48:21 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
69368549 ps |
| T874 |
/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1004110203 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
34793013 ps |
| T875 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2621750670 |
|
|
Feb 28 05:47:57 PM PST 24 |
Feb 28 05:47:59 PM PST 24 |
37759929 ps |
| T876 |
/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2886399394 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
35527010 ps |
| T95 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1445657468 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
139690508 ps |
| T94 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3520591336 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
157669364 ps |
| T877 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.4166276627 |
|
|
Feb 28 05:47:56 PM PST 24 |
Feb 28 05:48:01 PM PST 24 |
227638661 ps |
| T878 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1461494008 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
270758329 ps |
| T879 |
/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3613282841 |
|
|
Feb 28 05:48:27 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
13234753 ps |
| T880 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.952700809 |
|
|
Feb 28 05:48:01 PM PST 24 |
Feb 28 05:48:02 PM PST 24 |
58907130 ps |
| T881 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1159896381 |
|
|
Feb 28 05:48:02 PM PST 24 |
Feb 28 05:48:03 PM PST 24 |
34312454 ps |
| T882 |
/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1461197727 |
|
|
Feb 28 05:48:19 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
11250777 ps |
| T75 |
/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3341136874 |
|
|
Feb 28 05:48:29 PM PST 24 |
Feb 28 05:48:32 PM PST 24 |
24372892 ps |
| T883 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3920850059 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:48:00 PM PST 24 |
72480057 ps |
| T104 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.660528419 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
100824382 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2614183129 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
173272753 ps |
| T884 |
/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3251946576 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
39764006 ps |
| T885 |
/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3420301040 |
|
|
Feb 28 05:48:19 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
41008188 ps |
| T886 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.702836988 |
|
|
Feb 28 05:48:02 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
44599263 ps |
| T887 |
/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3988158339 |
|
|
Feb 28 05:48:02 PM PST 24 |
Feb 28 05:48:03 PM PST 24 |
13430779 ps |
| T888 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1375543651 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
44016031 ps |
| T889 |
/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1148210193 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:27 PM PST 24 |
75577584 ps |
| T890 |
/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1792258654 |
|
|
Feb 28 05:48:30 PM PST 24 |
Feb 28 05:48:33 PM PST 24 |
13195689 ps |
| T891 |
/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.207404796 |
|
|
Feb 28 05:48:29 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
16633545 ps |
| T892 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2032962529 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
88319362 ps |
| T893 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2378709327 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
27088902 ps |
| T894 |
/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1582314888 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
80275865 ps |
| T895 |
/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1615692401 |
|
|
Feb 28 05:48:22 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
59364351 ps |
| T896 |
/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3113089722 |
|
|
Feb 28 05:48:30 PM PST 24 |
Feb 28 05:48:33 PM PST 24 |
13542833 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1270985636 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:48:02 PM PST 24 |
409494967 ps |
| T897 |
/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2887211165 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
158101625 ps |
| T898 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2453890602 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
23391421 ps |
| T899 |
/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3666244189 |
|
|
Feb 28 05:48:15 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
43657155 ps |
| T900 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3480977763 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
1441013339 ps |
| T118 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.451240835 |
|
|
Feb 28 05:48:01 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
406374701 ps |
| T901 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1611387352 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:03 PM PST 24 |
91294654 ps |
| T902 |
/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3054829969 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
13375770 ps |
| T903 |
/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1155089012 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
100993390 ps |
| T904 |
/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2746488210 |
|
|
Feb 28 05:48:19 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
11633211 ps |
| T905 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.48095952 |
|
|
Feb 28 05:48:09 PM PST 24 |
Feb 28 05:48:14 PM PST 24 |
552876924 ps |
| T906 |
/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3206176880 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:16 PM PST 24 |
65518804 ps |
| T907 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1914120444 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
31875597 ps |
| T90 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2145361130 |
|
|
Feb 28 05:48:09 PM PST 24 |
Feb 28 05:48:11 PM PST 24 |
199319398 ps |
| T908 |
/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4133395810 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:27 PM PST 24 |
16736632 ps |
| T110 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3901345903 |
|
|
Feb 28 05:48:03 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
117814462 ps |
| T144 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.845804428 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
115080423 ps |
| T909 |
/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.594182658 |
|
|
Feb 28 05:48:12 PM PST 24 |
Feb 28 05:48:14 PM PST 24 |
22404027 ps |
| T910 |
/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3983022505 |
|
|
Feb 28 05:48:25 PM PST 24 |
Feb 28 05:48:27 PM PST 24 |
31478766 ps |
| T911 |
/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.536987201 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
14950646 ps |
| T111 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2172672471 |
|
|
Feb 28 05:48:02 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
219450238 ps |
| T912 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2017361745 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:48:01 PM PST 24 |
254897084 ps |
| T913 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1632782 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
14162316 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2406221198 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:13 PM PST 24 |
232311730 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.157568459 |
|
|
Feb 28 05:48:15 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
108448658 ps |
| T107 |
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.729933455 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:47:59 PM PST 24 |
124558675 ps |
| T108 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1055652868 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:10 PM PST 24 |
268403490 ps |
| T914 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.798380106 |
|
|
Feb 28 05:48:03 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
77145901 ps |
| T915 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2066141360 |
|
|
Feb 28 05:47:59 PM PST 24 |
Feb 28 05:48:00 PM PST 24 |
18254573 ps |
| T916 |
/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.496843840 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:11 PM PST 24 |
170157226 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.464148424 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
155105962 ps |
| T917 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.479841092 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
22521494 ps |
| T918 |
/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4112928448 |
|
|
Feb 28 05:47:56 PM PST 24 |
Feb 28 05:47:58 PM PST 24 |
94337383 ps |
| T919 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1014258574 |
|
|
Feb 28 05:48:12 PM PST 24 |
Feb 28 05:48:15 PM PST 24 |
30224462 ps |
| T920 |
/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3055798649 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
12794831 ps |
| T921 |
/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.603176413 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
38029648 ps |
| T922 |
/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.753077736 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
48751392 ps |
| T923 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2393127465 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
94706065 ps |
| T924 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1626765831 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:12 PM PST 24 |
114755599 ps |
| T925 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.776958181 |
|
|
Feb 28 05:47:54 PM PST 24 |
Feb 28 05:47:55 PM PST 24 |
19184468 ps |
| T926 |
/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3223159248 |
|
|
Feb 28 05:48:12 PM PST 24 |
Feb 28 05:48:14 PM PST 24 |
36927809 ps |
| T927 |
/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3719936945 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
11353741 ps |
| T928 |
/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3643046821 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
34332576 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.438655332 |
|
|
Feb 28 05:48:29 PM PST 24 |
Feb 28 05:48:33 PM PST 24 |
105922924 ps |
| T929 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1300816782 |
|
|
Feb 28 05:47:57 PM PST 24 |
Feb 28 05:47:57 PM PST 24 |
45105080 ps |
| T930 |
/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2385664634 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
33538654 ps |
| T931 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1124017807 |
|
|
Feb 28 05:48:11 PM PST 24 |
Feb 28 05:48:12 PM PST 24 |
74738303 ps |
| T932 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1479265213 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:21 PM PST 24 |
18904283 ps |
| T933 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1297281905 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:10 PM PST 24 |
621450649 ps |
| T934 |
/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3416291951 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:11 PM PST 24 |
32332935 ps |
| T935 |
/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3164018284 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
219085722 ps |
| T936 |
/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1833569681 |
|
|
Feb 28 05:48:26 PM PST 24 |
Feb 28 05:48:27 PM PST 24 |
33829777 ps |
| T937 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3292761337 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:15 PM PST 24 |
51202915 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3595819177 |
|
|
Feb 28 05:47:56 PM PST 24 |
Feb 28 05:47:57 PM PST 24 |
83615481 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2473763101 |
|
|
Feb 28 05:47:59 PM PST 24 |
Feb 28 05:48:01 PM PST 24 |
48226338 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2741228840 |
|
|
Feb 28 05:47:59 PM PST 24 |
Feb 28 05:48:01 PM PST 24 |
17570642 ps |
| T940 |
/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3229496005 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
18276966 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1467096157 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
112295213 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2621804826 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
110400442 ps |
| T98 |
/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.452670318 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:26 PM PST 24 |
51180816 ps |
| T942 |
/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3090438964 |
|
|
Feb 28 05:48:27 PM PST 24 |
Feb 28 05:48:29 PM PST 24 |
14282065 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3891739580 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
62006292 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1729507701 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
507742543 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2364423997 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
52903984 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.554876356 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
347115757 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2211508821 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
383504616 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2000750222 |
|
|
Feb 28 05:48:09 PM PST 24 |
Feb 28 05:48:14 PM PST 24 |
862562040 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2258472024 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
51035897 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2525837181 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
70967447 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3830782181 |
|
|
Feb 28 05:48:03 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
124441987 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2009850886 |
|
|
Feb 28 05:47:55 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
1718619588 ps |
| T952 |
/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2658384369 |
|
|
Feb 28 05:48:33 PM PST 24 |
Feb 28 05:48:34 PM PST 24 |
46039590 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1691229119 |
|
|
Feb 28 05:48:27 PM PST 24 |
Feb 28 05:48:30 PM PST 24 |
14988164 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2184801790 |
|
|
Feb 28 05:48:11 PM PST 24 |
Feb 28 05:48:12 PM PST 24 |
50419555 ps |
| T955 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1084649027 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:08 PM PST 24 |
52452084 ps |
| T956 |
/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3730294351 |
|
|
Feb 28 05:48:24 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
87426083 ps |
| T957 |
/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.856383542 |
|
|
Feb 28 05:48:33 PM PST 24 |
Feb 28 05:48:34 PM PST 24 |
17792771 ps |
| T113 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.142428974 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
55043936 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2193312779 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
18740483 ps |
| T959 |
/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.983944922 |
|
|
Feb 28 05:48:30 PM PST 24 |
Feb 28 05:48:34 PM PST 24 |
33660826 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2667186312 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
35603299 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.848672858 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
32513840 ps |
| T962 |
/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3367773552 |
|
|
Feb 28 05:48:33 PM PST 24 |
Feb 28 05:48:34 PM PST 24 |
17091260 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1846487934 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
51916200 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1400465827 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
234938338 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2175156558 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:15 PM PST 24 |
84367698 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2774499388 |
|
|
Feb 28 05:48:25 PM PST 24 |
Feb 28 05:48:28 PM PST 24 |
158688037 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.4004468130 |
|
|
Feb 28 05:48:21 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
126604420 ps |
| T967 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2911201459 |
|
|
Feb 28 05:48:17 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
75076537 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.359896600 |
|
|
Feb 28 05:48:22 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
204795321 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3850606203 |
|
|
Feb 28 05:48:21 PM PST 24 |
Feb 28 05:48:23 PM PST 24 |
26819626 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1001115015 |
|
|
Feb 28 05:48:03 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
15746288 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1494329217 |
|
|
Feb 28 05:48:14 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
148143331 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3441611435 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
14382456 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.471409997 |
|
|
Feb 28 05:48:06 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
58726393 ps |
| T974 |
/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1636432945 |
|
|
Feb 28 05:48:30 PM PST 24 |
Feb 28 05:48:33 PM PST 24 |
11659134 ps |
| T975 |
/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1578582126 |
|
|
Feb 28 05:48:27 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
64651809 ps |
| T976 |
/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.898669881 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
82323330 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1844093920 |
|
|
Feb 28 05:48:08 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
173488691 ps |
| T978 |
/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3232566951 |
|
|
Feb 28 05:48:29 PM PST 24 |
Feb 28 05:48:32 PM PST 24 |
39895761 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3003373908 |
|
|
Feb 28 05:48:15 PM PST 24 |
Feb 28 05:48:17 PM PST 24 |
55129351 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1922119629 |
|
|
Feb 28 05:48:15 PM PST 24 |
Feb 28 05:48:18 PM PST 24 |
156449961 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2862095736 |
|
|
Feb 28 05:48:00 PM PST 24 |
Feb 28 05:48:02 PM PST 24 |
199654399 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.306853443 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:48:01 PM PST 24 |
144040021 ps |
| T982 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3441848920 |
|
|
Feb 28 05:48:10 PM PST 24 |
Feb 28 05:48:14 PM PST 24 |
222535665 ps |
| T983 |
/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.322770450 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
22939526 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2786846325 |
|
|
Feb 28 05:47:58 PM PST 24 |
Feb 28 05:48:00 PM PST 24 |
85915297 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.553921495 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:25 PM PST 24 |
50101944 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3278925358 |
|
|
Feb 28 05:48:05 PM PST 24 |
Feb 28 05:48:06 PM PST 24 |
30311229 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3335746132 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:22 PM PST 24 |
20973701 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.747065737 |
|
|
Feb 28 05:48:03 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
18871118 ps |
| T989 |
/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.776767721 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
29378745 ps |
| T990 |
/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1994458175 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:09 PM PST 24 |
77225245 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2296468549 |
|
|
Feb 28 05:48:23 PM PST 24 |
Feb 28 05:48:24 PM PST 24 |
15191598 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.4216189795 |
|
|
Feb 28 05:48:18 PM PST 24 |
Feb 28 05:48:19 PM PST 24 |
43117329 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3074705130 |
|
|
Feb 28 05:48:04 PM PST 24 |
Feb 28 05:48:05 PM PST 24 |
41021566 ps |
| T994 |
/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2687515017 |
|
|
Feb 28 05:48:28 PM PST 24 |
Feb 28 05:48:31 PM PST 24 |
14588316 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3559941074 |
|
|
Feb 28 05:48:19 PM PST 24 |
Feb 28 05:48:22 PM PST 24 |
158120755 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1041963050 |
|
|
Feb 28 05:48:12 PM PST 24 |
Feb 28 05:48:15 PM PST 24 |
249788456 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.723340595 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:07 PM PST 24 |
21880214 ps |
| T996 |
/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1390663522 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:21 PM PST 24 |
61012668 ps |
| T120 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3440230836 |
|
|
Feb 28 05:48:02 PM PST 24 |
Feb 28 05:48:04 PM PST 24 |
93289376 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3528455856 |
|
|
Feb 28 05:48:16 PM PST 24 |
Feb 28 05:48:20 PM PST 24 |
409241471 ps |
| T998 |
/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.998041859 |
|
|
Feb 28 05:48:29 PM PST 24 |
Feb 28 05:48:32 PM PST 24 |
21561940 ps |
| T999 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2609695387 |
|
|
Feb 28 05:48:07 PM PST 24 |
Feb 28 05:48:11 PM PST 24 |
152529483 ps |
| T1000 |
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1211447718 |
|
|
Feb 28 05:48:20 PM PST 24 |
Feb 28 05:48:21 PM PST 24 |
87874043 ps |