Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 315488974 1 T5 4816 T6 3148 T7 2724
auto[1] 400348 1 T23 640 T25 694 T1 932


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 315471262 1 T5 4816 T6 3092 T7 2724
auto[1] 418060 1 T6 56 T23 378 T25 576


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 315382428 1 T5 4816 T6 3058 T7 2724
auto[1] 506894 1 T6 90 T23 590 T25 892


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301529786 1 T5 4816 T6 242 T7 2724
auto[1] 14359536 1 T6 2906 T23 356 T25 1826


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 176560612 1 T5 4784 T6 2956 T7 2724
auto[1] 139328710 1 T5 32 T6 192 T23 670


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 162212714 1 T5 4784 T6 226 T7 2724
auto[0] auto[0] auto[0] auto[0] auto[1] 138933388 1 T5 32 T23 412 T24 2066
auto[0] auto[0] auto[0] auto[1] auto[0] 30568 1 T23 30 T1 28 T2 498
auto[0] auto[0] auto[0] auto[1] auto[1] 6986 1 T23 52 T25 8 T1 16
auto[0] auto[0] auto[1] auto[0] auto[0] 13724398 1 T6 2656 T23 134 T25 920
auto[0] auto[0] auto[1] auto[0] auto[1] 282596 1 T6 176 T25 56 T2 3000
auto[0] auto[0] auto[1] auto[1] auto[0] 51150 1 T23 26 T25 72 T1 44
auto[0] auto[0] auto[1] auto[1] auto[1] 12874 1 T25 16 T2 324 T109 80
auto[0] auto[1] auto[0] auto[0] auto[0] 74540 1 T23 12 T25 42 T2 30
auto[0] auto[1] auto[0] auto[0] auto[1] 1716 1 T23 68 T156 18 T157 6
auto[0] auto[1] auto[0] auto[1] auto[0] 10522 1 T23 66 T18 40 T109 62
auto[0] auto[1] auto[0] auto[1] auto[1] 3394 1 T23 64 T156 50 T157 72
auto[0] auto[1] auto[1] auto[0] auto[0] 10404 1 T25 10 T1 2 T2 472
auto[0] auto[1] auto[1] auto[0] auto[1] 2318 1 T2 18 T109 10 T84 26
auto[0] auto[1] auto[1] auto[1] auto[0] 20366 1 T25 44 T1 58 T2 950
auto[0] auto[1] auto[1] auto[1] auto[1] 4494 1 T2 66 T109 46 T156 50
auto[1] auto[0] auto[0] auto[0] auto[0] 76940 1 T23 144 T4 664 T1 16
auto[1] auto[0] auto[0] auto[0] auto[1] 4074 1 T2 6 T21 2 T109 18
auto[1] auto[0] auto[0] auto[1] auto[0] 30574 1 T23 176 T1 156 T2 498
auto[1] auto[0] auto[0] auto[1] auto[1] 7188 1 T2 94 T21 44 T109 42
auto[1] auto[0] auto[1] auto[0] auto[0] 26556 1 T6 26 T23 20 T25 124
auto[1] auto[0] auto[1] auto[0] auto[1] 7262 1 T6 8 T25 18 T2 200
auto[1] auto[0] auto[1] auto[1] auto[0] 50434 1 T23 82 T25 208 T1 242
auto[1] auto[0] auto[1] auto[1] auto[1] 13560 1 T25 62 T2 164 T110 54
auto[1] auto[1] auto[0] auto[0] auto[0] 72614 1 T6 16 T25 98 T2 1050
auto[1] auto[1] auto[0] auto[0] auto[1] 5992 1 T23 20 T25 4 T1 20
auto[1] auto[1] auto[0] auto[1] auto[0] 47232 1 T2 1308 T21 172 T109 60
auto[1] auto[1] auto[0] auto[1] auto[1] 11344 1 T23 54 T25 82 T1 162
auto[1] auto[1] auto[1] auto[0] auto[0] 42256 1 T6 32 T23 4 T25 94
auto[1] auto[1] auto[1] auto[0] auto[1] 11206 1 T6 8 T2 476 T18 20
auto[1] auto[1] auto[1] auto[1] auto[0] 79344 1 T23 90 T25 202 T1 226
auto[1] auto[1] auto[1] auto[1] auto[1] 20318 1 T2 918 T109 38 T80 44

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