Summary for Variable byp_req_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for byp_req_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309720828 |
1 |
|
|
T5 |
2228 |
|
T6 |
2668 |
|
T7 |
3620 |
auto[1] |
404220 |
1 |
|
|
T5 |
222 |
|
T6 |
382 |
|
T7 |
662 |
Summary for Variable csr_low_speed_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_low_speed_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309750824 |
1 |
|
|
T5 |
2128 |
|
T6 |
2712 |
|
T7 |
4002 |
auto[1] |
374224 |
1 |
|
|
T5 |
322 |
|
T6 |
338 |
|
T7 |
280 |
Summary for Variable csr_sel_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_sel_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
309636228 |
1 |
|
|
T5 |
2124 |
|
T6 |
2680 |
|
T7 |
3728 |
auto[1] |
488820 |
1 |
|
|
T5 |
326 |
|
T6 |
370 |
|
T7 |
554 |
Summary for Variable hw_debug_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for hw_debug_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
294627622 |
1 |
|
|
T5 |
2450 |
|
T6 |
412 |
|
T7 |
3992 |
auto[1] |
15497426 |
1 |
|
|
T6 |
2638 |
|
T7 |
290 |
|
T2 |
1454 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
182301290 |
1 |
|
|
T5 |
2288 |
|
T6 |
764 |
|
T7 |
4158 |
auto[1] |
127823758 |
1 |
|
|
T5 |
162 |
|
T6 |
2286 |
|
T7 |
124 |
Summary for Cross extclk_cross
Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
32 |
0 |
32 |
100.00 |
|
Automatically Generated Cross Bins for extclk_cross
Bins
csr_sel_cp | csr_low_speed_cp | hw_debug_en_cp | byp_req_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
169380458 |
1 |
|
|
T5 |
1916 |
|
T6 |
172 |
|
T7 |
3144 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
124935024 |
1 |
|
|
T5 |
118 |
|
T6 |
20 |
|
T7 |
112 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
29190 |
1 |
|
|
T6 |
26 |
|
T7 |
210 |
|
T2 |
14 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
7206 |
1 |
|
|
T2 |
2 |
|
T11 |
104 |
|
T31 |
60 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
12362064 |
1 |
|
|
T6 |
228 |
|
T7 |
168 |
|
T2 |
1240 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
2774920 |
1 |
|
|
T6 |
2094 |
|
T28 |
234 |
|
T47 |
68 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
50872 |
1 |
|
|
T6 |
20 |
|
T7 |
10 |
|
T2 |
30 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
12954 |
1 |
|
|
T6 |
22 |
|
T28 |
4 |
|
T47 |
4 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
28954 |
1 |
|
|
T5 |
14 |
|
T7 |
20 |
|
T4 |
1080 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
1270 |
1 |
|
|
T132 |
2 |
|
T140 |
2 |
|
T25 |
22 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
12302 |
1 |
|
|
T5 |
76 |
|
T7 |
64 |
|
T2 |
48 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
2664 |
1 |
|
|
T132 |
54 |
|
T140 |
62 |
|
T25 |
52 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
10664 |
1 |
|
|
T2 |
10 |
|
T47 |
24 |
|
T11 |
98 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
2514 |
1 |
|
|
T6 |
4 |
|
T11 |
8 |
|
T35 |
12 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
20156 |
1 |
|
|
T2 |
64 |
|
T47 |
100 |
|
T11 |
418 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
5016 |
1 |
|
|
T6 |
94 |
|
T35 |
70 |
|
T13 |
60 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
50622 |
1 |
|
|
T5 |
50 |
|
T7 |
68 |
|
T2 |
18 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
3938 |
1 |
|
|
T5 |
44 |
|
T2 |
26 |
|
T11 |
44 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
31804 |
1 |
|
|
T7 |
178 |
|
T2 |
92 |
|
T28 |
42 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
7854 |
1 |
|
|
T2 |
56 |
|
T11 |
36 |
|
T12 |
52 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
29990 |
1 |
|
|
T6 |
14 |
|
T7 |
52 |
|
T2 |
8 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
7604 |
1 |
|
|
T6 |
52 |
|
T28 |
2 |
|
T47 |
2 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
52556 |
1 |
|
|
T6 |
64 |
|
T7 |
60 |
|
T47 |
42 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
13768 |
1 |
|
|
T28 |
44 |
|
T47 |
50 |
|
T11 |
152 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
73920 |
1 |
|
|
T5 |
86 |
|
T6 |
38 |
|
T7 |
44 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
5204 |
1 |
|
|
T7 |
12 |
|
T2 |
20 |
|
T18 |
30 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
45220 |
1 |
|
|
T5 |
146 |
|
T6 |
156 |
|
T7 |
140 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
11992 |
1 |
|
|
T2 |
52 |
|
T18 |
86 |
|
T11 |
116 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
42300 |
1 |
|
|
T6 |
46 |
|
T2 |
8 |
|
T28 |
42 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
11382 |
1 |
|
|
T28 |
30 |
|
T11 |
126 |
|
T12 |
58 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
80218 |
1 |
|
|
T2 |
94 |
|
T28 |
140 |
|
T47 |
42 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
20448 |
1 |
|
|
T11 |
348 |
|
T12 |
96 |
|
T13 |
346 |