Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286182198 1 T5 3682 T6 1576 T7 3000
auto[1] 407830 1 T5 206 T6 258 T29 920


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286167744 1 T5 3704 T6 1662 T7 3000
auto[1] 422284 1 T5 184 T6 172 T29 658


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286120926 1 T5 3576 T6 1662 T7 3000
auto[1] 469102 1 T5 312 T6 172 T29 826


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 273993218 1 T5 440 T6 1834 T7 3000
auto[1] 12596810 1 T5 3448 T29 1714 T1 3908


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168787610 1 T5 910 T6 1834 T7 3000
auto[1] 117802418 1 T5 2978 T26 2176 T27 3156


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 156459784 1 T5 128 T6 1540 T7 3000
auto[0] auto[0] auto[0] auto[0] auto[1] 117206108 1 T5 204 T26 2176 T27 3156
auto[0] auto[0] auto[0] auto[1] auto[0] 28896 1 T6 122 T29 38 T1 40
auto[0] auto[0] auto[0] auto[1] auto[1] 8078 1 T1 14 T22 46 T41 20
auto[0] auto[0] auto[1] auto[0] auto[0] 11751262 1 T5 584 T29 594 T1 2204
auto[0] auto[0] auto[1] auto[0] auto[1] 479560 1 T5 2638 T29 228 T1 472
auto[0] auto[0] auto[1] auto[1] auto[0] 51264 1 T5 10 T29 134 T1 260
auto[0] auto[0] auto[1] auto[1] auto[1] 13006 1 T5 12 T29 126 T1 28
auto[0] auto[1] auto[0] auto[0] auto[0] 65926 1 T29 8 T1 48 T19 16
auto[0] auto[1] auto[0] auto[0] auto[1] 1408 1 T22 2 T41 10 T11 8
auto[0] auto[1] auto[0] auto[1] auto[0] 11426 1 T29 74 T1 48 T23 76
auto[0] auto[1] auto[0] auto[1] auto[1] 3728 1 T22 42 T41 62 T11 58
auto[0] auto[1] auto[1] auto[0] auto[0] 11430 1 T1 22 T21 2 T22 2
auto[0] auto[1] auto[1] auto[0] auto[1] 2528 1 T19 10 T11 8 T168 16
auto[0] auto[1] auto[1] auto[1] auto[0] 21788 1 T1 54 T21 46 T22 44
auto[0] auto[1] auto[1] auto[1] auto[1] 4734 1 T19 44 T168 58 T161 58
auto[1] auto[0] auto[0] auto[0] auto[0] 25274 1 T5 16 T29 64 T1 10
auto[1] auto[0] auto[0] auto[0] auto[1] 3846 1 T5 8 T1 18 T19 4
auto[1] auto[0] auto[0] auto[1] auto[0] 28962 1 T5 40 T41 172 T166 142
auto[1] auto[0] auto[0] auto[1] auto[1] 7884 1 T1 62 T19 58 T131 62
auto[1] auto[0] auto[1] auto[0] auto[0] 30882 1 T5 10 T29 18 T1 102
auto[1] auto[0] auto[1] auto[0] auto[1] 7390 1 T5 8 T29 14 T1 24
auto[1] auto[0] auto[1] auto[1] auto[0] 52028 1 T5 46 T29 68 T1 260
auto[1] auto[0] auto[1] auto[1] auto[1] 13520 1 T29 86 T1 80 T22 38
auto[1] auto[1] auto[0] auto[0] auto[0] 75220 1 T6 36 T29 8 T1 30
auto[1] auto[1] auto[0] auto[0] auto[1] 6282 1 T5 8 T29 52 T1 4
auto[1] auto[1] auto[0] auto[1] auto[0] 49574 1 T6 136 T29 70 T1 110
auto[1] auto[1] auto[0] auto[1] auto[1] 10822 1 T5 36 T1 60 T131 54
auto[1] auto[1] auto[1] auto[0] auto[0] 43662 1 T5 76 T29 118 T1 104
auto[1] auto[1] auto[1] auto[0] auto[1] 11636 1 T5 2 T29 4 T1 40
auto[1] auto[1] auto[1] auto[1] auto[0] 80232 1 T29 240 T1 186 T19 278
auto[1] auto[1] auto[1] auto[1] auto[1] 21888 1 T5 62 T29 84 T1 72

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