| T795 |
/workspace/coverage/default/2.clkmgr_div_intersig_mubi.2302627354 |
|
|
Mar 05 02:02:10 PM PST 24 |
Mar 05 02:02:11 PM PST 24 |
48172078 ps |
| T796 |
/workspace/coverage/default/47.clkmgr_alert_test.898375923 |
|
|
Mar 05 02:05:47 PM PST 24 |
Mar 05 02:05:48 PM PST 24 |
33502018 ps |
| T797 |
/workspace/coverage/default/4.clkmgr_alert_test.3665079634 |
|
|
Mar 05 02:02:25 PM PST 24 |
Mar 05 02:02:26 PM PST 24 |
17532960 ps |
| T798 |
/workspace/coverage/default/8.clkmgr_regwen.4005920279 |
|
|
Mar 05 02:02:47 PM PST 24 |
Mar 05 02:02:50 PM PST 24 |
486365363 ps |
| T799 |
/workspace/coverage/default/17.clkmgr_frequency_timeout.413164862 |
|
|
Mar 05 02:03:33 PM PST 24 |
Mar 05 02:03:46 PM PST 24 |
2419222616 ps |
| T800 |
/workspace/coverage/default/7.clkmgr_div_intersig_mubi.1828564630 |
|
|
Mar 05 02:02:40 PM PST 24 |
Mar 05 02:02:42 PM PST 24 |
59913670 ps |
| T801 |
/workspace/coverage/default/32.clkmgr_peri.1552962585 |
|
|
Mar 05 02:04:36 PM PST 24 |
Mar 05 02:04:37 PM PST 24 |
44865048 ps |
| T802 |
/workspace/coverage/default/42.clkmgr_regwen.3616441319 |
|
|
Mar 05 02:05:27 PM PST 24 |
Mar 05 02:05:34 PM PST 24 |
940658897 ps |
| T803 |
/workspace/coverage/default/49.clkmgr_trans.2351642353 |
|
|
Mar 05 02:05:56 PM PST 24 |
Mar 05 02:05:58 PM PST 24 |
47586957 ps |
| T804 |
/workspace/coverage/default/17.clkmgr_extclk.228742154 |
|
|
Mar 05 02:03:29 PM PST 24 |
Mar 05 02:03:30 PM PST 24 |
41657384 ps |
| T805 |
/workspace/coverage/default/36.clkmgr_alert_test.1174164783 |
|
|
Mar 05 02:05:03 PM PST 24 |
Mar 05 02:05:03 PM PST 24 |
15774123 ps |
| T806 |
/workspace/coverage/default/26.clkmgr_peri.175172788 |
|
|
Mar 05 02:04:08 PM PST 24 |
Mar 05 02:04:09 PM PST 24 |
30702793 ps |
| T807 |
/workspace/coverage/default/5.clkmgr_peri.825497096 |
|
|
Mar 05 02:02:28 PM PST 24 |
Mar 05 02:02:30 PM PST 24 |
49238431 ps |
| T808 |
/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1447796282 |
|
|
Mar 05 02:05:57 PM PST 24 |
Mar 05 02:05:59 PM PST 24 |
31634666 ps |
| T809 |
/workspace/coverage/default/11.clkmgr_clk_status.145746905 |
|
|
Mar 05 02:03:10 PM PST 24 |
Mar 05 02:03:11 PM PST 24 |
24152861 ps |
| T810 |
/workspace/coverage/default/18.clkmgr_smoke.1498153260 |
|
|
Mar 05 02:03:32 PM PST 24 |
Mar 05 02:03:33 PM PST 24 |
20062985 ps |
| T811 |
/workspace/coverage/default/36.clkmgr_peri.3376709164 |
|
|
Mar 05 02:04:53 PM PST 24 |
Mar 05 02:04:55 PM PST 24 |
24437930 ps |
| T812 |
/workspace/coverage/default/4.clkmgr_regwen.1687913264 |
|
|
Mar 05 02:02:26 PM PST 24 |
Mar 05 02:02:28 PM PST 24 |
281453436 ps |
| T813 |
/workspace/coverage/default/0.clkmgr_stress_all.3972756350 |
|
|
Mar 05 02:01:43 PM PST 24 |
Mar 05 02:01:59 PM PST 24 |
2248427973 ps |
| T814 |
/workspace/coverage/default/6.clkmgr_peri.4137992313 |
|
|
Mar 05 02:02:39 PM PST 24 |
Mar 05 02:02:40 PM PST 24 |
13964880 ps |
| T815 |
/workspace/coverage/default/11.clkmgr_trans.4123618790 |
|
|
Mar 05 02:03:04 PM PST 24 |
Mar 05 02:03:05 PM PST 24 |
18136513 ps |
| T816 |
/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1410753552 |
|
|
Mar 05 02:03:31 PM PST 24 |
Mar 05 02:03:32 PM PST 24 |
32207126 ps |
| T817 |
/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.2134806978 |
|
|
Mar 05 02:03:10 PM PST 24 |
Mar 05 02:08:27 PM PST 24 |
17320673449 ps |
| T818 |
/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3302535091 |
|
|
Mar 05 02:02:49 PM PST 24 |
Mar 05 02:02:50 PM PST 24 |
24882646 ps |
| T819 |
/workspace/coverage/default/8.clkmgr_smoke.3097518714 |
|
|
Mar 05 02:02:37 PM PST 24 |
Mar 05 02:02:39 PM PST 24 |
273806302 ps |
| T820 |
/workspace/coverage/default/8.clkmgr_div_intersig_mubi.1680687475 |
|
|
Mar 05 02:02:45 PM PST 24 |
Mar 05 02:02:47 PM PST 24 |
90548777 ps |
| T821 |
/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3442445145 |
|
|
Mar 05 02:05:45 PM PST 24 |
Mar 05 02:05:46 PM PST 24 |
15435913 ps |
| T822 |
/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1253762146 |
|
|
Mar 05 02:04:36 PM PST 24 |
Mar 05 02:04:37 PM PST 24 |
31356897 ps |
| T823 |
/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3086884122 |
|
|
Mar 05 02:03:53 PM PST 24 |
Mar 05 02:03:53 PM PST 24 |
24121945 ps |
| T824 |
/workspace/coverage/default/45.clkmgr_extclk.556441576 |
|
|
Mar 05 02:05:39 PM PST 24 |
Mar 05 02:05:40 PM PST 24 |
25132264 ps |
| T825 |
/workspace/coverage/default/4.clkmgr_stress_all.1296504108 |
|
|
Mar 05 02:02:29 PM PST 24 |
Mar 05 02:03:43 PM PST 24 |
10364252603 ps |
| T826 |
/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.722318056 |
|
|
Mar 05 02:02:28 PM PST 24 |
Mar 05 02:13:46 PM PST 24 |
45733729560 ps |
| T827 |
/workspace/coverage/default/33.clkmgr_clk_status.1402008435 |
|
|
Mar 05 02:04:47 PM PST 24 |
Mar 05 02:04:48 PM PST 24 |
17630617 ps |
| T828 |
/workspace/coverage/default/6.clkmgr_extclk.539761182 |
|
|
Mar 05 02:02:40 PM PST 24 |
Mar 05 02:02:41 PM PST 24 |
78414161 ps |
| T829 |
/workspace/coverage/default/18.clkmgr_extclk.120739773 |
|
|
Mar 05 02:03:32 PM PST 24 |
Mar 05 02:03:33 PM PST 24 |
129013246 ps |
| T830 |
/workspace/coverage/default/36.clkmgr_extclk.3770056614 |
|
|
Mar 05 02:04:51 PM PST 24 |
Mar 05 02:04:52 PM PST 24 |
55468985 ps |
| T831 |
/workspace/coverage/default/12.clkmgr_peri.1826313884 |
|
|
Mar 05 02:03:03 PM PST 24 |
Mar 05 02:03:04 PM PST 24 |
37917516 ps |
| T832 |
/workspace/coverage/default/1.clkmgr_frequency_timeout.3701478588 |
|
|
Mar 05 02:01:52 PM PST 24 |
Mar 05 02:02:09 PM PST 24 |
2300107393 ps |
| T833 |
/workspace/coverage/default/40.clkmgr_clk_status.4262505568 |
|
|
Mar 05 02:05:19 PM PST 24 |
Mar 05 02:05:20 PM PST 24 |
19925343 ps |
| T834 |
/workspace/coverage/default/37.clkmgr_regwen.106911442 |
|
|
Mar 05 02:04:59 PM PST 24 |
Mar 05 02:05:07 PM PST 24 |
1364581974 ps |
| T835 |
/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3300143514 |
|
|
Mar 05 02:01:53 PM PST 24 |
Mar 05 02:01:54 PM PST 24 |
17681639 ps |
| T836 |
/workspace/coverage/default/40.clkmgr_alert_test.2524294743 |
|
|
Mar 05 02:05:19 PM PST 24 |
Mar 05 02:05:20 PM PST 24 |
16202660 ps |
| T837 |
/workspace/coverage/default/24.clkmgr_regwen.1089366002 |
|
|
Mar 05 02:04:03 PM PST 24 |
Mar 05 02:04:08 PM PST 24 |
812683541 ps |
| T838 |
/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.27220285 |
|
|
Mar 05 02:03:31 PM PST 24 |
Mar 05 02:09:24 PM PST 24 |
56793609314 ps |
| T839 |
/workspace/coverage/default/36.clkmgr_smoke.2897905916 |
|
|
Mar 05 02:04:51 PM PST 24 |
Mar 05 02:04:53 PM PST 24 |
44259578 ps |
| T840 |
/workspace/coverage/default/47.clkmgr_peri.2357735865 |
|
|
Mar 05 02:05:46 PM PST 24 |
Mar 05 02:05:47 PM PST 24 |
20492706 ps |
| T841 |
/workspace/coverage/default/49.clkmgr_alert_test.2232172591 |
|
|
Mar 05 02:05:56 PM PST 24 |
Mar 05 02:05:57 PM PST 24 |
105380447 ps |
| T842 |
/workspace/coverage/default/17.clkmgr_trans.2582407479 |
|
|
Mar 05 02:03:30 PM PST 24 |
Mar 05 02:03:31 PM PST 24 |
59092475 ps |
| T843 |
/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3599183091 |
|
|
Mar 05 02:03:06 PM PST 24 |
Mar 05 02:03:07 PM PST 24 |
80592626 ps |
| T844 |
/workspace/coverage/default/6.clkmgr_stress_all.4234943526 |
|
|
Mar 05 02:02:37 PM PST 24 |
Mar 05 02:03:02 PM PST 24 |
6092763960 ps |
| T845 |
/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.49672251 |
|
|
Mar 05 02:03:23 PM PST 24 |
Mar 05 02:03:24 PM PST 24 |
54976428 ps |
| T846 |
/workspace/coverage/default/37.clkmgr_stress_all.2239038935 |
|
|
Mar 05 02:05:04 PM PST 24 |
Mar 05 02:05:28 PM PST 24 |
3754344399 ps |
| T847 |
/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2907095813 |
|
|
Mar 05 02:02:08 PM PST 24 |
Mar 05 02:02:10 PM PST 24 |
59008155 ps |
| T848 |
/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2391632249 |
|
|
Mar 05 12:42:57 PM PST 24 |
Mar 05 12:42:58 PM PST 24 |
15094758 ps |
| T849 |
/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.697963945 |
|
|
Mar 05 12:43:06 PM PST 24 |
Mar 05 12:43:07 PM PST 24 |
37928487 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3986639921 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
36405771 ps |
| T850 |
/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.822303489 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
35313398 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.10356758 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:49 PM PST 24 |
27487131 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2516204971 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:45 PM PST 24 |
57961275 ps |
| T851 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.4097095968 |
|
|
Mar 05 12:42:55 PM PST 24 |
Mar 05 12:42:59 PM PST 24 |
392815519 ps |
| T852 |
/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3791088521 |
|
|
Mar 05 12:43:00 PM PST 24 |
Mar 05 12:43:01 PM PST 24 |
55024649 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.54719125 |
|
|
Mar 05 12:42:41 PM PST 24 |
Mar 05 12:42:42 PM PST 24 |
68949653 ps |
| T97 |
/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3718103388 |
|
|
Mar 05 12:43:05 PM PST 24 |
Mar 05 12:43:06 PM PST 24 |
30173900 ps |
| T853 |
/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1345998737 |
|
|
Mar 05 12:42:57 PM PST 24 |
Mar 05 12:42:58 PM PST 24 |
10675622 ps |
| T854 |
/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.712043409 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:33 PM PST 24 |
60961577 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.460545114 |
|
|
Mar 05 12:42:21 PM PST 24 |
Mar 05 12:42:24 PM PST 24 |
94552415 ps |
| T110 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3995317957 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
225695926 ps |
| T855 |
/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.4292169451 |
|
|
Mar 05 12:42:29 PM PST 24 |
Mar 05 12:42:30 PM PST 24 |
37544337 ps |
| T856 |
/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3672272370 |
|
|
Mar 05 12:42:55 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
39661238 ps |
| T857 |
/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.290004394 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
14832221 ps |
| T98 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2616433066 |
|
|
Mar 05 12:42:55 PM PST 24 |
Mar 05 12:43:01 PM PST 24 |
17772281 ps |
| T858 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2990290059 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:49 PM PST 24 |
267837145 ps |
| T859 |
/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.4024069508 |
|
|
Mar 05 12:43:11 PM PST 24 |
Mar 05 12:43:12 PM PST 24 |
24368946 ps |
| T111 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.737853732 |
|
|
Mar 05 12:42:44 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
97695971 ps |
| T99 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3328245783 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
24647947 ps |
| T860 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1942238617 |
|
|
Mar 05 12:42:42 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
560389027 ps |
| T861 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2854339750 |
|
|
Mar 05 12:42:39 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
611813279 ps |
| T862 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2017241468 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
15015599 ps |
| T863 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.406208384 |
|
|
Mar 05 12:42:56 PM PST 24 |
Mar 05 12:42:59 PM PST 24 |
182891731 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1910541841 |
|
|
Mar 05 12:42:36 PM PST 24 |
Mar 05 12:42:38 PM PST 24 |
302946502 ps |
| T864 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3903563291 |
|
|
Mar 05 12:42:27 PM PST 24 |
Mar 05 12:42:29 PM PST 24 |
83410939 ps |
| T865 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4208025580 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:51 PM PST 24 |
27484757 ps |
| T73 |
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.744382000 |
|
|
Mar 05 12:42:44 PM PST 24 |
Mar 05 12:42:53 PM PST 24 |
117971178 ps |
| T100 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.691420830 |
|
|
Mar 05 12:43:26 PM PST 24 |
Mar 05 12:43:27 PM PST 24 |
13140830 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1202617303 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:49 PM PST 24 |
83833136 ps |
| T866 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2536785657 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:45 PM PST 24 |
73768512 ps |
| T77 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2501660649 |
|
|
Mar 05 12:42:59 PM PST 24 |
Mar 05 12:43:01 PM PST 24 |
62017880 ps |
| T867 |
/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.61582346 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
21734355 ps |
| T868 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2662331559 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
32768086 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2409309562 |
|
|
Mar 05 12:42:27 PM PST 24 |
Mar 05 12:42:35 PM PST 24 |
132623777 ps |
| T869 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2413936380 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:06 PM PST 24 |
25090571 ps |
| T870 |
/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3656794736 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
42356712 ps |
| T871 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1324161497 |
|
|
Mar 05 12:42:59 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
834468261 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.888073684 |
|
|
Mar 05 12:43:01 PM PST 24 |
Mar 05 12:43:03 PM PST 24 |
194027297 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.781732576 |
|
|
Mar 05 12:42:38 PM PST 24 |
Mar 05 12:42:40 PM PST 24 |
93850587 ps |
| T145 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1471577498 |
|
|
Mar 05 12:42:51 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
84078696 ps |
| T872 |
/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.506918508 |
|
|
Mar 05 12:42:56 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
10619230 ps |
| T873 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2349505345 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
250969930 ps |
| T874 |
/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2104207157 |
|
|
Mar 05 12:43:11 PM PST 24 |
Mar 05 12:43:13 PM PST 24 |
48486244 ps |
| T875 |
/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.4219645438 |
|
|
Mar 05 12:43:11 PM PST 24 |
Mar 05 12:43:12 PM PST 24 |
15091273 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3741991172 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:32 PM PST 24 |
52199897 ps |
| T876 |
/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.990098443 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:32 PM PST 24 |
96238335 ps |
| T877 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2221271342 |
|
|
Mar 05 12:43:09 PM PST 24 |
Mar 05 12:43:09 PM PST 24 |
18573886 ps |
| T878 |
/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2918501103 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:43:00 PM PST 24 |
68979987 ps |
| T879 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2671682230 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:35 PM PST 24 |
35804009 ps |
| T880 |
/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.342651357 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:53 PM PST 24 |
20976425 ps |
| T115 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1077045396 |
|
|
Mar 05 12:42:40 PM PST 24 |
Mar 05 12:42:42 PM PST 24 |
104983159 ps |
| T78 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3975336663 |
|
|
Mar 05 12:42:42 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
184701624 ps |
| T881 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2510016806 |
|
|
Mar 05 12:42:39 PM PST 24 |
Mar 05 12:42:40 PM PST 24 |
105333408 ps |
| T882 |
/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3430937485 |
|
|
Mar 05 12:43:20 PM PST 24 |
Mar 05 12:43:21 PM PST 24 |
23026265 ps |
| T143 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3469557779 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
476539419 ps |
| T883 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1006265248 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:58 PM PST 24 |
229248472 ps |
| T884 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.3440887334 |
|
|
Mar 05 12:43:01 PM PST 24 |
Mar 05 12:43:03 PM PST 24 |
205039189 ps |
| T885 |
/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.268898352 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:04 PM PST 24 |
29808023 ps |
| T886 |
/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3242755587 |
|
|
Mar 05 12:43:12 PM PST 24 |
Mar 05 12:43:12 PM PST 24 |
23033250 ps |
| T887 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4158585649 |
|
|
Mar 05 12:42:35 PM PST 24 |
Mar 05 12:42:38 PM PST 24 |
176928900 ps |
| T888 |
/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.542438418 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
12504697 ps |
| T79 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.825589367 |
|
|
Mar 05 12:43:05 PM PST 24 |
Mar 05 12:43:08 PM PST 24 |
325705524 ps |
| T889 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3490434663 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
77554052 ps |
| T890 |
/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4127814389 |
|
|
Mar 05 12:43:10 PM PST 24 |
Mar 05 12:43:11 PM PST 24 |
59075969 ps |
| T891 |
/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3036830396 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
24710537 ps |
| T116 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1899013483 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
248936253 ps |
| T892 |
/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2401510793 |
|
|
Mar 05 12:43:05 PM PST 24 |
Mar 05 12:43:06 PM PST 24 |
25557274 ps |
| T893 |
/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.627639858 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:03 PM PST 24 |
41162579 ps |
| T894 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2375497910 |
|
|
Mar 05 12:42:44 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
197537332 ps |
| T895 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3644693392 |
|
|
Mar 05 12:43:01 PM PST 24 |
Mar 05 12:43:03 PM PST 24 |
46889495 ps |
| T896 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.63050828 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
32936430 ps |
| T137 |
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.196063503 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
408356297 ps |
| T138 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1655888726 |
|
|
Mar 05 12:42:50 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
330763142 ps |
| T897 |
/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1325112648 |
|
|
Mar 05 12:42:44 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
55340668 ps |
| T144 |
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3882688099 |
|
|
Mar 05 12:43:07 PM PST 24 |
Mar 05 12:43:09 PM PST 24 |
117580044 ps |
| T898 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.830276236 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:45 PM PST 24 |
141939964 ps |
| T899 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3906696160 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
55338350 ps |
| T146 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1519652448 |
|
|
Mar 05 12:42:35 PM PST 24 |
Mar 05 12:42:38 PM PST 24 |
303206870 ps |
| T900 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2360016347 |
|
|
Mar 05 12:42:39 PM PST 24 |
Mar 05 12:42:40 PM PST 24 |
93977368 ps |
| T901 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.649183313 |
|
|
Mar 05 12:42:41 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
213934236 ps |
| T902 |
/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.812701156 |
|
|
Mar 05 12:42:59 PM PST 24 |
Mar 05 12:43:01 PM PST 24 |
59679418 ps |
| T903 |
/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3258002691 |
|
|
Mar 05 12:42:56 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
85801472 ps |
| T904 |
/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.4278587500 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
14064716 ps |
| T905 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2943981415 |
|
|
Mar 05 12:43:13 PM PST 24 |
Mar 05 12:43:14 PM PST 24 |
18965526 ps |
| T906 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1082642869 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
30178245 ps |
| T907 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2245354948 |
|
|
Mar 05 12:42:29 PM PST 24 |
Mar 05 12:42:30 PM PST 24 |
44688468 ps |
| T908 |
/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3687871227 |
|
|
Mar 05 12:43:06 PM PST 24 |
Mar 05 12:43:07 PM PST 24 |
13050414 ps |
| T909 |
/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1788836938 |
|
|
Mar 05 12:42:41 PM PST 24 |
Mar 05 12:42:42 PM PST 24 |
23428233 ps |
| T139 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2295410047 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
124716892 ps |
| T910 |
/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.4101756012 |
|
|
Mar 05 12:43:15 PM PST 24 |
Mar 05 12:43:17 PM PST 24 |
15001327 ps |
| T911 |
/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1834024597 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
14581385 ps |
| T912 |
/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.751861910 |
|
|
Mar 05 12:42:59 PM PST 24 |
Mar 05 12:43:00 PM PST 24 |
146780617 ps |
| T913 |
/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2278868873 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
52537295 ps |
| T914 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2875134422 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
14400038 ps |
| T140 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3534186203 |
|
|
Mar 05 12:42:50 PM PST 24 |
Mar 05 12:42:53 PM PST 24 |
142083695 ps |
| T147 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2479574042 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:36 PM PST 24 |
104646766 ps |
| T915 |
/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1509043051 |
|
|
Mar 05 12:43:11 PM PST 24 |
Mar 05 12:43:17 PM PST 24 |
38144391 ps |
| T916 |
/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2049673343 |
|
|
Mar 05 12:42:58 PM PST 24 |
Mar 05 12:43:00 PM PST 24 |
24438854 ps |
| T917 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1445219681 |
|
|
Mar 05 12:43:08 PM PST 24 |
Mar 05 12:43:09 PM PST 24 |
15959369 ps |
| T918 |
/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.61784391 |
|
|
Mar 05 12:43:07 PM PST 24 |
Mar 05 12:43:09 PM PST 24 |
224764419 ps |
| T919 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1556930563 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:42 PM PST 24 |
431567493 ps |
| T920 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.906791463 |
|
|
Mar 05 12:42:32 PM PST 24 |
Mar 05 12:42:34 PM PST 24 |
214384738 ps |
| T921 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4188204467 |
|
|
Mar 05 12:42:41 PM PST 24 |
Mar 05 12:42:43 PM PST 24 |
65140131 ps |
| T922 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.4076424259 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
27348856 ps |
| T923 |
/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3838419838 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
34225926 ps |
| T924 |
/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2326495945 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
17253681 ps |
| T141 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1005635201 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:45 PM PST 24 |
85239585 ps |
| T925 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2834066511 |
|
|
Mar 05 12:42:32 PM PST 24 |
Mar 05 12:42:36 PM PST 24 |
377047531 ps |
| T120 |
/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3752277121 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
148345393 ps |
| T926 |
/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2030170686 |
|
|
Mar 05 12:43:06 PM PST 24 |
Mar 05 12:43:07 PM PST 24 |
25224104 ps |
| T927 |
/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2464602717 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
27941216 ps |
| T928 |
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1247563826 |
|
|
Mar 05 12:42:32 PM PST 24 |
Mar 05 12:42:34 PM PST 24 |
85694903 ps |
| T929 |
/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1077329166 |
|
|
Mar 05 12:43:09 PM PST 24 |
Mar 05 12:43:10 PM PST 24 |
110743169 ps |
| T930 |
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.405987689 |
|
|
Mar 05 12:42:43 PM PST 24 |
Mar 05 12:42:45 PM PST 24 |
167731745 ps |
| T931 |
/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.279546166 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
24384429 ps |
| T932 |
/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.761576175 |
|
|
Mar 05 12:42:50 PM PST 24 |
Mar 05 12:42:53 PM PST 24 |
80873745 ps |
| T933 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3911939939 |
|
|
Mar 05 12:42:38 PM PST 24 |
Mar 05 12:42:40 PM PST 24 |
32508162 ps |
| T934 |
/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2545411628 |
|
|
Mar 05 12:42:56 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
26655334 ps |
| T935 |
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4286175264 |
|
|
Mar 05 12:42:39 PM PST 24 |
Mar 05 12:42:41 PM PST 24 |
149568475 ps |
| T936 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2237023525 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:04 PM PST 24 |
49388634 ps |
| T937 |
/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.4128323100 |
|
|
Mar 05 12:43:03 PM PST 24 |
Mar 05 12:43:04 PM PST 24 |
31049822 ps |
| T938 |
/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.905345795 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
14867388 ps |
| T939 |
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.607362949 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:36 PM PST 24 |
88269169 ps |
| T142 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1497790359 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
154057929 ps |
| T940 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3011204403 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:06 PM PST 24 |
78252409 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1461655990 |
|
|
Mar 05 12:42:30 PM PST 24 |
Mar 05 12:42:31 PM PST 24 |
19185991 ps |
| T942 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.238844750 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
51591923 ps |
| T943 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2272751357 |
|
|
Mar 05 12:42:51 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
418054988 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3215790016 |
|
|
Mar 05 12:42:50 PM PST 24 |
Mar 05 12:42:53 PM PST 24 |
56492221 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1846015002 |
|
|
Mar 05 12:42:58 PM PST 24 |
Mar 05 12:43:01 PM PST 24 |
112750243 ps |
| T946 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.3186976105 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:52 PM PST 24 |
783235348 ps |
| T947 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.969708423 |
|
|
Mar 05 12:42:29 PM PST 24 |
Mar 05 12:42:30 PM PST 24 |
48069195 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1063510290 |
|
|
Mar 05 12:42:42 PM PST 24 |
Mar 05 12:42:43 PM PST 24 |
57163635 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1905060883 |
|
|
Mar 05 12:42:57 PM PST 24 |
Mar 05 12:42:58 PM PST 24 |
78831041 ps |
| T118 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.257622697 |
|
|
Mar 05 12:42:30 PM PST 24 |
Mar 05 12:42:32 PM PST 24 |
84659219 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3371143506 |
|
|
Mar 05 12:42:45 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
454409072 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1024975082 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
34095556 ps |
| T121 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2010200479 |
|
|
Mar 05 12:42:58 PM PST 24 |
Mar 05 12:43:00 PM PST 24 |
123117109 ps |
| T952 |
/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1128526097 |
|
|
Mar 05 12:43:01 PM PST 24 |
Mar 05 12:43:02 PM PST 24 |
17813744 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3682128349 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
170921404 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3949715619 |
|
|
Mar 05 12:42:30 PM PST 24 |
Mar 05 12:42:33 PM PST 24 |
100781403 ps |
| T954 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2641655186 |
|
|
Mar 05 12:42:42 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
81514225 ps |
| T955 |
/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2007457759 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
58743941 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1328045799 |
|
|
Mar 05 12:42:57 PM PST 24 |
Mar 05 12:42:58 PM PST 24 |
12938465 ps |
| T125 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.435850766 |
|
|
Mar 05 12:43:12 PM PST 24 |
Mar 05 12:43:15 PM PST 24 |
228639602 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2624728456 |
|
|
Mar 05 12:42:30 PM PST 24 |
Mar 05 12:42:32 PM PST 24 |
79252552 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.189252801 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
72681445 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1914183748 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
68382368 ps |
| T126 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.22966193 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
243866446 ps |
| T960 |
/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1343548505 |
|
|
Mar 05 12:43:09 PM PST 24 |
Mar 05 12:43:10 PM PST 24 |
24630795 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.312114548 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:49 PM PST 24 |
270245992 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2238459939 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:38 PM PST 24 |
41049261 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2646894416 |
|
|
Mar 05 12:42:32 PM PST 24 |
Mar 05 12:42:34 PM PST 24 |
113028436 ps |
| T964 |
/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3703007760 |
|
|
Mar 05 12:42:58 PM PST 24 |
Mar 05 12:42:59 PM PST 24 |
18464642 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.599995761 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:41 PM PST 24 |
669898692 ps |
| T966 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.441978990 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:52 PM PST 24 |
299053675 ps |
| T967 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2871841546 |
|
|
Mar 05 12:42:51 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
151639426 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1436769687 |
|
|
Mar 05 12:43:07 PM PST 24 |
Mar 05 12:43:08 PM PST 24 |
41528232 ps |
| T969 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3581269870 |
|
|
Mar 05 12:42:49 PM PST 24 |
Mar 05 12:42:51 PM PST 24 |
84186196 ps |
| T970 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.4079875362 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
58490930 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2016006928 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
76349660 ps |
| T123 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2162268482 |
|
|
Mar 05 12:43:10 PM PST 24 |
Mar 05 12:43:12 PM PST 24 |
131989580 ps |
| T972 |
/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.158991638 |
|
|
Mar 05 12:43:11 PM PST 24 |
Mar 05 12:43:12 PM PST 24 |
12875753 ps |
| T119 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2489292253 |
|
|
Mar 05 12:42:33 PM PST 24 |
Mar 05 12:42:36 PM PST 24 |
272856689 ps |
| T973 |
/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1174785327 |
|
|
Mar 05 12:42:52 PM PST 24 |
Mar 05 12:42:54 PM PST 24 |
32598828 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2299468444 |
|
|
Mar 05 12:42:56 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
88261268 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1637517606 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
194475850 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1753710766 |
|
|
Mar 05 12:42:26 PM PST 24 |
Mar 05 12:42:27 PM PST 24 |
120715606 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.611513068 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
23436828 ps |
| T978 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.561821557 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
197847028 ps |
| T979 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2577318069 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:56 PM PST 24 |
149813011 ps |
| T128 |
/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.84838803 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:07 PM PST 24 |
248146873 ps |
| T980 |
/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.232861957 |
|
|
Mar 05 12:43:04 PM PST 24 |
Mar 05 12:43:05 PM PST 24 |
15596251 ps |
| T981 |
/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3259548506 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:47 PM PST 24 |
14608170 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2595845265 |
|
|
Mar 05 12:43:19 PM PST 24 |
Mar 05 12:43:21 PM PST 24 |
13916231 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2495568180 |
|
|
Mar 05 12:42:44 PM PST 24 |
Mar 05 12:42:46 PM PST 24 |
36321100 ps |
| T984 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3491601050 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:04 PM PST 24 |
89571827 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1649104147 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:33 PM PST 24 |
102570859 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3001369007 |
|
|
Mar 05 12:42:53 PM PST 24 |
Mar 05 12:42:55 PM PST 24 |
56137863 ps |
| T987 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3490259094 |
|
|
Mar 05 12:42:47 PM PST 24 |
Mar 05 12:42:49 PM PST 24 |
214998859 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.72382659 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:31 PM PST 24 |
25890248 ps |
| T989 |
/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1660039334 |
|
|
Mar 05 12:43:02 PM PST 24 |
Mar 05 12:43:03 PM PST 24 |
13834294 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3957043414 |
|
|
Mar 05 12:43:03 PM PST 24 |
Mar 05 12:43:04 PM PST 24 |
14130978 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1201402439 |
|
|
Mar 05 12:42:48 PM PST 24 |
Mar 05 12:42:50 PM PST 24 |
31101959 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.591138155 |
|
|
Mar 05 12:43:07 PM PST 24 |
Mar 05 12:43:09 PM PST 24 |
104715236 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1193340119 |
|
|
Mar 05 12:42:54 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
91974909 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.527577158 |
|
|
Mar 05 12:42:34 PM PST 24 |
Mar 05 12:42:35 PM PST 24 |
20990669 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.134100540 |
|
|
Mar 05 12:42:55 PM PST 24 |
Mar 05 12:42:57 PM PST 24 |
106923119 ps |
| T995 |
/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.4219763704 |
|
|
Mar 05 12:43:06 PM PST 24 |
Mar 05 12:43:07 PM PST 24 |
14004102 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1883090161 |
|
|
Mar 05 12:42:31 PM PST 24 |
Mar 05 12:42:32 PM PST 24 |
17917203 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.82501857 |
|
|
Mar 05 12:42:41 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
1802467980 ps |
| T998 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.292174397 |
|
|
Mar 05 12:42:46 PM PST 24 |
Mar 05 12:42:48 PM PST 24 |
72272909 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.562886958 |
|
|
Mar 05 12:42:42 PM PST 24 |
Mar 05 12:42:44 PM PST 24 |
29315734 ps |
| T1000 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.234683304 |
|
|
Mar 05 12:42:33 PM PST 24 |
Mar 05 12:42:36 PM PST 24 |
308890576 ps |