Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314584434 1 T6 2076 T7 2638 T8 2684
auto[1] 388370 1 T8 600 T25 298 T22 90


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314596646 1 T6 2076 T7 2638 T8 2800
auto[1] 376158 1 T8 484 T25 272 T22 68


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314526254 1 T6 2076 T7 2638 T8 2730
auto[1] 446550 1 T8 554 T25 224 T22 156


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 290949308 1 T6 2076 T7 2638 T8 2564
auto[1] 24023496 1 T8 720 T25 1834 T123 1752


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 181693214 1 T6 2076 T7 2280 T8 2836
auto[1] 133279590 1 T7 358 T8 448 T24 482


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 166743768 1 T6 2076 T7 2280 T8 1902
auto[0] auto[0] auto[0] auto[0] auto[1] 123888392 1 T7 358 T8 176 T24 482
auto[0] auto[0] auto[0] auto[1] auto[0] 27532 1 T8 56 T25 50 T22 30
auto[0] auto[0] auto[0] auto[1] auto[1] 6592 1 T11 18 T12 68 T13 170
auto[0] auto[0] auto[1] auto[0] auto[0] 14401354 1 T8 276 T25 1614 T123 1624
auto[0] auto[0] auto[1] auto[0] auto[1] 9285112 1 T8 90 T25 84 T40 266
auto[0] auto[0] auto[1] auto[1] auto[0] 50010 1 T8 86 T25 32 T40 40
auto[0] auto[0] auto[1] auto[1] auto[1] 11622 1 T8 14 T40 26 T124 140
auto[0] auto[1] auto[0] auto[0] auto[0] 58104 1 T8 6 T123 36 T40 8
auto[0] auto[1] auto[0] auto[0] auto[1] 1486 1 T125 6 T11 2 T12 28
auto[0] auto[1] auto[0] auto[1] auto[0] 11610 1 T8 48 T124 68 T11 104
auto[0] auto[1] auto[0] auto[1] auto[1] 2866 1 T125 70 T11 48 T13 84
auto[0] auto[1] auto[1] auto[0] auto[0] 10396 1 T25 6 T40 14 T124 28
auto[0] auto[1] auto[1] auto[0] auto[1] 2168 1 T8 8 T25 34 T40 8
auto[0] auto[1] auto[1] auto[1] auto[0] 20688 1 T25 64 T40 82 T125 98
auto[0] auto[1] auto[1] auto[1] auto[1] 4554 1 T8 68 T12 84 T16 72
auto[1] auto[0] auto[0] auto[0] auto[0] 40680 1 T8 34 T25 2 T22 54
auto[1] auto[0] auto[0] auto[0] auto[1] 3908 1 T8 34 T22 34 T11 8
auto[1] auto[0] auto[0] auto[1] auto[0] 32894 1 T8 46 T25 54 T40 62
auto[1] auto[0] auto[0] auto[1] auto[1] 8422 1 T8 58 T12 180 T13 174
auto[1] auto[0] auto[1] auto[0] auto[0] 26698 1 T8 28 T123 32 T40 20
auto[1] auto[0] auto[1] auto[0] auto[1] 6506 1 T40 20 T124 40 T125 50
auto[1] auto[0] auto[1] auto[1] auto[0] 48778 1 T40 126 T125 76 T11 370
auto[1] auto[0] auto[1] auto[1] auto[1] 14378 1 T40 102 T124 146 T125 58
auto[1] auto[1] auto[0] auto[0] auto[0] 61436 1 T8 62 T25 38 T22 8
auto[1] auto[1] auto[0] auto[0] auto[1] 5628 1 T25 32 T123 10 T40 8
auto[1] auto[1] auto[0] auto[1] auto[0] 44538 1 T8 142 T25 52 T22 60
auto[1] auto[1] auto[0] auto[1] auto[1] 11452 1 T25 46 T12 86 T13 252
auto[1] auto[1] auto[1] auto[0] auto[0] 39622 1 T8 68 T123 96 T40 34
auto[1] auto[1] auto[1] auto[0] auto[1] 9176 1 T124 38 T126 70 T11 12
auto[1] auto[1] auto[1] auto[1] auto[0] 75106 1 T8 82 T40 42 T125 226
auto[1] auto[1] auto[1] auto[1] auto[1] 17328 1 T11 96 T12 142 T13 598

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