Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294179808

1

T5

3934

T4

2470

T6

2400

auto[1]

395236

1

T15

212

T18

312

T21

440

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294206894

1

T5

3934

T4

2470

T6

2400

auto[1]

368150

1

T15

388

T18

184

T21

188

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294118104

1

T5

3934

T4

2470

T6

2400

auto[1]

456940

1

T15

366

T18

442

T21

380

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284272390

1

T5

3934

T4

2470

T6

2400

auto[1]

10302654

1

T15

2326

T18

1828

T27

2064

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163164332

1

T5

3886

T4

2452

T6

2400

auto[1]

131410712

1

T5

48

T4

18

T22

20

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

153811206

1

T5

3886

T4

2452

T6

2400

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130164934

1

T5

48

T4

18

T22

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28314

1

T18

8

T21

134

T27

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6972

1

T21

14

T109

86

T3

44

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

8828550

1

T15

1798

T18

1598

T27

400

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1131818

1

T15

64

T27

1244

T109

220

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47504

1

T15

12

T18

22

T27

172

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12402

1

T27

12

T109

4

T3

304

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

31100

1

T109

18

T67

8

T7

54

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1604

1

T15

28

T7

46

T9

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12448

1

T109

70

T82

50

T85

78

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3182

1

T9

116

T150

60

T33

46

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10568

1

T15

58

T27

2

T73

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2442

1

T15

20

T27

18

T109

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19636

1

T15

70

T27

64

T73

62

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5424

1

T27

42

T109

66

T9

226

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36522

1

T15

22

T18

54

T21

24

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3618

1

T21

2

T109

4

T70

18

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29972

1

T18

108

T21

110

T27

54

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7336

1

T21

56

T109

58

T70

78

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25992

1

T15

72

T18

40

T27

24

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7318

1

T27

2

T109

18

T70

62

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50202

1

T15

60

T18

56

T27

36

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14234

1

T27

40

T71

86

T72

80

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

68152

1

T15

22

T18

26

T21

62

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6116

1

T15

18

T109

24

T3

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47664

1

T18

46

T21

126

T27

38

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13250

1

T3

88

T67

64

T82

64

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39340

1

T15

102

T18

40

T73

92

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10528

1

T27

8

T109

6

T3

160

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

77162

1

T15

70

T18

72

T73

86

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19534

1

T109

56

T3

456

T70

154