Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300090230

1

T7

3502

T5

121570

T8

3022

auto[1]

393544

1

T7

758

T25

618

T26

636

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300096582

1

T7

3440

T5

121570

T8

3022

auto[1]

387192

1

T7

820

T25

384

T26

534

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300011376

1

T7

3266

T5

121570

T8

3022

auto[1]

472398

1

T7

994

T25

410

T26

708

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281814960

1

T7

2314

T5

121570

T8

3022

auto[1]

18668814

1

T7

1946

T25

134

T26

1392

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

173131322

1

T7

3622

T5

121570

T8

3022

auto[1]

127352452

1

T7

638

T25

920

T26

304

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

157379486

1

T7

2008

T5

121570

T8

3022

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

124103138

1

T25

546

T1

4184

T2

439904

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30498

1

T7

110

T25

52

T26

24

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7590

1

T25

154

T2

52

T19

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15196430

1

T7

750

T25

80

T26

598

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3133964

1

T7

272

T26

136

T2

2570

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46350

1

T7

28

T25

2

T26

66

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12398

1

T7

40

T26

34

T2

82

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50774

1

T25

4

T26

6

T2

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1040

1

T2

26

T11

2

T12

26

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11814

1

T25

114

T26

66

T2

44

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2854

1

T11

38

T15

84

T67

62

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9116

1

T7

58

T26

8

T2

36

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2702

1

T2

68

T20

4

T11

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17074

1

T26

72

T2

96

T3

50

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6148

1

T2

128

T20

64

T11

40

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43946

1

T7

66

T25

34

T26

112

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3916

1

T25

24

T2

18

T19

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29108

1

T7

54

T26

72

T2

248

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9568

1

T25

86

T2

212

T19

58

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27514

1

T7

112

T26

52

T2

224

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7656

1

T26

10

T2

50

T3

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51578

1

T2

596

T3

126

T20

240

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13442

1

T26

80

T2

122

T3

54

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

75164

1

T7

76

T25

40

T26

46

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6332

1

T25

14

T2

16

T3

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46790

1

T25

64

T2

436

T20

66

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12942

1

T25

96

T2

136

T3

48

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39594

1

T7

106

T25

2

T26

70

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9458

1

T7

54

T26

44

T2

66

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

76086

1

T7

254

T25

50

T26

222

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19304

1

T7

272

T2

232

T11

106