Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318897438 1 T7 1960 T8 3908 T9 29944
auto[1] 403540 1 T7 122 T8 920 T9 462


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318893278 1 T7 1972 T8 4374 T9 29936
auto[1] 407700 1 T7 110 T8 454 T9 470


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318807262 1 T7 1972 T8 3938 T9 29792
auto[1] 493716 1 T7 110 T8 890 T9 614


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298427416 1 T7 2082 T8 1234 T9 29008
auto[1] 20873562 1 T8 3594 T9 1398 T6 4560


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 197048504 1 T7 1928 T8 1806 T9 18342
auto[1] 122252474 1 T7 154 T8 3022 T9 12064


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 178781728 1 T7 1828 T8 402 T9 16956
auto[0] auto[0] auto[0] auto[0] auto[1] 119286562 1 T7 76 T8 280 T9 11792
auto[0] auto[0] auto[0] auto[1] auto[0] 29928 1 T7 46 T8 92 T9 52
auto[0] auto[0] auto[0] auto[1] auto[1] 7524 1 T7 22 T8 118 T19 22
auto[0] auto[0] auto[1] auto[0] auto[0] 17671574 1 T8 518 T9 738 T6 826
auto[0] auto[0] auto[1] auto[0] auto[1] 2852146 1 T8 2358 T9 132 T6 2876
auto[0] auto[0] auto[1] auto[1] auto[0] 50626 1 T8 140 T9 20 T6 100
auto[0] auto[0] auto[1] auto[1] auto[1] 11944 1 T9 30 T6 2 T19 32
auto[0] auto[1] auto[0] auto[0] auto[0] 58000 1 T29 10 T4 1860 T20 40
auto[0] auto[1] auto[0] auto[0] auto[1] 1378 1 T86 32 T188 2 T189 2
auto[0] auto[1] auto[0] auto[1] auto[0] 12420 1 T29 88 T22 54 T12 100
auto[0] auto[1] auto[0] auto[1] auto[1] 2972 1 T188 66 T189 46 T190 100
auto[0] auto[1] auto[1] auto[0] auto[0] 11730 1 T8 30 T9 38 T22 22
auto[0] auto[1] auto[1] auto[0] auto[1] 2942 1 T9 34 T13 22 T14 2
auto[0] auto[1] auto[1] auto[1] auto[0] 21002 1 T25 94 T86 90 T12 116
auto[0] auto[1] auto[1] auto[1] auto[1] 4786 1 T13 42 T14 56 T16 38
auto[1] auto[0] auto[0] auto[0] auto[0] 58702 1 T8 70 T9 12 T6 10
auto[1] auto[0] auto[0] auto[0] auto[1] 4576 1 T8 8 T19 38 T22 4
auto[1] auto[0] auto[0] auto[1] auto[0] 30206 1 T8 62 T9 80 T6 48
auto[1] auto[0] auto[0] auto[1] auto[1] 8060 1 T8 68 T19 126 T22 52
auto[1] auto[0] auto[1] auto[0] auto[0] 27318 1 T8 30 T9 48 T6 42
auto[1] auto[0] auto[1] auto[0] auto[1] 6746 1 T8 78 T9 22 T19 10
auto[1] auto[0] auto[1] auto[1] auto[0] 53196 1 T8 72 T6 112 T19 84
auto[1] auto[0] auto[1] auto[1] auto[1] 12442 1 T8 78 T9 54 T19 74
auto[1] auto[1] auto[0] auto[0] auto[0] 77996 1 T7 54 T8 30 T9 48
auto[1] auto[1] auto[0] auto[0] auto[1] 6006 1 T7 2 T8 34 T85 44
auto[1] auto[1] auto[0] auto[1] auto[0] 48852 1 T8 70 T9 68 T6 106
auto[1] auto[1] auto[0] auto[1] auto[1] 12506 1 T7 54 T12 100 T16 102
auto[1] auto[1] auto[1] auto[0] auto[0] 39104 1 T8 70 T9 124 T6 44
auto[1] auto[1] auto[1] auto[0] auto[1] 10930 1 T6 22 T22 40 T25 20
auto[1] auto[1] auto[1] auto[1] auto[0] 76122 1 T8 220 T9 158 T6 414
auto[1] auto[1] auto[1] auto[1] auto[1] 20954 1 T6 122 T22 46 T25 86

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