Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312654394 1 T6 2458 T7 2086 T4 37820
auto[1] 425264 1 T6 64 T7 420 T25 66


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312657106 1 T6 2442 T7 2222 T4 37820
auto[1] 422552 1 T6 80 T7 284 T25 134


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312584706 1 T6 2442 T7 1994 T4 37820
auto[1] 494952 1 T6 80 T7 512 T25 236


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298403268 1 T6 2522 T7 2506 T4 37820
auto[1] 14676390 1 T25 946 T1 11016 T19 184


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 177884170 1 T6 2502 T7 2174 T4 37820
auto[1] 135195488 1 T6 20 T7 332 T5 28


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 164462532 1 T6 2422 T7 1738 T4 37820
auto[0] auto[0] auto[0] auto[0] auto[1] 133590068 1 T6 20 T7 182 T5 28
auto[0] auto[0] auto[0] auto[1] auto[0] 32952 1 T7 74 T1 188 T21 4
auto[0] auto[0] auto[0] auto[1] auto[1] 7582 1 T1 32 T19 106 T22 4
auto[0] auto[0] auto[1] auto[0] auto[0] 12819730 1 T25 616 T1 3206 T19 92
auto[0] auto[0] auto[1] auto[0] auto[1] 1486286 1 T25 92 T1 5614 T21 130
auto[0] auto[0] auto[1] auto[1] auto[0] 51832 1 T25 66 T1 248 T19 26
auto[0] auto[0] auto[1] auto[1] auto[1] 14058 1 T1 140 T22 10 T31 6
auto[0] auto[1] auto[0] auto[0] auto[0] 64068 1 T21 14 T182 16 T12 18
auto[0] auto[1] auto[0] auto[0] auto[1] 1496 1 T182 8 T35 16 T163 26
auto[0] auto[1] auto[0] auto[1] auto[0] 12430 1 T21 88 T12 60 T85 176
auto[0] auto[1] auto[0] auto[1] auto[1] 2894 1 T35 88 T163 44 T72 56
auto[0] auto[1] auto[1] auto[0] auto[0] 10898 1 T25 22 T1 54 T21 106
auto[0] auto[1] auto[1] auto[0] auto[1] 2414 1 T1 32 T21 46 T22 22
auto[0] auto[1] auto[1] auto[1] auto[0] 19702 1 T1 154 T23 60 T36 48
auto[0] auto[1] auto[1] auto[1] auto[1] 5764 1 T1 70 T22 58 T183 50
auto[1] auto[0] auto[0] auto[0] auto[0] 35680 1 T7 118 T1 106 T21 50
auto[1] auto[0] auto[0] auto[0] auto[1] 4412 1 T1 8 T19 12 T22 6
auto[1] auto[0] auto[0] auto[1] auto[0] 35000 1 T7 110 T1 60 T22 46
auto[1] auto[0] auto[0] auto[1] auto[1] 8148 1 T1 68 T19 60 T22 48
auto[1] auto[0] auto[1] auto[0] auto[0] 30116 1 T25 88 T1 138 T21 92
auto[1] auto[0] auto[1] auto[0] auto[1] 7544 1 T25 36 T1 52 T22 36
auto[1] auto[0] auto[1] auto[1] auto[0] 56912 1 T1 356 T22 54 T23 122
auto[1] auto[0] auto[1] auto[1] auto[1] 14254 1 T1 78 T23 52 T31 56
auto[1] auto[1] auto[0] auto[0] auto[0] 78238 1 T6 16 T7 14 T25 86
auto[1] auto[1] auto[0] auto[0] auto[1] 6174 1 T7 34 T1 6 T22 28
auto[1] auto[1] auto[0] auto[1] auto[0] 49386 1 T6 64 T7 120 T1 434
auto[1] auto[1] auto[0] auto[1] auto[1] 12208 1 T7 116 T1 84 T182 152
auto[1] auto[1] auto[1] auto[0] auto[0] 43630 1 T25 26 T1 166 T19 2
auto[1] auto[1] auto[1] auto[0] auto[1] 11108 1 T1 72 T30 12 T117 10
auto[1] auto[1] auto[1] auto[1] auto[0] 81064 1 T1 458 T19 64 T22 126
auto[1] auto[1] auto[1] auto[1] auto[1] 21078 1 T1 178 T117 90 T12 68

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%