Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80


Total test records in report: 1010
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T804 /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3826493610 Mar 17 12:45:40 PM PDT 24 Mar 17 12:45:42 PM PDT 24 29931920 ps
T805 /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.659221088 Mar 17 12:44:58 PM PDT 24 Mar 17 12:44:59 PM PDT 24 34689293 ps
T806 /workspace/coverage/default/3.clkmgr_peri.4182322645 Mar 17 12:44:39 PM PDT 24 Mar 17 12:44:40 PM PDT 24 24641469 ps
T807 /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3258641929 Mar 17 12:46:09 PM PDT 24 Mar 17 12:46:10 PM PDT 24 84557864 ps
T808 /workspace/coverage/default/39.clkmgr_frequency_timeout.61966851 Mar 17 12:45:34 PM PDT 24 Mar 17 12:45:37 PM PDT 24 381429312 ps
T809 /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.828090164 Mar 17 12:44:41 PM PDT 24 Mar 17 12:56:52 PM PDT 24 165477215039 ps
T810 /workspace/coverage/default/29.clkmgr_frequency.1180656949 Mar 17 12:45:41 PM PDT 24 Mar 17 12:45:59 PM PDT 24 2359839209 ps
T811 /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3742850948 Mar 17 12:46:02 PM PDT 24 Mar 17 12:46:04 PM PDT 24 70506818 ps
T812 /workspace/coverage/default/5.clkmgr_trans.2431731016 Mar 17 12:44:44 PM PDT 24 Mar 17 12:44:45 PM PDT 24 75754091 ps
T813 /workspace/coverage/default/12.clkmgr_stress_all.2399231810 Mar 17 12:44:50 PM PDT 24 Mar 17 12:45:03 PM PDT 24 2609290575 ps
T814 /workspace/coverage/default/48.clkmgr_clk_status.992172231 Mar 17 12:46:27 PM PDT 24 Mar 17 12:46:28 PM PDT 24 13198147 ps
T815 /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.102980810 Mar 17 12:44:48 PM PDT 24 Mar 17 12:44:48 PM PDT 24 22288047 ps
T816 /workspace/coverage/default/41.clkmgr_peri.367184906 Mar 17 12:46:03 PM PDT 24 Mar 17 12:46:04 PM PDT 24 38625959 ps
T817 /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.60037342 Mar 17 12:45:39 PM PDT 24 Mar 17 12:45:40 PM PDT 24 40990452 ps
T818 /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3241924790 Mar 17 12:46:28 PM PDT 24 Mar 17 12:46:29 PM PDT 24 15147720 ps
T819 /workspace/coverage/default/39.clkmgr_frequency.1228773312 Mar 17 12:45:48 PM PDT 24 Mar 17 12:45:51 PM PDT 24 995466667 ps
T820 /workspace/coverage/default/9.clkmgr_frequency_timeout.1317150676 Mar 17 12:44:52 PM PDT 24 Mar 17 12:45:01 PM PDT 24 2423872971 ps
T821 /workspace/coverage/default/30.clkmgr_regwen.4163658224 Mar 17 12:45:41 PM PDT 24 Mar 17 12:45:44 PM PDT 24 567548480 ps
T822 /workspace/coverage/default/4.clkmgr_clk_status.43536414 Mar 17 12:44:44 PM PDT 24 Mar 17 12:44:47 PM PDT 24 21198855 ps
T823 /workspace/coverage/default/36.clkmgr_smoke.3450058742 Mar 17 12:45:35 PM PDT 24 Mar 17 12:45:36 PM PDT 24 23918549 ps
T824 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.630486010 Mar 17 12:45:41 PM PDT 24 Mar 17 12:54:52 PM PDT 24 82807917975 ps
T825 /workspace/coverage/default/9.clkmgr_smoke.2943665551 Mar 17 12:44:51 PM PDT 24 Mar 17 12:44:52 PM PDT 24 44653967 ps
T826 /workspace/coverage/default/20.clkmgr_trans.3117668004 Mar 17 12:45:35 PM PDT 24 Mar 17 12:45:42 PM PDT 24 44959767 ps
T827 /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.388093032 Mar 17 12:44:57 PM PDT 24 Mar 17 12:53:25 PM PDT 24 150517227425 ps
T59 /workspace/coverage/default/1.clkmgr_sec_cm.722962648 Mar 17 12:44:38 PM PDT 24 Mar 17 12:44:42 PM PDT 24 698454230 ps
T828 /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1008149536 Mar 17 12:44:44 PM PDT 24 Mar 17 12:44:45 PM PDT 24 45764890 ps
T829 /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3018744067 Mar 17 12:45:30 PM PDT 24 Mar 17 12:45:31 PM PDT 24 26001593 ps
T830 /workspace/coverage/default/22.clkmgr_clk_status.1964613079 Mar 17 12:45:34 PM PDT 24 Mar 17 12:45:35 PM PDT 24 17855257 ps
T831 /workspace/coverage/default/16.clkmgr_peri.262077082 Mar 17 12:44:51 PM PDT 24 Mar 17 12:44:52 PM PDT 24 36137439 ps
T832 /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3011272868 Mar 17 12:44:50 PM PDT 24 Mar 17 12:56:46 PM PDT 24 79902769743 ps
T833 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1606636137 Mar 17 12:45:33 PM PDT 24 Mar 17 12:45:34 PM PDT 24 89388879 ps
T834 /workspace/coverage/default/47.clkmgr_frequency.1141058444 Mar 17 12:46:34 PM PDT 24 Mar 17 12:46:47 PM PDT 24 1636459803 ps
T835 /workspace/coverage/default/6.clkmgr_peri.3358242895 Mar 17 12:44:46 PM PDT 24 Mar 17 12:44:47 PM PDT 24 22295518 ps
T836 /workspace/coverage/default/43.clkmgr_clk_status.1182283745 Mar 17 12:46:23 PM PDT 24 Mar 17 12:46:24 PM PDT 24 16206656 ps
T837 /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1415106118 Mar 17 12:46:11 PM PDT 24 Mar 17 12:46:12 PM PDT 24 71542402 ps
T838 /workspace/coverage/default/27.clkmgr_regwen.2176736844 Mar 17 12:45:31 PM PDT 24 Mar 17 12:45:36 PM PDT 24 1242631912 ps
T839 /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.727886443 Mar 17 12:45:31 PM PDT 24 Mar 17 12:45:32 PM PDT 24 32598941 ps
T840 /workspace/coverage/default/34.clkmgr_smoke.3505970579 Mar 17 12:45:41 PM PDT 24 Mar 17 12:45:42 PM PDT 24 47275323 ps
T841 /workspace/coverage/default/46.clkmgr_peri.4001521831 Mar 17 12:46:27 PM PDT 24 Mar 17 12:46:28 PM PDT 24 176814074 ps
T842 /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.3210853896 Mar 17 12:44:44 PM PDT 24 Mar 17 12:55:19 PM PDT 24 109386321073 ps
T843 /workspace/coverage/default/31.clkmgr_div_intersig_mubi.846998443 Mar 17 12:45:41 PM PDT 24 Mar 17 12:45:43 PM PDT 24 88492610 ps
T844 /workspace/coverage/default/49.clkmgr_stress_all.2375157324 Mar 17 12:46:34 PM PDT 24 Mar 17 12:46:52 PM PDT 24 2305339428 ps
T845 /workspace/coverage/default/18.clkmgr_smoke.3805992300 Mar 17 12:44:52 PM PDT 24 Mar 17 12:44:53 PM PDT 24 35064777 ps
T846 /workspace/coverage/default/28.clkmgr_regwen.3981859882 Mar 17 12:45:40 PM PDT 24 Mar 17 12:45:47 PM PDT 24 1692127981 ps
T847 /workspace/coverage/default/48.clkmgr_frequency.3770929615 Mar 17 12:46:34 PM PDT 24 Mar 17 12:46:46 PM PDT 24 2120161557 ps
T848 /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3217582075 Mar 17 12:45:33 PM PDT 24 Mar 17 12:45:34 PM PDT 24 58190531 ps
T849 /workspace/coverage/default/26.clkmgr_stress_all.1943435292 Mar 17 12:45:34 PM PDT 24 Mar 17 12:45:46 PM PDT 24 2648548627 ps
T850 /workspace/coverage/default/35.clkmgr_trans.4040479105 Mar 17 12:46:10 PM PDT 24 Mar 17 12:46:11 PM PDT 24 173043439 ps
T851 /workspace/coverage/default/0.clkmgr_regwen.3170297009 Mar 17 12:44:38 PM PDT 24 Mar 17 12:44:41 PM PDT 24 388149885 ps
T852 /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.2302034410 Mar 17 12:46:29 PM PDT 24 Mar 17 12:46:30 PM PDT 24 17723926 ps
T853 /workspace/coverage/default/40.clkmgr_trans.942613612 Mar 17 12:45:45 PM PDT 24 Mar 17 12:45:46 PM PDT 24 31088255 ps
T854 /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.3310620141 Mar 17 12:44:44 PM PDT 24 Mar 17 12:44:45 PM PDT 24 35490641 ps
T855 /workspace/coverage/default/6.clkmgr_trans.364188455 Mar 17 12:44:37 PM PDT 24 Mar 17 12:44:38 PM PDT 24 163315975 ps
T856 /workspace/coverage/default/7.clkmgr_extclk.424057513 Mar 17 12:44:47 PM PDT 24 Mar 17 12:44:49 PM PDT 24 79121090 ps
T857 /workspace/coverage/default/46.clkmgr_frequency.1026918896 Mar 17 12:46:22 PM PDT 24 Mar 17 12:46:32 PM PDT 24 2646011496 ps
T858 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4150260488 Mar 17 12:33:40 PM PDT 24 Mar 17 12:33:41 PM PDT 24 12860027 ps
T61 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1217120393 Mar 17 12:33:13 PM PDT 24 Mar 17 12:33:16 PM PDT 24 137106746 ps
T113 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.4169319063 Mar 17 12:33:19 PM PDT 24 Mar 17 12:33:22 PM PDT 24 484470743 ps
T859 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3426505169 Mar 17 12:32:56 PM PDT 24 Mar 17 12:32:58 PM PDT 24 36036449 ps
T860 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1876909950 Mar 17 12:33:31 PM PDT 24 Mar 17 12:33:32 PM PDT 24 11667225 ps
T861 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1672084624 Mar 17 12:33:35 PM PDT 24 Mar 17 12:33:37 PM PDT 24 16322070 ps
T862 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.2834188972 Mar 17 12:33:10 PM PDT 24 Mar 17 12:33:11 PM PDT 24 12107784 ps
T114 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.4011619800 Mar 17 12:27:19 PM PDT 24 Mar 17 12:27:23 PM PDT 24 470614827 ps
T115 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2451830911 Mar 17 12:33:19 PM PDT 24 Mar 17 12:33:22 PM PDT 24 349415673 ps
T88 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3417535980 Mar 17 12:32:41 PM PDT 24 Mar 17 12:32:43 PM PDT 24 51421496 ps
T863 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1319720273 Mar 17 12:32:55 PM PDT 24 Mar 17 12:32:58 PM PDT 24 86389237 ps
T864 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1495465708 Mar 17 12:28:15 PM PDT 24 Mar 17 12:28:17 PM PDT 24 26275373 ps
T865 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1275230441 Mar 17 12:32:42 PM PDT 24 Mar 17 12:32:45 PM PDT 24 472934063 ps
T866 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.182171905 Mar 17 12:33:36 PM PDT 24 Mar 17 12:33:37 PM PDT 24 13353281 ps
T867 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1194821970 Mar 17 12:33:17 PM PDT 24 Mar 17 12:33:18 PM PDT 24 13055242 ps
T89 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1040202411 Mar 17 12:24:29 PM PDT 24 Mar 17 12:24:31 PM PDT 24 90632256 ps
T90 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2007270191 Mar 17 12:32:55 PM PDT 24 Mar 17 12:32:57 PM PDT 24 74301807 ps
T868 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3201935458 Mar 17 12:33:39 PM PDT 24 Mar 17 12:33:40 PM PDT 24 29133211 ps
T91 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1127226561 Mar 17 12:28:32 PM PDT 24 Mar 17 12:28:35 PM PDT 24 53754710 ps
T62 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3921405677 Mar 17 12:33:16 PM PDT 24 Mar 17 12:33:18 PM PDT 24 180444674 ps
T63 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.561003063 Mar 17 12:33:19 PM PDT 24 Mar 17 12:33:22 PM PDT 24 109246351 ps
T64 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.250626531 Mar 17 12:33:02 PM PDT 24 Mar 17 12:33:06 PM PDT 24 60924312 ps
T178 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1448048751 Mar 17 12:28:00 PM PDT 24 Mar 17 12:28:08 PM PDT 24 1865037697 ps
T869 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.37931792 Mar 17 12:33:03 PM PDT 24 Mar 17 12:33:07 PM PDT 24 90416601 ps
T92 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.4273218233 Mar 17 12:33:01 PM PDT 24 Mar 17 12:33:06 PM PDT 24 49382900 ps
T870 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2869948126 Mar 17 12:33:42 PM PDT 24 Mar 17 12:33:43 PM PDT 24 35640565 ps
T871 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3767027869 Mar 17 12:28:06 PM PDT 24 Mar 17 12:28:08 PM PDT 24 67963831 ps
T93 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.377289935 Mar 17 12:33:18 PM PDT 24 Mar 17 12:33:19 PM PDT 24 57272329 ps
T65 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3366515611 Mar 17 12:33:26 PM PDT 24 Mar 17 12:33:29 PM PDT 24 658104303 ps
T872 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3338782393 Mar 17 12:33:40 PM PDT 24 Mar 17 12:33:41 PM PDT 24 35386506 ps
T873 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2603140209 Mar 17 12:32:48 PM PDT 24 Mar 17 12:32:51 PM PDT 24 74766194 ps
T874 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.906908309 Mar 17 12:33:40 PM PDT 24 Mar 17 12:33:40 PM PDT 24 26863512 ps
T875 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1551400871 Mar 17 12:33:18 PM PDT 24 Mar 17 12:33:20 PM PDT 24 77785341 ps
T876 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1497249276 Mar 17 12:33:39 PM PDT 24 Mar 17 12:33:40 PM PDT 24 24415864 ps
T877 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.399710562 Mar 17 12:27:56 PM PDT 24 Mar 17 12:27:58 PM PDT 24 28322864 ps
T121 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1828778397 Mar 17 12:33:17 PM PDT 24 Mar 17 12:33:19 PM PDT 24 65944857 ps
T878 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.302748156 Mar 17 12:33:41 PM PDT 24 Mar 17 12:33:42 PM PDT 24 167836863 ps
T879 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3264646524 Mar 17 12:33:17 PM PDT 24 Mar 17 12:33:18 PM PDT 24 19075087 ps
T880 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3379701422 Mar 17 12:33:38 PM PDT 24 Mar 17 12:33:39 PM PDT 24 38191083 ps
T881 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3216313908 Mar 17 12:33:39 PM PDT 24 Mar 17 12:33:40 PM PDT 24 13512867 ps
T882 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1878149059 Mar 17 12:33:16 PM PDT 24 Mar 17 12:33:18 PM PDT 24 118600489 ps
T123 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1974911626 Mar 17 12:32:40 PM PDT 24 Mar 17 12:32:43 PM PDT 24 166724065 ps
T883 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.123720775 Mar 17 12:33:17 PM PDT 24 Mar 17 12:33:18 PM PDT 24 22921586 ps
T884 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.4177386505 Mar 17 12:33:27 PM PDT 24 Mar 17 12:33:28 PM PDT 24 25971397 ps
T885 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2851137167 Mar 17 12:33:28 PM PDT 24 Mar 17 12:33:31 PM PDT 24 101168772 ps
T886 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.145213735 Mar 17 12:33:42 PM PDT 24 Mar 17 12:33:43 PM PDT 24 21855914 ps
T887 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.73605287 Mar 17 12:33:32 PM PDT 24 Mar 17 12:33:32 PM PDT 24 30135322 ps
T888 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2762495602 Mar 17 12:27:31 PM PDT 24 Mar 17 12:27:35 PM PDT 24 214259032 ps
T889 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.640979432 Mar 17 12:32:41 PM PDT 24 Mar 17 12:32:42 PM PDT 24 49305722 ps
T890 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2493882628 Mar 17 12:33:32 PM PDT 24 Mar 17 12:33:33 PM PDT 24 13634197 ps
T891 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2410471572 Mar 17 12:27:49 PM PDT 24 Mar 17 12:27:50 PM PDT 24 29042340 ps
T68 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2764500198 Mar 17 12:26:13 PM PDT 24 Mar 17 12:26:17 PM PDT 24 566450194 ps
T94 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2030632130 Mar 17 12:32:56 PM PDT 24 Mar 17 12:32:58 PM PDT 24 111209624 ps
T892 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3533117582 Mar 17 12:26:22 PM PDT 24 Mar 17 12:26:23 PM PDT 24 91486753 ps
T67 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2320230386 Mar 17 12:33:18 PM PDT 24 Mar 17 12:33:20 PM PDT 24 213966503 ps
T125 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.714235739 Mar 17 12:33:17 PM PDT 24 Mar 17 12:33:20 PM PDT 24 220126498 ps
T66 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2678654375 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:45 PM PDT 24 510179013 ps
T95 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2084722525 Mar 17 12:23:57 PM PDT 24 Mar 17 12:23:58 PM PDT 24 42529518 ps
T130 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.364162040 Mar 17 12:32:56 PM PDT 24 Mar 17 12:32:59 PM PDT 24 143369297 ps
T118 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2069866103 Mar 17 12:32:40 PM PDT 24 Mar 17 12:32:42 PM PDT 24 67265891 ps
T893 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.4121743990 Mar 17 12:27:56 PM PDT 24 Mar 17 12:27:58 PM PDT 24 84025415 ps
T894 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1009810008 Mar 17 12:33:32 PM PDT 24 Mar 17 12:33:33 PM PDT 24 47215995 ps
T895 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.4243552523 Mar 17 12:33:09 PM PDT 24 Mar 17 12:33:10 PM PDT 24 18635672 ps
T896 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.744126675 Mar 17 12:32:40 PM PDT 24 Mar 17 12:32:41 PM PDT 24 23251823 ps
T141 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3935692409 Mar 17 12:33:01 PM PDT 24 Mar 17 12:33:07 PM PDT 24 64621906 ps
T897 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3399350954 Mar 17 12:32:47 PM PDT 24 Mar 17 12:32:50 PM PDT 24 46528216 ps
T898 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.4134769290 Mar 17 12:32:51 PM PDT 24 Mar 17 12:32:53 PM PDT 24 47548380 ps
T145 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.178883337 Mar 17 12:33:03 PM PDT 24 Mar 17 12:33:08 PM PDT 24 315002129 ps
T131 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3351744007 Mar 17 12:28:17 PM PDT 24 Mar 17 12:28:18 PM PDT 24 99860341 ps
T132 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.661249710 Mar 17 12:23:41 PM PDT 24 Mar 17 12:23:46 PM PDT 24 740872251 ps
T899 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.651057976 Mar 17 12:33:41 PM PDT 24 Mar 17 12:33:42 PM PDT 24 16638463 ps
T900 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.740424191 Mar 17 12:32:42 PM PDT 24 Mar 17 12:32:44 PM PDT 24 255090301 ps
T901 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2037383859 Mar 17 12:32:48 PM PDT 24 Mar 17 12:32:50 PM PDT 24 34708586 ps
T902 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.417229344 Mar 17 12:23:09 PM PDT 24 Mar 17 12:23:10 PM PDT 24 70337963 ps
T903 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.784354819 Mar 17 12:33:37 PM PDT 24 Mar 17 12:33:37 PM PDT 24 27123504 ps
T904 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2546523752 Mar 17 12:25:56 PM PDT 24 Mar 17 12:26:01 PM PDT 24 863744171 ps
T122 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2211991661 Mar 17 12:32:55 PM PDT 24 Mar 17 12:32:57 PM PDT 24 111459251 ps
T905 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2711814293 Mar 17 12:27:41 PM PDT 24 Mar 17 12:27:47 PM PDT 24 1201158603 ps
T906 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3578612489 Mar 17 12:32:39 PM PDT 24 Mar 17 12:32:41 PM PDT 24 60214282 ps
T907 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2266202873 Mar 17 12:27:15 PM PDT 24 Mar 17 12:27:16 PM PDT 24 53366923 ps
T908 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3362925283 Mar 17 12:32:41 PM PDT 24 Mar 17 12:32:44 PM PDT 24 92910687 ps
T909 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.4073933696 Mar 17 12:33:24 PM PDT 24 Mar 17 12:33:27 PM PDT 24 18188881 ps
T133 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.638989931 Mar 17 12:33:11 PM PDT 24 Mar 17 12:33:16 PM PDT 24 515148592 ps
T910 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1324328188 Mar 17 12:27:20 PM PDT 24 Mar 17 12:27:23 PM PDT 24 269341103 ps
T911 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1383894898 Mar 17 12:33:16 PM PDT 24 Mar 17 12:33:18 PM PDT 24 94247615 ps
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