Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 364829326 1 T6 2314 T4 10812 T7 2502
auto[1] 452234 1 T26 544 T1 6666 T20 624


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 364843700 1 T6 2314 T4 10812 T7 2502
auto[1] 437860 1 T26 648 T1 4512 T5 1294


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 364737640 1 T6 2314 T4 10812 T7 2502
auto[1] 543920 1 T26 688 T1 5908 T20 674


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 341521378 1 T6 2314 T4 10812 T7 2502
auto[1] 23760182 1 T26 1444 T1 22890 T2 146960


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 211378138 1 T6 2314 T4 10788 T7 2142
auto[1] 153903422 1 T4 24 T7 360 T26 668


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 191358200 1 T6 2314 T4 10788 T7 2142
auto[0] auto[0] auto[0] auto[0] auto[1] 149795852 1 T4 24 T7 360 T26 92
auto[0] auto[0] auto[0] auto[1] auto[0] 31412 1 T26 16 T1 392 T20 24
auto[0] auto[0] auto[0] auto[1] auto[1] 7296 1 T26 18 T1 76 T20 6
auto[0] auto[0] auto[1] auto[0] auto[0] 19378352 1 T26 640 T1 15462 T2 146473
auto[0] auto[0] auto[1] auto[0] auto[1] 3981340 1 T26 276 T1 2486 T2 1492
auto[0] auto[0] auto[1] auto[1] auto[0] 54496 1 T26 18 T1 578 T2 398
auto[0] auto[0] auto[1] auto[1] auto[1] 16464 1 T26 16 T1 218 T2 66
auto[0] auto[1] auto[0] auto[0] auto[0] 58602 1 T26 10 T1 120 T5 1294
auto[0] auto[1] auto[0] auto[0] auto[1] 1478 1 T1 10 T14 128 T152 2
auto[0] auto[1] auto[0] auto[1] auto[0] 12940 1 T26 48 T1 362 T20 58
auto[0] auto[1] auto[0] auto[1] auto[1] 2562 1 T1 40 T152 54 T16 44
auto[0] auto[1] auto[1] auto[0] auto[0] 10350 1 T1 20 T2 84 T3 34
auto[0] auto[1] auto[1] auto[0] auto[1] 2540 1 T1 24 T2 22 T64 58
auto[0] auto[1] auto[1] auto[1] auto[0] 20516 1 T1 64 T2 300 T3 76
auto[0] auto[1] auto[1] auto[1] auto[1] 5240 1 T1 110 T2 64 T16 214
auto[1] auto[0] auto[0] auto[0] auto[0] 57158 1 T1 158 T20 16 T2 186
auto[1] auto[0] auto[0] auto[0] auto[1] 3430 1 T1 2 T20 2 T2 60
auto[1] auto[0] auto[0] auto[1] auto[0] 36628 1 T1 460 T20 92 T2 170
auto[1] auto[0] auto[0] auto[1] auto[1] 7730 1 T1 40 T20 42 T2 84
auto[1] auto[0] auto[1] auto[0] auto[0] 32814 1 T26 32 T1 220 T2 462
auto[1] auto[0] auto[1] auto[0] auto[1] 6892 1 T1 10 T2 4 T3 106
auto[1] auto[0] auto[1] auto[1] auto[0] 61056 1 T26 66 T1 1002 T2 742
auto[1] auto[0] auto[1] auto[1] auto[1] 14580 1 T1 254 T2 54 T70 66
auto[1] auto[1] auto[0] auto[0] auto[0] 76886 1 T26 46 T1 156 T20 108
auto[1] auto[1] auto[0] auto[0] auto[1] 6622 1 T26 18 T1 72 T20 12
auto[1] auto[1] auto[0] auto[1] auto[0] 53114 1 T26 68 T1 748 T20 366
auto[1] auto[1] auto[0] auto[1] auto[1] 11468 1 T26 62 T1 344 T20 36
auto[1] auto[1] auto[1] auto[0] auto[0] 46226 1 T26 110 T1 434 T2 352
auto[1] auto[1] auto[1] auto[0] auto[1] 12584 1 T26 54 T1 30 T2 90
auto[1] auto[1] auto[1] auto[1] auto[0] 89388 1 T26 100 T1 1802 T2 470
auto[1] auto[1] auto[1] auto[1] auto[1] 27344 1 T26 132 T1 176 T2 268

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