Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300875678

1

T7

1628

T8

4092

T5

178964

auto[1]

369750

1

T26

640

T27

760

T28

996

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300860396

1

T7

1628

T8

4092

T5

178964

auto[1]

385032

1

T26

496

T27

642

T28

1012

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300786940

1

T7

1498

T8

4092

T5

178964

auto[1]

458488

1

T7

130

T26

564

T27

700

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

285248380

1

T7

1478

T8

4092

T5

178964

auto[1]

15997048

1

T7

150

T26

914

T27

318

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168960272

1

T7

1608

T8

4092

T5

178936

auto[1]

132285156

1

T7

20

T5

28

T26

3152

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

155043044

1

T7

1354

T8

4092

T5

178936

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

129893412

1

T7

20

T5

28

T26

2704

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

26708

1

T26

24

T27

70

T28

36

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6364

1

T26

42

T28

18

T33

50

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

13378354

1

T7

124

T26

400

T27

92

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2289024

1

T26

192

T27

76

T28

268

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45600

1

T26

8

T27

4

T28

108

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12630

1

T26

34

T33

20

T1

36

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40362

1

T26

18

T27

34

T33

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1302

1

T1

4

T2

14

T173

26

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10690

1

T26

38

T27

56

T21

62

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2482

1

T1

106

T2

56

T74

108

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

11054

1

T26

8

T27

2

T28

26

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2168

1

T28

42

T1

36

T116

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19632

1

T27

62

T1

118

T21

74

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4114

1

T28

60

T11

140

T174

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

30426

1

T7

104

T26

12

T27

38

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3994

1

T1

28

T19

8

T22

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

26920

1

T26

58

T27

174

T28

68

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7094

1

T1

50

T19

70

T22

46

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

26630

1

T7

26

T26

10

T28

102

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6638

1

T26

8

T1

42

T21

26

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51972

1

T26

44

T28

66

T33

56

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11586

1

T1

172

T21

64

T175

50

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

96556

1

T26

6

T27

62

T28

34

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5642

1

T26

26

T27

12

T28

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42650

1

T26

144

T27

292

T28

66

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10734

1

T26

46

T27

40

T28

62

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37374

1

T26

4

T28

140

T33

52

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9698

1

T26

4

T27

20

T28

64

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

72300

1

T26

106

T28

458

T33

134

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18274

1

T26

96

T27

62

T28

54