Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333588848

1

T7

2492

T8

2688

T9

2446

auto[1]

426568

1

T8

608

T9

432

T24

280

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333611654

1

T7

1562

T8

3080

T9

2666

auto[1]

403762

1

T7

930

T8

216

T9

212

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

333515280

1

T7

2492

T8

2818

T9

2554

auto[1]

500136

1

T8

478

T9

324

T24

242

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316390860

1

T7

2492

T8

540

T9

546

auto[1]

17624556

1

T8

2756

T9

2332

T24

574

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192332402

1

T7

2472

T8

1358

T9

2502

auto[1]

141683014

1

T7

20

T8

1938

T9

376

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

179436264

1

T7

1542

T8

206

T9

218

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

136634412

1

T7

20

T8

188

T9

104

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30808

1

T8

16

T9

98

T24

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7718

1

T25

12

T26

8

T1

22

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

12308028

1

T8

592

T9

1844

T24

306

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4929008

1

T8

1636

T9

114

T25

254

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58534

1

T8

126

T9

78

T24

26

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14282

1

T8

10

T9

16

T25

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42232

1

T7

930

T9

8

T24

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1948

1

T26

8

T157

8

T158

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11960

1

T9

74

T24

56

T25

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2848

1

T26

76

T17

56

T30

142

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10408

1

T8

2

T25

14

T26

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2230

1

T1

2

T11

4

T159

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18986

1

T8

42

T25

62

T26

80

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5614

1

T1

42

T11

46

T14

88

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

34576

1

T8

2

T25

46

T1

32

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5628

1

T9

44

T25

8

T1

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31402

1

T8

62

T1

116

T3

866

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8844

1

T25

60

T1

48

T3

368

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32752

1

T8

24

T9

62

T24

22

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7908

1

T8

24

T25

38

T26

68

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

58378

1

T8

114

T9

88

T24

64

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13112

1

T8

80

T25

42

T26

82

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

79276

1

T8

2

T26

134

T4

2264

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5380

1

T1

16

T3

210

T72

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45486

1

T8

64

T26

236

T1

64

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12078

1

T3

350

T14

620

T16

120

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

47266

1

T8

12

T9

32

T24

34

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11532

1

T9

20

T25

28

T26

86

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

86046

1

T8

94

T24

122

T25

128

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20472

1

T9

78

T26

168

T3

526