Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311525286 1 T7 6678 T8 3228 T9 1784
auto[1] 402206 1 T8 426 T29 1086 T31 566


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311522332 1 T7 6678 T8 3142 T9 1784
auto[1] 405160 1 T8 512 T29 738 T31 276


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311421010 1 T7 6678 T8 2952 T9 1784
auto[1] 506482 1 T8 702 T29 1012 T31 610


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 287760222 1 T7 6678 T8 3320 T9 1784
auto[1] 24167270 1 T8 334 T29 3698 T31 166


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 189331802 1 T7 4304 T8 1546 T9 1766
auto[1] 122595690 1 T7 2374 T8 2108 T9 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 168413414 1 T7 4304 T8 680 T9 1766
auto[0] auto[0] auto[0] auto[0] auto[1] 118998242 1 T7 2374 T8 1984 T9 18
auto[0] auto[0] auto[0] auto[1] auto[0] 29174 1 T8 84 T31 66 T33 44
auto[0] auto[0] auto[0] auto[1] auto[1] 6618 1 T29 24 T31 26 T33 18
auto[0] auto[0] auto[1] auto[0] auto[0] 20319870 1 T8 204 T29 2448 T31 60
auto[0] auto[0] auto[1] auto[0] auto[1] 3490208 1 T29 184 T42 292 T1 2720
auto[0] auto[0] auto[1] auto[1] auto[0] 52316 1 T29 336 T31 26 T38 34
auto[0] auto[0] auto[1] auto[1] auto[1] 11884 1 T29 10 T1 90 T56 52
auto[0] auto[1] auto[0] auto[0] auto[0] 43970 1 T29 30 T33 14 T4 2206
auto[0] auto[1] auto[0] auto[0] auto[1] 1276 1 T29 14 T39 2 T40 4
auto[0] auto[1] auto[0] auto[1] auto[0] 11624 1 T29 60 T33 122 T38 160
auto[0] auto[1] auto[0] auto[1] auto[1] 2100 1 T29 54 T39 48 T40 98
auto[0] auto[1] auto[1] auto[0] auto[0] 11126 1 T42 20 T1 24 T54 10
auto[0] auto[1] auto[1] auto[0] auto[1] 3180 1 T1 4 T54 8 T2 2
auto[0] auto[1] auto[1] auto[1] auto[0] 21360 1 T42 94 T1 184 T2 252
auto[0] auto[1] auto[1] auto[1] auto[1] 4648 1 T1 72 T2 64 T13 62
auto[1] auto[0] auto[0] auto[0] auto[0] 52764 1 T8 14 T29 36 T31 50
auto[1] auto[0] auto[0] auto[0] auto[1] 3736 1 T8 52 T29 14 T31 16
auto[1] auto[0] auto[0] auto[1] auto[0] 33836 1 T8 90 T31 84 T33 54
auto[1] auto[0] auto[0] auto[1] auto[1] 8450 1 T29 84 T31 104 T33 132
auto[1] auto[0] auto[1] auto[0] auto[0] 28972 1 T8 34 T29 54 T31 8
auto[1] auto[0] auto[1] auto[0] auto[1] 7544 1 T29 20 T42 20 T1 6
auto[1] auto[0] auto[1] auto[1] auto[0] 52620 1 T29 168 T31 72 T1 220
auto[1] auto[0] auto[1] auto[1] auto[1] 12684 1 T29 56 T42 56 T1 70
auto[1] auto[1] auto[0] auto[0] auto[0] 92750 1 T8 150 T29 98 T31 88
auto[1] auto[1] auto[0] auto[0] auto[1] 5482 1 T8 72 T33 8 T38 4
auto[1] auto[1] auto[0] auto[1] auto[0] 45624 1 T8 194 T29 60 T31 188
auto[1] auto[1] auto[0] auto[1] auto[1] 11162 1 T38 68 T1 46 T20 42
auto[1] auto[1] auto[1] auto[0] auto[0] 41984 1 T8 38 T29 152 T38 28
auto[1] auto[1] auto[1] auto[0] auto[1] 10768 1 T29 36 T1 44 T22 90
auto[1] auto[1] auto[1] auto[1] auto[0] 80398 1 T8 58 T29 234 T38 116
auto[1] auto[1] auto[1] auto[1] auto[1] 17708 1 T1 62 T56 168 T2 212

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