| T798 |
/workspace/coverage/default/40.clkmgr_div_intersig_mubi.3658190005 |
|
|
Mar 31 01:15:05 PM PDT 24 |
Mar 31 01:15:06 PM PDT 24 |
92967604 ps |
| T799 |
/workspace/coverage/default/27.clkmgr_div_intersig_mubi.3511273777 |
|
|
Mar 31 01:14:28 PM PDT 24 |
Mar 31 01:14:29 PM PDT 24 |
16119910 ps |
| T800 |
/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3845709161 |
|
|
Mar 31 01:13:52 PM PDT 24 |
Mar 31 01:13:53 PM PDT 24 |
18936668 ps |
| T801 |
/workspace/coverage/default/26.clkmgr_alert_test.3464582716 |
|
|
Mar 31 01:14:29 PM PDT 24 |
Mar 31 01:14:30 PM PDT 24 |
16338638 ps |
| T802 |
/workspace/coverage/default/43.clkmgr_regwen.3658700538 |
|
|
Mar 31 01:15:14 PM PDT 24 |
Mar 31 01:15:21 PM PDT 24 |
1027810845 ps |
| T803 |
/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2394852572 |
|
|
Mar 31 01:15:05 PM PDT 24 |
Mar 31 01:15:06 PM PDT 24 |
21044854 ps |
| T804 |
/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.3296684977 |
|
|
Mar 31 01:13:22 PM PDT 24 |
Mar 31 01:20:38 PM PDT 24 |
49832549932 ps |
| T805 |
/workspace/coverage/default/5.clkmgr_stress_all.3945045709 |
|
|
Mar 31 01:13:35 PM PDT 24 |
Mar 31 01:13:45 PM PDT 24 |
2107029243 ps |
| T806 |
/workspace/coverage/default/40.clkmgr_frequency.896650380 |
|
|
Mar 31 01:15:00 PM PDT 24 |
Mar 31 01:15:06 PM PDT 24 |
927582964 ps |
| T807 |
/workspace/coverage/default/0.clkmgr_stress_all.178109933 |
|
|
Mar 31 01:13:16 PM PDT 24 |
Mar 31 01:13:35 PM PDT 24 |
2323430282 ps |
| T808 |
/workspace/coverage/default/37.clkmgr_regwen.3835853157 |
|
|
Mar 31 01:14:50 PM PDT 24 |
Mar 31 01:14:53 PM PDT 24 |
864860796 ps |
| T809 |
/workspace/coverage/default/2.clkmgr_alert_test.1122185901 |
|
|
Mar 31 01:13:21 PM PDT 24 |
Mar 31 01:13:22 PM PDT 24 |
32687788 ps |
| T810 |
/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2623226679 |
|
|
Mar 31 01:14:35 PM PDT 24 |
Mar 31 01:14:36 PM PDT 24 |
114334484 ps |
| T811 |
/workspace/coverage/default/20.clkmgr_smoke.3134732883 |
|
|
Mar 31 01:14:08 PM PDT 24 |
Mar 31 01:14:09 PM PDT 24 |
22289704 ps |
| T812 |
/workspace/coverage/default/48.clkmgr_trans.4274837905 |
|
|
Mar 31 01:15:16 PM PDT 24 |
Mar 31 01:15:18 PM PDT 24 |
26224510 ps |
| T813 |
/workspace/coverage/default/42.clkmgr_frequency.1352264556 |
|
|
Mar 31 01:15:04 PM PDT 24 |
Mar 31 01:15:07 PM PDT 24 |
320066040 ps |
| T814 |
/workspace/coverage/default/28.clkmgr_frequency.2509649221 |
|
|
Mar 31 01:14:27 PM PDT 24 |
Mar 31 01:14:38 PM PDT 24 |
1395384447 ps |
| T815 |
/workspace/coverage/default/13.clkmgr_regwen.3422382501 |
|
|
Mar 31 01:13:56 PM PDT 24 |
Mar 31 01:14:00 PM PDT 24 |
1041876951 ps |
| T816 |
/workspace/coverage/default/9.clkmgr_extclk.4034395944 |
|
|
Mar 31 01:13:47 PM PDT 24 |
Mar 31 01:13:48 PM PDT 24 |
16237645 ps |
| T817 |
/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.4124497973 |
|
|
Mar 31 01:15:08 PM PDT 24 |
Mar 31 01:15:10 PM PDT 24 |
26009394 ps |
| T818 |
/workspace/coverage/default/12.clkmgr_smoke.4284169088 |
|
|
Mar 31 01:13:54 PM PDT 24 |
Mar 31 01:13:55 PM PDT 24 |
21355975 ps |
| T819 |
/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.3344201850 |
|
|
Mar 31 01:14:19 PM PDT 24 |
Mar 31 01:30:22 PM PDT 24 |
156644094731 ps |
| T820 |
/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.2714872875 |
|
|
Mar 31 01:15:19 PM PDT 24 |
Mar 31 01:15:20 PM PDT 24 |
55715391 ps |
| T821 |
/workspace/coverage/default/45.clkmgr_frequency.4071144283 |
|
|
Mar 31 01:15:08 PM PDT 24 |
Mar 31 01:15:26 PM PDT 24 |
2115920367 ps |
| T822 |
/workspace/coverage/default/31.clkmgr_extclk.3280840614 |
|
|
Mar 31 01:14:37 PM PDT 24 |
Mar 31 01:14:38 PM PDT 24 |
19263624 ps |
| T823 |
/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.3859008381 |
|
|
Mar 31 01:14:31 PM PDT 24 |
Mar 31 01:24:51 PM PDT 24 |
99355607310 ps |
| T824 |
/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2485888219 |
|
|
Mar 31 01:14:35 PM PDT 24 |
Mar 31 01:14:36 PM PDT 24 |
17902544 ps |
| T825 |
/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.295610095 |
|
|
Mar 31 01:14:50 PM PDT 24 |
Mar 31 01:14:51 PM PDT 24 |
35099195 ps |
| T826 |
/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.240077266 |
|
|
Mar 31 01:15:16 PM PDT 24 |
Mar 31 01:15:17 PM PDT 24 |
17462798 ps |
| T827 |
/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.3264364001 |
|
|
Mar 31 01:14:46 PM PDT 24 |
Mar 31 01:14:47 PM PDT 24 |
20741680 ps |
| T828 |
/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2965159153 |
|
|
Mar 31 01:13:57 PM PDT 24 |
Mar 31 01:14:00 PM PDT 24 |
19110865 ps |
| T829 |
/workspace/coverage/default/12.clkmgr_regwen.2428410075 |
|
|
Mar 31 01:13:56 PM PDT 24 |
Mar 31 01:14:03 PM PDT 24 |
1295428324 ps |
| T830 |
/workspace/coverage/default/13.clkmgr_clk_status.4137985057 |
|
|
Mar 31 01:13:54 PM PDT 24 |
Mar 31 01:13:55 PM PDT 24 |
47324621 ps |
| T831 |
/workspace/coverage/default/46.clkmgr_alert_test.1092368168 |
|
|
Mar 31 01:15:17 PM PDT 24 |
Mar 31 01:15:18 PM PDT 24 |
35521586 ps |
| T832 |
/workspace/coverage/default/18.clkmgr_alert_test.1152578793 |
|
|
Mar 31 01:14:02 PM PDT 24 |
Mar 31 01:14:04 PM PDT 24 |
17088145 ps |
| T833 |
/workspace/coverage/default/46.clkmgr_trans.3142569054 |
|
|
Mar 31 01:15:09 PM PDT 24 |
Mar 31 01:15:11 PM PDT 24 |
15924032 ps |
| T834 |
/workspace/coverage/default/33.clkmgr_frequency.1177335367 |
|
|
Mar 31 01:14:40 PM PDT 24 |
Mar 31 01:14:43 PM PDT 24 |
323026920 ps |
| T835 |
/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.696409134 |
|
|
Mar 31 01:13:52 PM PDT 24 |
Mar 31 01:13:53 PM PDT 24 |
27040086 ps |
| T836 |
/workspace/coverage/default/38.clkmgr_peri.297522373 |
|
|
Mar 31 01:14:52 PM PDT 24 |
Mar 31 01:14:53 PM PDT 24 |
22993855 ps |
| T837 |
/workspace/coverage/default/2.clkmgr_stress_all.2303851064 |
|
|
Mar 31 01:13:21 PM PDT 24 |
Mar 31 01:13:29 PM PDT 24 |
1816343174 ps |
| T838 |
/workspace/coverage/default/4.clkmgr_stress_all.3142974083 |
|
|
Mar 31 01:13:37 PM PDT 24 |
Mar 31 01:14:29 PM PDT 24 |
7308857513 ps |
| T839 |
/workspace/coverage/default/37.clkmgr_frequency.3568843773 |
|
|
Mar 31 01:14:47 PM PDT 24 |
Mar 31 01:15:00 PM PDT 24 |
1763485349 ps |
| T840 |
/workspace/coverage/default/18.clkmgr_peri.601678303 |
|
|
Mar 31 01:13:57 PM PDT 24 |
Mar 31 01:13:59 PM PDT 24 |
15246286 ps |
| T841 |
/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2638183392 |
|
|
Mar 31 01:13:57 PM PDT 24 |
Mar 31 01:13:59 PM PDT 24 |
23305779 ps |
| T842 |
/workspace/coverage/default/47.clkmgr_trans.3989424263 |
|
|
Mar 31 01:15:24 PM PDT 24 |
Mar 31 01:15:25 PM PDT 24 |
16261592 ps |
| T843 |
/workspace/coverage/default/5.clkmgr_smoke.3881879047 |
|
|
Mar 31 01:13:41 PM PDT 24 |
Mar 31 01:13:43 PM PDT 24 |
52916308 ps |
| T844 |
/workspace/coverage/default/5.clkmgr_regwen.1728183460 |
|
|
Mar 31 01:13:36 PM PDT 24 |
Mar 31 01:13:40 PM PDT 24 |
1014186055 ps |
| T845 |
/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3165923373 |
|
|
Mar 31 01:15:01 PM PDT 24 |
Mar 31 01:15:02 PM PDT 24 |
54676746 ps |
| T846 |
/workspace/coverage/default/20.clkmgr_clk_status.3028125022 |
|
|
Mar 31 01:14:03 PM PDT 24 |
Mar 31 01:14:04 PM PDT 24 |
15572787 ps |
| T847 |
/workspace/coverage/default/45.clkmgr_smoke.2801188889 |
|
|
Mar 31 01:15:13 PM PDT 24 |
Mar 31 01:15:14 PM PDT 24 |
20535377 ps |
| T848 |
/workspace/coverage/default/40.clkmgr_stress_all.1275099662 |
|
|
Mar 31 01:15:02 PM PDT 24 |
Mar 31 01:15:30 PM PDT 24 |
5173168899 ps |
| T849 |
/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2571792940 |
|
|
Mar 31 01:15:07 PM PDT 24 |
Mar 31 01:15:09 PM PDT 24 |
14113758 ps |
| T850 |
/workspace/coverage/default/24.clkmgr_frequency_timeout.1624437111 |
|
|
Mar 31 01:14:20 PM PDT 24 |
Mar 31 01:14:29 PM PDT 24 |
2435186968 ps |
| T851 |
/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1050544469 |
|
|
Mar 31 01:14:23 PM PDT 24 |
Mar 31 01:14:24 PM PDT 24 |
33049175 ps |
| T852 |
/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2909330495 |
|
|
Mar 31 01:13:45 PM PDT 24 |
Mar 31 01:13:46 PM PDT 24 |
80419909 ps |
| T853 |
/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1992655289 |
|
|
Mar 31 12:27:37 PM PDT 24 |
Mar 31 12:27:38 PM PDT 24 |
152879538 ps |
| T854 |
/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2480684219 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
33213987 ps |
| T114 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1436220738 |
|
|
Mar 31 12:27:39 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
443157118 ps |
| T855 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.4241153886 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
43607802 ps |
| T856 |
/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3086334378 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:27:58 PM PDT 24 |
23180463 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1361067144 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
309245393 ps |
| T116 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.4201646181 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:36 PM PDT 24 |
129108512 ps |
| T857 |
/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3741860780 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
15860392 ps |
| T858 |
/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3944155419 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
106901753 ps |
| T859 |
/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.765478996 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
21024131 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1798785123 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
23927831 ps |
| T61 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3820308156 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:26 PM PDT 24 |
191187251 ps |
| T860 |
/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1476642441 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:29:19 PM PDT 24 |
87441796 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1088862908 |
|
|
Mar 31 12:27:19 PM PDT 24 |
Mar 31 12:27:21 PM PDT 24 |
287614852 ps |
| T861 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3605090850 |
|
|
Mar 31 12:27:17 PM PDT 24 |
Mar 31 12:27:19 PM PDT 24 |
77786487 ps |
| T862 |
/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1372273484 |
|
|
Mar 31 12:27:31 PM PDT 24 |
Mar 31 12:27:32 PM PDT 24 |
20855045 ps |
| T863 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2943740760 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
14447799 ps |
| T864 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3139779016 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
82160863 ps |
| T96 |
/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.4094218124 |
|
|
Mar 31 12:28:46 PM PDT 24 |
Mar 31 12:28:47 PM PDT 24 |
49326673 ps |
| T865 |
/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3476491204 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
12874005 ps |
| T62 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3368858065 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
256676586 ps |
| T866 |
/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1142375064 |
|
|
Mar 31 12:27:36 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
51576917 ps |
| T867 |
/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.904312243 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:41 PM PDT 24 |
22339810 ps |
| T868 |
/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2108912410 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
10142312 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3532306746 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
104507986 ps |
| T869 |
/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1403366768 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
14259714 ps |
| T870 |
/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.481114997 |
|
|
Mar 31 12:29:18 PM PDT 24 |
Mar 31 12:29:19 PM PDT 24 |
32678774 ps |
| T97 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.528929076 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:02 PM PDT 24 |
121236379 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3407810759 |
|
|
Mar 31 12:28:46 PM PDT 24 |
Mar 31 12:28:48 PM PDT 24 |
196093231 ps |
| T119 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2152526054 |
|
|
Mar 31 12:27:47 PM PDT 24 |
Mar 31 12:27:50 PM PDT 24 |
139701010 ps |
| T871 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2711510226 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
61631354 ps |
| T63 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1961834644 |
|
|
Mar 31 12:27:48 PM PDT 24 |
Mar 31 12:27:50 PM PDT 24 |
63459482 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3809637839 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:07 PM PDT 24 |
15812983 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2260824722 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:30 PM PDT 24 |
56173728 ps |
| T872 |
/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1906866915 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
125186401 ps |
| T126 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1244575758 |
|
|
Mar 31 12:27:19 PM PDT 24 |
Mar 31 12:27:21 PM PDT 24 |
57352614 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.113359528 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:24 PM PDT 24 |
21242319 ps |
| T873 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2061605199 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:35 PM PDT 24 |
82347413 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1685322863 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
647618106 ps |
| T874 |
/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.329126261 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
13682603 ps |
| T120 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2731117219 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:29 PM PDT 24 |
140558447 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3491158305 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
47402777 ps |
| T875 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3090886728 |
|
|
Mar 31 12:27:25 PM PDT 24 |
Mar 31 12:27:28 PM PDT 24 |
43602357 ps |
| T876 |
/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3007804347 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
16836512 ps |
| T877 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.318943129 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
18243648 ps |
| T878 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2723309425 |
|
|
Mar 31 12:27:39 PM PDT 24 |
Mar 31 12:27:41 PM PDT 24 |
74376722 ps |
| T879 |
/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3521096226 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
57712944 ps |
| T880 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3368730783 |
|
|
Mar 31 12:27:48 PM PDT 24 |
Mar 31 12:27:49 PM PDT 24 |
18008112 ps |
| T881 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3820679286 |
|
|
Mar 31 12:27:04 PM PDT 24 |
Mar 31 12:27:05 PM PDT 24 |
123383619 ps |
| T74 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2400558993 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
56744424 ps |
| T882 |
/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2605879670 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:51 PM PDT 24 |
28082718 ps |
| T883 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3628323559 |
|
|
Mar 31 12:27:25 PM PDT 24 |
Mar 31 12:27:26 PM PDT 24 |
21043849 ps |
| T884 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.550433620 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:36 PM PDT 24 |
37555300 ps |
| T885 |
/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3133963716 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
49820317 ps |
| T886 |
/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2433888378 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
23345484 ps |
| T887 |
/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3500851618 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:51 PM PDT 24 |
14524478 ps |
| T888 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.33139383 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:06 PM PDT 24 |
338978706 ps |
| T117 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3917077661 |
|
|
Mar 31 12:28:23 PM PDT 24 |
Mar 31 12:28:26 PM PDT 24 |
236190359 ps |
| T889 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3379171046 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
56616013 ps |
| T890 |
/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2193635924 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
21357800 ps |
| T67 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3727665844 |
|
|
Mar 31 12:27:08 PM PDT 24 |
Mar 31 12:27:10 PM PDT 24 |
80370195 ps |
| T891 |
/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.3109931927 |
|
|
Mar 31 12:27:15 PM PDT 24 |
Mar 31 12:27:16 PM PDT 24 |
14114957 ps |
| T892 |
/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3415298843 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
74048889 ps |
| T75 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2638491761 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
112736938 ps |
| T893 |
/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1861633340 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
78610519 ps |
| T894 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1872213365 |
|
|
Mar 31 12:27:42 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
28673913 ps |
| T895 |
/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.2482701575 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:40 PM PDT 24 |
423530502 ps |
| T73 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.133951271 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
115781747 ps |
| T896 |
/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2269024711 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:26 PM PDT 24 |
62678714 ps |
| T897 |
/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2839370376 |
|
|
Mar 31 12:27:29 PM PDT 24 |
Mar 31 12:27:32 PM PDT 24 |
373785181 ps |
| T898 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2554507798 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:08 PM PDT 24 |
43080178 ps |
| T899 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1735639974 |
|
|
Mar 31 12:27:38 PM PDT 24 |
Mar 31 12:27:41 PM PDT 24 |
195003288 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3549895342 |
|
|
Mar 31 12:29:23 PM PDT 24 |
Mar 31 12:29:26 PM PDT 24 |
223327249 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1280176173 |
|
|
Mar 31 12:27:27 PM PDT 24 |
Mar 31 12:27:30 PM PDT 24 |
350998228 ps |
| T900 |
/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3137020967 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
41781183 ps |
| T901 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3558397953 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
101920050 ps |
| T902 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2742732208 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
31233788 ps |
| T903 |
/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2501006417 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:27:57 PM PDT 24 |
13123128 ps |
| T141 |
/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1104859935 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
353820021 ps |
| T904 |
/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2712683744 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
285215944 ps |
| T71 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1376323003 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:09 PM PDT 24 |
371658605 ps |
| T905 |
/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3268001741 |
|
|
Mar 31 12:27:42 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
52546938 ps |
| T906 |
/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.181186602 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
16908281 ps |
| T907 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.3070689183 |
|
|
Mar 31 12:26:59 PM PDT 24 |
Mar 31 12:27:01 PM PDT 24 |
268748890 ps |
| T908 |
/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.4076127310 |
|
|
Mar 31 12:27:48 PM PDT 24 |
Mar 31 12:27:49 PM PDT 24 |
31531412 ps |
| T909 |
/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.575820380 |
|
|
Mar 31 12:27:47 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
11921963 ps |
| T910 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.880532139 |
|
|
Mar 31 12:27:21 PM PDT 24 |
Mar 31 12:27:24 PM PDT 24 |
127711556 ps |
| T72 |
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2294698250 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:34 PM PDT 24 |
68420080 ps |
| T135 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3630306394 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
80219025 ps |
| T118 |
/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2729984895 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:39 PM PDT 24 |
385750310 ps |
| T911 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1202333708 |
|
|
Mar 31 12:26:55 PM PDT 24 |
Mar 31 12:26:56 PM PDT 24 |
127624679 ps |
| T136 |
/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3340137637 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:36 PM PDT 24 |
182176074 ps |
| T912 |
/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2701422072 |
|
|
Mar 31 12:27:29 PM PDT 24 |
Mar 31 12:27:32 PM PDT 24 |
183415537 ps |
| T913 |
/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.198115462 |
|
|
Mar 31 12:28:44 PM PDT 24 |
Mar 31 12:28:46 PM PDT 24 |
110628240 ps |
| T125 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1489875030 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
131816642 ps |
| T914 |
/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.3943444013 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
28748797 ps |
| T915 |
/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.722873455 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
12734824 ps |
| T916 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1340792624 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:07 PM PDT 24 |
16589958 ps |
| T917 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2637864823 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
273056789 ps |
| T144 |
/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3563778108 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:44 PM PDT 24 |
108196647 ps |
| T918 |
/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3705749948 |
|
|
Mar 31 12:27:01 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
33154984 ps |
| T919 |
/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2246848203 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:34 PM PDT 24 |
28874436 ps |
| T137 |
/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.201089986 |
|
|
Mar 31 12:28:26 PM PDT 24 |
Mar 31 12:28:29 PM PDT 24 |
370658250 ps |
| T920 |
/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1332307657 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
34505610 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.787060379 |
|
|
Mar 31 12:28:44 PM PDT 24 |
Mar 31 12:28:46 PM PDT 24 |
132128063 ps |
| T921 |
/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1789512520 |
|
|
Mar 31 12:27:25 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
105449393 ps |
| T922 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1318974552 |
|
|
Mar 31 12:28:46 PM PDT 24 |
Mar 31 12:28:47 PM PDT 24 |
45225700 ps |
| T923 |
/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3147146576 |
|
|
Mar 31 12:27:39 PM PDT 24 |
Mar 31 12:27:40 PM PDT 24 |
38406090 ps |
| T924 |
/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3896124914 |
|
|
Mar 31 12:27:49 PM PDT 24 |
Mar 31 12:27:51 PM PDT 24 |
15683215 ps |
| T138 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.531728967 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:08 PM PDT 24 |
145079916 ps |
| T925 |
/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1746826972 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
734541568 ps |
| T142 |
/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.445186542 |
|
|
Mar 31 12:27:33 PM PDT 24 |
Mar 31 12:27:35 PM PDT 24 |
145893613 ps |
| T926 |
/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2496918229 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
25105969 ps |
| T927 |
/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2304829704 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
39992109 ps |
| T928 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.459054479 |
|
|
Mar 31 12:27:45 PM PDT 24 |
Mar 31 12:27:46 PM PDT 24 |
33462620 ps |
| T139 |
/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.51008216 |
|
|
Mar 31 12:27:37 PM PDT 24 |
Mar 31 12:27:38 PM PDT 24 |
50658468 ps |
| T929 |
/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.45349890 |
|
|
Mar 31 12:27:36 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
14209781 ps |
| T930 |
/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2563771466 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
85440544 ps |
| T931 |
/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1072500053 |
|
|
Mar 31 12:27:07 PM PDT 24 |
Mar 31 12:27:08 PM PDT 24 |
26222583 ps |
| T932 |
/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1263555147 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
27845287 ps |
| T933 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.4028075201 |
|
|
Mar 31 12:27:17 PM PDT 24 |
Mar 31 12:27:20 PM PDT 24 |
276838355 ps |
| T934 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2423088127 |
|
|
Mar 31 12:27:08 PM PDT 24 |
Mar 31 12:27:09 PM PDT 24 |
99352117 ps |
| T143 |
/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1259855115 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
156703757 ps |
| T935 |
/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2877441437 |
|
|
Mar 31 12:27:38 PM PDT 24 |
Mar 31 12:27:41 PM PDT 24 |
271833797 ps |
| T936 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.933991241 |
|
|
Mar 31 12:27:32 PM PDT 24 |
Mar 31 12:27:34 PM PDT 24 |
301131884 ps |
| T937 |
/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.929660728 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:35 PM PDT 24 |
55309472 ps |
| T938 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3499601807 |
|
|
Mar 31 12:27:00 PM PDT 24 |
Mar 31 12:27:04 PM PDT 24 |
218672197 ps |
| T939 |
/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1758048662 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
14142723 ps |
| T940 |
/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.4257372158 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:51 PM PDT 24 |
19249729 ps |
| T941 |
/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2835559609 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
28474190 ps |
| T942 |
/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1725808481 |
|
|
Mar 31 12:27:20 PM PDT 24 |
Mar 31 12:27:22 PM PDT 24 |
62597075 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3808940329 |
|
|
Mar 31 12:27:36 PM PDT 24 |
Mar 31 12:27:38 PM PDT 24 |
112258668 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1133523817 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:49 PM PDT 24 |
94778163 ps |
| T945 |
/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.233899259 |
|
|
Mar 31 12:27:48 PM PDT 24 |
Mar 31 12:27:50 PM PDT 24 |
132124466 ps |
| T946 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3332709860 |
|
|
Mar 31 12:27:34 PM PDT 24 |
Mar 31 12:27:35 PM PDT 24 |
81392752 ps |
| T947 |
/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.714894446 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:28:04 PM PDT 24 |
15428255 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.4084240789 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
100711784 ps |
| T949 |
/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1111409391 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
18215882 ps |
| T950 |
/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.4187915540 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
37439503 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2244453486 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
68133041 ps |
| T952 |
/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2830166679 |
|
|
Mar 31 12:27:56 PM PDT 24 |
Mar 31 12:27:57 PM PDT 24 |
12727534 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3027494489 |
|
|
Mar 31 12:29:21 PM PDT 24 |
Mar 31 12:29:23 PM PDT 24 |
62112666 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.270994018 |
|
|
Mar 31 12:27:39 PM PDT 24 |
Mar 31 12:27:40 PM PDT 24 |
15387737 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.972444650 |
|
|
Mar 31 12:28:27 PM PDT 24 |
Mar 31 12:28:28 PM PDT 24 |
20484242 ps |
| T956 |
/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.553890520 |
|
|
Mar 31 12:27:32 PM PDT 24 |
Mar 31 12:27:36 PM PDT 24 |
435036263 ps |
| T957 |
/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1561346683 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
40868572 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.11407696 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
24416570 ps |
| T146 |
/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2982598605 |
|
|
Mar 31 12:27:06 PM PDT 24 |
Mar 31 12:27:09 PM PDT 24 |
255825698 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.157709659 |
|
|
Mar 31 12:29:38 PM PDT 24 |
Mar 31 12:29:42 PM PDT 24 |
329153080 ps |
| T960 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.4055887073 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
397517328 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2202385806 |
|
|
Mar 31 12:27:55 PM PDT 24 |
Mar 31 12:27:56 PM PDT 24 |
22422587 ps |
| T962 |
/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1463929773 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:53 PM PDT 24 |
11379114 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1355303606 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
12045758 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3786141907 |
|
|
Mar 31 12:27:12 PM PDT 24 |
Mar 31 12:27:16 PM PDT 24 |
347896283 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3458912391 |
|
|
Mar 31 12:27:46 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
149616370 ps |
| T966 |
/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3709091577 |
|
|
Mar 31 12:27:54 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
98921697 ps |
| T967 |
/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.128214245 |
|
|
Mar 31 12:28:24 PM PDT 24 |
Mar 31 12:28:25 PM PDT 24 |
13645309 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1531564877 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:28:04 PM PDT 24 |
39166360 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.814608687 |
|
|
Mar 31 12:27:41 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
16114685 ps |
| T122 |
/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1504217965 |
|
|
Mar 31 12:28:46 PM PDT 24 |
Mar 31 12:28:48 PM PDT 24 |
119985229 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3913176864 |
|
|
Mar 31 12:27:11 PM PDT 24 |
Mar 31 12:27:13 PM PDT 24 |
238935267 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.383697262 |
|
|
Mar 31 12:27:21 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
560403911 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4018772118 |
|
|
Mar 31 12:27:11 PM PDT 24 |
Mar 31 12:27:15 PM PDT 24 |
273527970 ps |
| T140 |
/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3214106462 |
|
|
Mar 31 12:27:10 PM PDT 24 |
Mar 31 12:27:11 PM PDT 24 |
122464705 ps |
| T973 |
/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.959508053 |
|
|
Mar 31 12:27:50 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
39301809 ps |
| T974 |
/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3526620203 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
32809508 ps |
| T975 |
/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3198233064 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:52 PM PDT 24 |
31391661 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.735341263 |
|
|
Mar 31 12:27:02 PM PDT 24 |
Mar 31 12:27:03 PM PDT 24 |
70070517 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3565170305 |
|
|
Mar 31 12:27:20 PM PDT 24 |
Mar 31 12:27:22 PM PDT 24 |
53526509 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2350827644 |
|
|
Mar 31 12:27:23 PM PDT 24 |
Mar 31 12:27:25 PM PDT 24 |
24249057 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3821172798 |
|
|
Mar 31 12:27:26 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
41206166 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.727317305 |
|
|
Mar 31 12:29:24 PM PDT 24 |
Mar 31 12:29:26 PM PDT 24 |
185562586 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3714993383 |
|
|
Mar 31 12:27:37 PM PDT 24 |
Mar 31 12:27:38 PM PDT 24 |
24347082 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.4209732084 |
|
|
Mar 31 12:28:46 PM PDT 24 |
Mar 31 12:28:47 PM PDT 24 |
78291157 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4102355573 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:37 PM PDT 24 |
45609611 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1717173371 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
24908882 ps |
| T985 |
/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3658639974 |
|
|
Mar 31 12:27:53 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
85641477 ps |
| T986 |
/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1029024857 |
|
|
Mar 31 12:27:40 PM PDT 24 |
Mar 31 12:27:42 PM PDT 24 |
228352550 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.79829335 |
|
|
Mar 31 12:27:20 PM PDT 24 |
Mar 31 12:27:21 PM PDT 24 |
38831266 ps |
| T988 |
/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.832191377 |
|
|
Mar 31 12:27:38 PM PDT 24 |
Mar 31 12:27:40 PM PDT 24 |
95378765 ps |
| T989 |
/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1778615525 |
|
|
Mar 31 12:27:47 PM PDT 24 |
Mar 31 12:27:48 PM PDT 24 |
57359873 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2003850636 |
|
|
Mar 31 12:27:44 PM PDT 24 |
Mar 31 12:27:47 PM PDT 24 |
235822567 ps |
| T991 |
/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3731921688 |
|
|
Mar 31 12:28:10 PM PDT 24 |
Mar 31 12:28:11 PM PDT 24 |
48005254 ps |
| T992 |
/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2135498501 |
|
|
Mar 31 12:27:29 PM PDT 24 |
Mar 31 12:27:30 PM PDT 24 |
26311994 ps |
| T993 |
/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.192928540 |
|
|
Mar 31 12:28:12 PM PDT 24 |
Mar 31 12:28:13 PM PDT 24 |
31611063 ps |
| T147 |
/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1157636405 |
|
|
Mar 31 12:27:58 PM PDT 24 |
Mar 31 12:28:00 PM PDT 24 |
266176905 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.406870602 |
|
|
Mar 31 12:27:39 PM PDT 24 |
Mar 31 12:27:40 PM PDT 24 |
56368533 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.707615725 |
|
|
Mar 31 12:27:35 PM PDT 24 |
Mar 31 12:27:36 PM PDT 24 |
16387169 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2940751113 |
|
|
Mar 31 12:27:28 PM PDT 24 |
Mar 31 12:27:31 PM PDT 24 |
150062941 ps |
| T997 |
/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2859545189 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:49 PM PDT 24 |
31967545 ps |
| T998 |
/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3861505014 |
|
|
Mar 31 12:27:42 PM PDT 24 |
Mar 31 12:27:43 PM PDT 24 |
17367657 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3442749094 |
|
|
Mar 31 12:27:24 PM PDT 24 |
Mar 31 12:27:27 PM PDT 24 |
196624177 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3073301481 |
|
|
Mar 31 12:27:52 PM PDT 24 |
Mar 31 12:27:55 PM PDT 24 |
105925349 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.465323249 |
|
|
Mar 31 12:27:43 PM PDT 24 |
Mar 31 12:27:45 PM PDT 24 |
88712889 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4175372016 |
|
|
Mar 31 12:27:51 PM PDT 24 |
Mar 31 12:27:54 PM PDT 24 |
105509093 ps |