Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335323892

1

T5

1480

T6

3944

T7

2848

auto[1]

451608

1

T6

978

T4

1322

T20

70

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335370234

1

T5

1480

T6

4150

T7

2848

auto[1]

405266

1

T6

772

T4

852

T20

68

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335261908

1

T5

1480

T6

4014

T7

2848

auto[1]

513592

1

T6

908

T4

1270

T20

94

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314616332

1

T5

1480

T6

980

T7

2848

auto[1]

21159168

1

T6

3942

T4

2934

T20

2036

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195533374

1

T5

1462

T6

2306

T7

394

auto[1]

140242126

1

T5

18

T6

2616

T7

2454

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

181032896

1

T5

1462

T6

420

T7

394

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133260400

1

T5

18

T6

158

T7

2454

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32020

1

T6

40

T4

152

T20

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9478

1

T22

48

T11

30

T123

20

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

13904578

1

T6

920

T4

1732

T20

2002

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6847304

1

T6

2046

T4

352

T3

194

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59816

1

T6

220

T4

98

T22

66

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14732

1

T6

38

T4

4

T3

82

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40206

1

T4

22

T125

16

T126

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1146

1

T12

32

T15

38

T16

22

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12250

1

T4

56

T125

54

T126

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3262

1

T12

96

T15

142

T16

142

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10870

1

T6

88

T4

32

T22

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3194

1

T12

60

T15

114

T16

100

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22570

1

T6

84

T22

42

T123

100

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7186

1

T12

98

T16

84

T96

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48696

1

T6

28

T4

48

T3

48

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4630

1

T4

34

T12

28

T109

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32112

1

T6

68

T4

98

T3

56

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8464

1

T4

48

T12

96

T109

54

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32032

1

T6

48

T4

4

T20

26

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8798

1

T6

44

T4

20

T3

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

58256

1

T6

66

T4

108

T3

70

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16022

1

T6

54

T4

168

T122

46

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61136

1

T6

54

T4

38

T20

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7026

1

T6

32

T4

14

T22

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48096

1

T6

180

T4

228

T20

58

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14514

1

T4

46

T22

66

T125

36

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48452

1

T6

44

T4

64

T20

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12528

1

T6

62

T4

36

T11

96

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

89388

1

T6

46

T4

256

T22

188

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23442

1

T6

182

T4

60

T11

214