26b0ee226| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 6.000s | 197.230us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 3.000s | 46.603us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 5.000s | 242.967us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 21.000s | 909.412us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 6.000s | 145.509us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 5.000s | 31.025us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 242.967us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 6.000s | 145.509us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 8.000s | 317.294us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 |
| V2 | cmds | csrng_cmds | 1.750m | 8.581ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 1.750m | 8.581ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 2.700m | 13.000ms | 47 | 50 | 94.00 |
| V2 | intr_test | csrng_intr_test | 4.000s | 78.770us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 6.000s | 44.338us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 14.000s | 533.761us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 14.000s | 533.761us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 3.000s | 46.603us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 242.967us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 145.509us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 7.000s | 477.850us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 3.000s | 46.603us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 242.967us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 145.509us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 7.000s | 477.850us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1431 | 1440 | 99.38 | |||
| V2S | tl_intg_err | csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 13.000s | 1.044ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 6.000s | 14.945us | 50 | 50 | 100.00 |
| csrng_csr_rw | 5.000s | 242.967us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 8.000s | 317.294us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 2.700m | 13.000ms | 47 | 50 | 94.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 8.000s | 317.294us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 2.700m | 13.000ms | 47 | 50 | 94.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 8.000s | 317.294us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 13.000s | 1.044ms | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| csrng_sec_cm | 7.000s | 264.100us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 8.000s | 204.232us | 200 | 200 | 100.00 |
| csrng_err | 6.000s | 26.819us | 494 | 500 | 98.80 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.001h | 35.972ms | 4 | 50 | 8.00 |
| V3 | TOTAL | 4 | 50 | 8.00 | |||
| TOTAL | 1615 | 1670 | 96.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 7 | 77.78 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.82 | 93.34 | 84.27 | 95.41 | 86.43 | 92.29 | 98.18 | 97.50 | 95.17 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 23 failures:
3.csrng_stress_all_with_rand_reset.3446162350
Line 244, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003775013 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xdd7b9814) == 0x6
UVM_INFO @ 10003775013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.csrng_stress_all_with_rand_reset.2502506591
Line 239, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10011079165 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x167d9494) == 0x6
UVM_INFO @ 10011079165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 18 failures:
1.csrng_stress_all_with_rand_reset.3277943219
Line 379, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20645337259 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xa5af94) == 0x6
UVM_INFO @ 20645337259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.3622695300
Line 594, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 26107417762 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x6fd1af94) == 0x6
UVM_INFO @ 26107417762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:
81.csrng_err.3587953138
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/81.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5169790 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5169790 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5169790 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 5169790 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 5169790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
225.csrng_err.2730628187
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/225.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2690148 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2690148 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2690148 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 2690148 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 2690148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:
5.csrng_stress_all_with_rand_reset.3147077611
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 10303538 PS + 13
Verilog Stack Trace:
42.csrng_stress_all_with_rand_reset.3963243000
Line 232, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 7591956 PS + 14
Verilog Stack Trace:
UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
11.csrng_stress_all_with_rand_reset.95152921
Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13595959929 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
UVM_INFO @ 13595959929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.csrng_stress_all_with_rand_reset.651576592
Line 404, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/48.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20316138255 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 20316138255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
31.csrng_stress_all.1114041443
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_stress_all/latest/run.log
UVM_ERROR @ 232470912 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 232470912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.csrng_stress_all.2995168421
Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_stress_all/latest/run.log
UVM_ERROR @ 2068860746 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 2068860746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 2 failures:
288.csrng_err.882595269
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/288.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 5711841 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 5711841 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5711841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
359.csrng_err.3109891376
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/359.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2961016 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2961016 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2961016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
22.csrng_stress_all.3797222714
Line 260, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all/latest/run.log
UVM_ERROR @ 258115241 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 258115241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
46.csrng_stress_all_with_rand_reset.3110069526
Line 773, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 35971573596 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 35971573596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---