CSRNG Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 5.000s 197.980us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 3.000s 35.112us 5 5 100.00
V1 csr_rw csrng_csr_rw 4.000s 15.217us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 35.000s 2.542ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 4.000s 90.830us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 6.000s 189.008us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 4.000s 15.217us 20 20 100.00
csrng_csr_aliasing 4.000s 90.830us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 7.000s 49.648us 200 200 100.00
V2 alerts csrng_alert 8.000s 273.227us 500 500 100.00
V2 err csrng_err 6.000s 22.042us 482 500 96.40
V2 cmds csrng_cmds 1.350m 8.226ms 50 50 100.00
V2 life cycle csrng_cmds 1.350m 8.226ms 50 50 100.00
V2 stress_all csrng_stress_all 1.383m 3.881ms 48 50 96.00
V2 intr_test csrng_intr_test 4.000s 15.643us 50 50 100.00
V2 alert_test csrng_alert_test 5.000s 162.410us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 15.000s 546.873us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 15.000s 546.873us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 3.000s 35.112us 5 5 100.00
csrng_csr_rw 4.000s 15.217us 20 20 100.00
csrng_csr_aliasing 4.000s 90.830us 5 5 100.00
csrng_same_csr_outstanding 6.000s 270.045us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 3.000s 35.112us 5 5 100.00
csrng_csr_rw 4.000s 15.217us 20 20 100.00
csrng_csr_aliasing 4.000s 90.830us 5 5 100.00
csrng_same_csr_outstanding 6.000s 270.045us 20 20 100.00
V2 TOTAL 1420 1440 98.61
V2S tl_intg_err csrng_sec_cm 8.000s 103.163us 5 5 100.00
csrng_tl_intg_err 12.000s 833.729us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 6.000s 11.413us 50 50 100.00
csrng_csr_rw 4.000s 15.217us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 8.000s 273.227us 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 1.383m 3.881ms 48 50 96.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 8.000s 273.227us 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
V2S sec_cm_constants_lc_gated csrng_stress_all 1.383m 3.881ms 48 50 96.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 8.000s 273.227us 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 12.000s 833.729us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
csrng_sec_cm 8.000s 103.163us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 7.000s 49.648us 200 200 100.00
csrng_err 6.000s 22.042us 482 500 96.40
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 1.032h 39.461ms 7 50 14.00
V3 TOTAL 7 50 14.00
TOTAL 1607 1670 96.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 7 77.78
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.86 93.35 84.31 95.43 86.47 92.29 100.00 97.50 95.64

Failure Buckets

Past Results