94eb0df12
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | csrng_smoke | 5.000s | 197.980us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | csrng_csr_hw_reset | 3.000s | 35.112us | 5 | 5 | 100.00 |
V1 | csr_rw | csrng_csr_rw | 4.000s | 15.217us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | csrng_csr_bit_bash | 35.000s | 2.542ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | csrng_csr_aliasing | 4.000s | 90.830us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 189.008us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 15.217us | 20 | 20 | 100.00 |
csrng_csr_aliasing | 4.000s | 90.830us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | interrupts | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
V2 | alerts | csrng_alert | 8.000s | 273.227us | 500 | 500 | 100.00 |
V2 | err | csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 |
V2 | cmds | csrng_cmds | 1.350m | 8.226ms | 50 | 50 | 100.00 |
V2 | life cycle | csrng_cmds | 1.350m | 8.226ms | 50 | 50 | 100.00 |
V2 | stress_all | csrng_stress_all | 1.383m | 3.881ms | 48 | 50 | 96.00 |
V2 | intr_test | csrng_intr_test | 4.000s | 15.643us | 50 | 50 | 100.00 |
V2 | alert_test | csrng_alert_test | 5.000s | 162.410us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | csrng_tl_errors | 15.000s | 546.873us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | csrng_tl_errors | 15.000s | 546.873us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 3.000s | 35.112us | 5 | 5 | 100.00 |
csrng_csr_rw | 4.000s | 15.217us | 20 | 20 | 100.00 | ||
csrng_csr_aliasing | 4.000s | 90.830us | 5 | 5 | 100.00 | ||
csrng_same_csr_outstanding | 6.000s | 270.045us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | csrng_csr_hw_reset | 3.000s | 35.112us | 5 | 5 | 100.00 |
csrng_csr_rw | 4.000s | 15.217us | 20 | 20 | 100.00 | ||
csrng_csr_aliasing | 4.000s | 90.830us | 5 | 5 | 100.00 | ||
csrng_same_csr_outstanding | 6.000s | 270.045us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1420 | 1440 | 98.61 | |||
V2S | tl_intg_err | csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 |
csrng_tl_intg_err | 12.000s | 833.729us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | csrng_regwen | 6.000s | 11.413us | 50 | 50 | 100.00 |
csrng_csr_rw | 4.000s | 15.217us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_mubi | csrng_alert | 8.000s | 273.227us | 500 | 500 | 100.00 |
V2S | sec_cm_intersig_mubi | csrng_stress_all | 1.383m | 3.881ms | 48 | 50 | 96.00 |
V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_update_fsm_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ctrl_mubi | csrng_alert | 8.000s | 273.227us | 500 | 500 | 100.00 |
V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
V2S | sec_cm_constants_lc_gated | csrng_stress_all | 1.383m | 3.881ms | 48 | 50 | 96.00 |
V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 8.000s | 273.227us | 500 | 500 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 12.000s | 833.729us | 20 | 20 | 100.00 |
V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
csrng_sec_cm | 8.000s | 103.163us | 5 | 5 | 100.00 | ||
V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 7.000s | 49.648us | 200 | 200 | 100.00 |
csrng_err | 6.000s | 22.042us | 482 | 500 | 96.40 | ||
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.032h | 39.461ms | 7 | 50 | 14.00 |
V3 | TOTAL | 7 | 50 | 14.00 | |||
TOTAL | 1607 | 1670 | 96.23 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 9 | 9 | 7 | 77.78 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
92.86 | 93.35 | 84.31 | 95.43 | 86.47 | 92.29 | 100.00 | 97.50 | 95.64 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == *
has 26 failures:
1.csrng_stress_all_with_rand_reset.2470286102
Line 243, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10011730393 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xc1b9314) == 0x6
UVM_INFO @ 10011730393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.csrng_stress_all_with_rand_reset.3135221736
Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10000794851 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x3b79c094) == 0x6
UVM_INFO @ 10000794851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == *
has 13 failures:
3.csrng_stress_all_with_rand_reset.2275781130
Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10001125265 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x15b2dd94) == 0x6
UVM_INFO @ 10001125265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.csrng_stress_all_with_rand_reset.2218185996
Line 526, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25207172518 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xaf500b94) == 0x6
UVM_INFO @ 25207172518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed
has 11 failures:
28.csrng_err.1028188410
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2029157 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2029157 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2029157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.csrng_err.1532317158
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 10116985 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 10116985 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 10116985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed
has 7 failures:
220.csrng_err.1934723710
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/220.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1615978 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1615978 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1615978 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1615978 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1615978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
259.csrng_err.2418675310
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/259.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1701223 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1701223 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1701223 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1701223 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1701223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 5 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference.
has 3 failures:
7.csrng_stress_all_with_rand_reset.1468832587
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 41487693 PS + 13
Verilog Stack Trace:
42.csrng_stress_all_with_rand_reset.3098754239
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 11958870 PS + 14
Verilog Stack Trace:
... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
has 2 failures:
2.csrng_stress_all.3387698554
Line 267, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
UVM_ERROR @ 616800243 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 616800243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.csrng_stress_all.657435454
Line 259, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
UVM_ERROR @ 667362592 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 667362592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: *
has 1 failures:
25.csrng_stress_all_with_rand_reset.3708238459
Line 251, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3092324723 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 3092324723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---