CSRNG Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	239.898us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	28.185us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	38.907us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	1.286ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	312.294us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	29.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	38.907us	20	20	100.00
		csrng_csr_aliasing	6.000s	312.294us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	42.857us	200	200	100.00
V2	alerts	csrng_alert	8.000s	434.839us	500	500	100.00
V2	err	csrng_err	7.000s	21.559us	482	500	96.40
V2	cmds	csrng_cmds	2.300m	14.720ms	50	50	100.00
V2	life cycle	csrng_cmds	2.300m	14.720ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.750m	6.800ms	45	50	90.00
V2	intr_test	csrng_intr_test	4.000s	52.957us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	31.613us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	568.269us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	568.269us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	28.185us	5	5	100.00
		csrng_csr_rw	5.000s	38.907us	20	20	100.00
		csrng_csr_aliasing	6.000s	312.294us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	138.245us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	28.185us	5	5	100.00
		csrng_csr_rw	5.000s	38.907us	20	20	100.00
		csrng_csr_aliasing	6.000s	312.294us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	138.245us	20	20	100.00
V2		TOTAL			1417	1440	98.40
V2S	tl_intg_err	csrng_sec_cm	6.000s	86.391us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.143ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	27.777us	50	50	100.00
		csrng_csr_rw	5.000s	38.907us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	434.839us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.750m	6.800ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	434.839us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.750m	6.800ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	434.839us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.143ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
		csrng_sec_cm	6.000s	86.391us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	42.857us	200	200	100.00
		csrng_err	7.000s	21.559us	482	500	96.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	35.350m	24.994ms	2	50	4.00
V3		TOTAL			2	50	4.00
		TOTAL			1599	1670	95.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.83	93.34	84.27	95.41	86.47	92.23	98.18	97.33	95.64

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 31 failures:
- Test csrng_stress_all_with_rand_reset has 31 failures.
  - 1.csrng_stress_all_with_rand_reset.245559715
    Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15495693869 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x67e25614) == 0x6
  UVM_INFO @ 15495693869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.830653400
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10001481345 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x86c2e214) == 0x6
  UVM_INFO @ 10001481345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 29 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 0.csrng_stress_all_with_rand_reset.2957421243
    Line 261, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12003424509 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x9e5ea294) == 0x6
  UVM_INFO @ 12003424509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.2961713649
    Line 356, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000822727 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x96844514) == 0x6
  UVM_INFO @ 10000822727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

2.csrng_err.776391882
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6554100 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6554100 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6554100 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   6554100 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   6554100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

22.csrng_err.620843251
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1694181 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1694181 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1694181 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1694181 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1694181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

104.csrng_err.3154822590
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3876024 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3876024 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3876024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

133.csrng_err.740754985
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/133.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1893003 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   1893003 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1893003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

2.csrng_stress_all.3418333282
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log

  UVM_ERROR @ 1329539520 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1329539520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.csrng_stress_all.246020335
Line 275, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all/latest/run.log

  UVM_ERROR @ 2060589581 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2060589581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

10.csrng_err.878713259
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  10.csrng_err.878713259
  
  coverage files:
    model(design data) :  /workspace/coverage/default/10.csrng_err.878713259/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/10.csrng_err.878713259/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 26, 2023 at 00:36:50 PDT  (total: 00:00:05)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1

206.csrng_err.651016019
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/206.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  206.csrng_err.651016019
  
  coverage files:
    model(design data) :  /workspace/coverage/default/206.csrng_err.651016019/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/206.csrng_err.651016019/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 26, 2023 at 00:39:02 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

13.csrng_stress_all_with_rand_reset.293234375
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 28198459 PS + 12
  Verilog Stack Trace:

29.csrng_stress_all_with_rand_reset.424973975
Line 279, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 8680778399 PS + 12
  Verilog Stack Trace:

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

6.csrng_stress_all.1086402010
Line 253, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log

  UVM_ERROR @  23180507 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  23180507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.csrng_stress_all.1875931526
Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log

  UVM_ERROR @  47541990 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  47541990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 41.csrng_stress_all_with_rand_reset.3673691078
    Line 430, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11976562308 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 11976562308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```