c06cc3921| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 5.000s | 211.114us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 19.510us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 4.000s | 28.565us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 20.000s | 594.053us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 5.000s | 75.451us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 263.584us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 4.000s | 28.565us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 5.000s | 75.451us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 10.000s | 46.573us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 |
| V2 | cmds | csrng_cmds | 1.500m | 5.986ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 1.500m | 5.986ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 2.700m | 15.958ms | 47 | 50 | 94.00 |
| V2 | intr_test | csrng_intr_test | 5.000s | 112.065us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 10.000s | 13.998us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 14.000s | 558.127us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 14.000s | 558.127us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 19.510us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 28.565us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 75.451us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 75.501us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 19.510us | 5 | 5 | 100.00 |
| csrng_csr_rw | 4.000s | 28.565us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 75.451us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 75.501us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1424 | 1440 | 98.89 | |||
| V2S | tl_intg_err | csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 27.000s | 941.826us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 5.000s | 137.451us | 50 | 50 | 100.00 |
| csrng_csr_rw | 4.000s | 28.565us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 10.000s | 46.573us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 2.700m | 15.958ms | 47 | 50 | 94.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 10.000s | 46.573us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 2.700m | 15.958ms | 47 | 50 | 94.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 10.000s | 46.573us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 27.000s | 941.826us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| csrng_sec_cm | 7.000s | 106.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 7.000s | 31.209us | 200 | 200 | 100.00 |
| csrng_err | 8.000s | 23.311us | 487 | 500 | 97.40 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 56.417m | 39.253ms | 4 | 50 | 8.00 |
| V3 | TOTAL | 4 | 50 | 8.00 | |||
| TOTAL | 1608 | 1670 | 96.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 7 | 77.78 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.87 | 93.35 | 84.31 | 95.43 | 86.47 | 92.29 | 100.00 | 97.50 | 95.99 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 26 failures:
0.csrng_stress_all_with_rand_reset.1492637306
Line 244, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10004553467 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x66dc0514) == 0x6
UVM_INFO @ 10004553467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.csrng_stress_all_with_rand_reset.1315251916
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10010808156 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xc31bf494) == 0x6
UVM_INFO @ 10010808156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 16 failures:
1.csrng_stress_all_with_rand_reset.3597414776
Line 243, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10013056674 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x40829c94) == 0x6
UVM_INFO @ 10013056674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.2687796790
Line 245, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003194818 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xb390ac14) == 0x6
UVM_INFO @ 10003194818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 8 failures:
32.csrng_err.3201822758
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6985251 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 6985251 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 6985251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.csrng_err.3965548576
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 12516023 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 12516023 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 12516023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 5 failures:
17.csrng_err.1492435460
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2913669 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2913669 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2913669 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 2913669 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 2913669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
198.csrng_err.599620761
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/198.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1763135 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1763135 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1763135 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1763135 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1763135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:
25.csrng_stress_all_with_rand_reset.1846105148
Line 231, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 2097077 PS + 12
Verilog Stack Trace:
38.csrng_stress_all_with_rand_reset.2576416325
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 8137648 PS + 11
Verilog Stack Trace:
UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
34.csrng_stress_all.2348393699
Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
UVM_ERROR @ 87313197 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 87313197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.csrng_stress_all.1881850712
Line 265, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all/latest/run.log
UVM_ERROR @ 436170631 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 436170631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
17.csrng_stress_all_with_rand_reset.4137640290
Line 274, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1260582080 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 1260582080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
19.csrng_stress_all.1213165743
Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
UVM_ERROR @ 1729865689 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1729865689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
43.csrng_stress_all_with_rand_reset.2101694487
Line 467, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 27775360716 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 27775360716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---