c06cc3921| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 6.000s | 157.759us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 37.563us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 6.000s | 50.184us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 23.000s | 856.403us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 5.000s | 87.577us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 7.000s | 34.345us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 6.000s | 50.184us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 5.000s | 87.577us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 9.000s | 464.407us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 |
| V2 | cmds | csrng_cmds | 1.017m | 4.111ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 1.017m | 4.111ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 2.267m | 10.725ms | 49 | 50 | 98.00 |
| V2 | intr_test | csrng_intr_test | 4.000s | 40.207us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 5.000s | 61.449us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 12.000s | 479.311us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 12.000s | 479.311us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 37.563us | 5 | 5 | 100.00 |
| csrng_csr_rw | 6.000s | 50.184us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 87.577us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 8.000s | 384.273us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 37.563us | 5 | 5 | 100.00 |
| csrng_csr_rw | 6.000s | 50.184us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 87.577us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 8.000s | 384.273us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1425 | 1440 | 98.96 | |||
| V2S | tl_intg_err | csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 9.000s | 163.314us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 5.000s | 21.281us | 50 | 50 | 100.00 |
| csrng_csr_rw | 6.000s | 50.184us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 9.000s | 464.407us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 2.267m | 10.725ms | 49 | 50 | 98.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 9.000s | 464.407us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 2.267m | 10.725ms | 49 | 50 | 98.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 9.000s | 464.407us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 9.000s | 163.314us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 7.000s | 228.188us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 7.000s | 359.329us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 60.635us | 486 | 500 | 97.20 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 40.850m | 26.592ms | 5 | 50 | 10.00 |
| V3 | TOTAL | 5 | 50 | 10.00 | |||
| TOTAL | 1610 | 1670 | 96.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 7 | 77.78 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.81 | 93.32 | 84.23 | 95.38 | 86.47 | 92.23 | 100.00 | 97.33 | 95.64 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 26 failures:
3.csrng_stress_all_with_rand_reset.1256718487
Line 277, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12252291616 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xd72a4a94) == 0x6
UVM_INFO @ 12252291616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.csrng_stress_all_with_rand_reset.496583174
Line 251, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11256018629 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x4e8c8114) == 0x6
UVM_INFO @ 11256018629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 14 failures:
0.csrng_stress_all_with_rand_reset.215670663
Line 258, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003439378 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x7329414) == 0x6
UVM_INFO @ 10003439378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_stress_all_with_rand_reset.896663841
Line 274, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10346505914 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x779cb294) == 0x6
UVM_INFO @ 10346505914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 9 failures:
21.csrng_err.171781829
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1801769 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 1801769 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1801769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
82.csrng_err.1631058007
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/82.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 1573250 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 1573250 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1573250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
16.csrng_stress_all_with_rand_reset.91785865
Line 522, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20347392123 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 20347392123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.csrng_stress_all_with_rand_reset.1431067999
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2295866776 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 2295866776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 3 failures:
278.csrng_err.3039532629
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/278.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1765165 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1765165 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1765165 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1765165 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1765165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
345.csrng_err.2422656585
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/345.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2401704 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2401704 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2401704 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 2401704 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 2401704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:
23.csrng_stress_all_with_rand_reset.1992234550
Line 286, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 3321873912 PS + 14
Verilog Stack Trace:
40.csrng_stress_all_with_rand_reset.1107369326
Line 266, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 2933879761 PS + 12
Verilog Stack Trace:
Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:
117.csrng_err.497619009
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/117.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 117.csrng_err.497619009
coverage files:
model(design data) : /workspace/coverage/default/117.csrng_err.497619009/icc_2fd05324_376d948a.ucm
data : /workspace/coverage/default/117.csrng_err.497619009/icc_2fd05324_376d948a.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 28, 2023 at 00:47:29 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1
265.csrng_err.609650278
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/265.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 265.csrng_err.609650278
coverage files:
model(design data) : /workspace/coverage/default/265.csrng_err.609650278/icc_2fd05324_376d948a.ucm
data : /workspace/coverage/default/265.csrng_err.609650278/icc_2fd05324_376d948a.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 28, 2023 at 00:48:34 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
47.csrng_stress_all.535028823
Line 263, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log
UVM_ERROR @ 605450516 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 605450516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---