CSRNG Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	85.641us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	23.930us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	18.701us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	14.000s	690.927us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	396.287us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	139.327us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	18.701us	20	20	100.00
		csrng_csr_aliasing	7.000s	396.287us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	107.886us	200	200	100.00
V2	alerts	csrng_alert	7.000s	196.960us	500	500	100.00
V2	err	csrng_err	6.000s	25.555us	488	500	97.60
V2	cmds	csrng_cmds	57.000s	5.162ms	50	50	100.00
V2	life cycle	csrng_cmds	57.000s	5.162ms	50	50	100.00
V2	stress_all	csrng_stress_all	1.917m	7.228ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	17.405us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	13.916us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	771.858us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	771.858us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	23.930us	5	5	100.00
		csrng_csr_rw	4.000s	18.701us	20	20	100.00
		csrng_csr_aliasing	7.000s	396.287us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	76.435us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	23.930us	5	5	100.00
		csrng_csr_rw	4.000s	18.701us	20	20	100.00
		csrng_csr_aliasing	7.000s	396.287us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	76.435us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	7.000s	147.673us	5	5	100.00
		csrng_tl_intg_err	8.000s	194.156us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	163.993us	50	50	100.00
		csrng_csr_rw	4.000s	18.701us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	7.000s	196.960us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	1.917m	7.228ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	7.000s	196.960us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	1.917m	7.228ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	7.000s	196.960us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	194.156us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
		csrng_sec_cm	7.000s	147.673us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	107.886us	200	200	100.00
		csrng_err	6.000s	25.555us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	50.567m	31.882ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			1610	1670	96.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.82	93.34	84.27	95.39	86.47	92.29	100.00	97.50	95.28

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 28 failures:
- Test csrng_stress_all_with_rand_reset has 28 failures.
  - 0.csrng_stress_all_with_rand_reset.2310625142
    Line 257, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003887496 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x7175ef14) == 0x6
  UVM_INFO @ 10003887496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.172132641
    Line 354, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000955415 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xc9165594) == 0x6
  UVM_INFO @ 10000955415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 8.csrng_stress_all_with_rand_reset.543787560
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11990845662 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xe7eb6a14) == 0x6
  UVM_INFO @ 11990845662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all_with_rand_reset.1905521183
    Line 242, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004206691 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xea6b2814) == 0x6
  UVM_INFO @ 10004206691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

164.csrng_err.501427789
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/164.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4042058 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4042058 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4042058 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4042058 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4042058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

245.csrng_err.3274940448
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/245.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2132759 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2132759 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2132759 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2132759 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2132759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

51.csrng_err.3006487680
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/51.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3449801 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3449801 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3449801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

101.csrng_err.924396977
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 5038859 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   5038859 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5038859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

19.csrng_stress_all_with_rand_reset.1789376949
Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 14551304256 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 14551304256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.csrng_stress_all_with_rand_reset.1624366370
Line 466, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 23051987093 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 23051987093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

5.csrng_stress_all.2806568968
Line 268, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log

  UVM_ERROR @ 470011813 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 470011813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.csrng_stress_all.4129345721
Line 254, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log

  UVM_ERROR @ 299079431 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 299079431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

6.csrng_stress_all_with_rand_reset.4121679312
Line 259, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 4073625867 PS + 13
  Verilog Stack Trace:

18.csrng_stress_all_with_rand_reset.3105238732
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
            Time: 7403797 PS + 11
  Verilog Stack Trace:

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

16.csrng_err.1207210720
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  16.csrng_err.1207210720
  
  coverage files:
    model(design data) :  /workspace/coverage/default/16.csrng_err.1207210720/icc_2fd05324_376d948a.ucm
    data               :  /workspace/coverage/default/16.csrng_err.1207210720/icc_2fd05324_376d948a.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 29, 2023 at 01:15:17 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1