25be3439125be34391| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 20 | 20 | 100.00 |
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | firmware | edn_genbits | 50 | 50 | 100.00 |
| V2 | csrng_commands | edn_genbits | 50 | 50 | 100.00 |
| V2 | genbits | edn_genbits | 50 | 50 | 100.00 |
| V2 | interrupts | edn_intr | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 50 | 50 | 100.00 |
| V2 | stress_all | edn_stress_all | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 390 | 390 | 100.00 | |
| V2S | tl_intg_err | edn_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_config_regwen | sec_cm_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_config_mubi | sec_cm_config_mubi | 0 | 0 | -- |
| V2S | sec_cm_main_sm_fsm_sparse | sec_cm_main_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ack_sm_fsm_sparse | sec_cm_ack_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ctr_redun | sec_cm_ctr_redun | 0 | 0 | -- |
| V2S | sec_cm_main_sm_ctr_local_esc | sec_cm_main_sm_ctr_local_esc | 0 | 0 | -- |
| V2S | sec_cm_cs_rdata_bus_consistency | sec_cm_cs_rdata_bus_consistency | 0 | 0 | -- |
| V2S | sec_cm_tile_link_bus_integrity | sec_cm_tile_link_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| TOTAL | 515 | 565 | 91.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 9 | 100.00 |
| V2S | 9 | 1 | 1 | 11.11 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 87.67 | 98.04 | 95.11 | 98.64 | 87.38 | 79.12 | 60.47 | 91.95 | 88.55 |
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.regwen has 13 failures:
0.edn_stress_all_with_rand_reset.4248067305
Line 72, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/0.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 2706355570 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 2706355570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.edn_stress_all_with_rand_reset.4216732883
Line 60, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/1.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7933111 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 7933111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 11 failures:
4.edn_stress_all_with_rand_reset.2048510600
Line 97, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/4.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10072392353 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0xe8c8cfa4) == 0x1
UVM_INFO @ 10072392353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.edn_stress_all_with_rand_reset.1662156958
Line 82, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/10.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10002061314 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0xd6d3e324) == 0x1
UVM_INFO @ 10002061314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.main_sm_state has 7 failures:
2.edn_stress_all_with_rand_reset.627147980
Line 116, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/2.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7343519542 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 7343519542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.edn_stress_all_with_rand_reset.3864269000
Line 155, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/3.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7376871564 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 7376871564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code has 7 failures:
16.edn_stress_all_with_rand_reset.1098796848
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/16.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 3983401 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 3983401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.edn_stress_all_with_rand_reset.3470925348
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/19.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 8842216 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 8842216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.alert_test has 6 failures:
11.edn_stress_all_with_rand_reset.899743677
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/11.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 12238116 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 12238116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.edn_stress_all_with_rand_reset.3131700100
Line 86, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/21.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 4361991847 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 4361991847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 3 failures:
6.edn_stress_all_with_rand_reset.2696549596
Line 121, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/6.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10015288039 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0xcf6b8d24) == 0x1
UVM_INFO @ 10015288039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.edn_stress_all_with_rand_reset.2411446425
Line 82, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/12.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10004410367 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x39597524) == 0x1
UVM_INFO @ 10004410367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code_test has 3 failures:
18.edn_stress_all_with_rand_reset.1247950769
Line 62, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/18.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 3530522059 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 3530522059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.edn_stress_all_with_rand_reset.1531523265
Line 72, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/36.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 2080195242 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 2080195242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.