8d5fa645a8d5fa645a| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 20 | 20 | 100.00 |
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | firmware | edn_genbits | 50 | 50 | 100.00 |
| V2 | csrng_commands | edn_genbits | 50 | 50 | 100.00 |
| V2 | genbits | edn_genbits | 50 | 50 | 100.00 |
| V2 | interrupts | edn_intr | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 50 | 50 | 100.00 |
| V2 | stress_all | edn_stress_all | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 390 | 390 | 100.00 | |
| V2S | tl_intg_err | edn_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_config_regwen | sec_cm_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_config_mubi | sec_cm_config_mubi | 0 | 0 | -- |
| V2S | sec_cm_main_sm_fsm_sparse | sec_cm_main_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ack_sm_fsm_sparse | sec_cm_ack_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ctr_redun | sec_cm_ctr_redun | 0 | 0 | -- |
| V2S | sec_cm_main_sm_ctr_local_esc | sec_cm_main_sm_ctr_local_esc | 0 | 0 | -- |
| V2S | sec_cm_cs_rdata_bus_consistency | sec_cm_cs_rdata_bus_consistency | 0 | 0 | -- |
| V2S | sec_cm_tile_link_bus_integrity | sec_cm_tile_link_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| TOTAL | 515 | 565 | 91.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 9 | 100.00 |
| V2S | 9 | 1 | 1 | 11.11 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 88.13 | 97.93 | 95.11 | 98.56 | 86.75 | 80.24 | 60.47 | 91.95 | 89.56 |
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 14 failures:
1.edn_stress_all_with_rand_reset.1564919373
Line 71, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/1.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000932354 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x32b75da4) == 0x1
UVM_INFO @ 10000932354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.edn_stress_all_with_rand_reset.195529070
Line 81, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/4.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10003841352 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x9975f824) == 0x1
UVM_INFO @ 10003841352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.main_sm_state has 7 failures:
3.edn_stress_all_with_rand_reset.528772895
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/3.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 5067606 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 5067606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.edn_stress_all_with_rand_reset.780866936
Line 65, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/7.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 2142716464 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 2142716464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code_test has 7 failures:
5.edn_stress_all_with_rand_reset.1678392827
Line 65, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/5.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 2542828181 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 2542828181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.edn_stress_all_with_rand_reset.1623653806
Line 91, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/14.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1761893290 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 1761893290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code has 7 failures:
18.edn_stress_all_with_rand_reset.665697659
Line 60, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/18.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 5240209 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 5240209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.edn_stress_all_with_rand_reset.3227996146
Line 67, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/20.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1501696586 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 1501696586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 6 failures:
0.edn_stress_all_with_rand_reset.3585614157
Line 121, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/0.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10022520987 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x8990fd24) == 0x1
UVM_INFO @ 10022520987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.edn_stress_all_with_rand_reset.4018311509
Line 86, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/13.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10001410275 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x505c824) == 0x1
UVM_INFO @ 10001410275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.regwen has 5 failures:
8.edn_stress_all_with_rand_reset.3351084732
Line 78, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/8.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 5749148574 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 5749148574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.edn_stress_all_with_rand_reset.1259192394
Line 62, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/9.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 385371418 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 385371418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.alert_test has 4 failures:
2.edn_stress_all_with_rand_reset.1459335653
Line 62, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/2.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 3686992300 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 3686992300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.edn_stress_all_with_rand_reset.635489884
Line 111, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/17.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7853052212 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 7853052212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.