6a92ed2656a92ed265| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 20 | 20 | 100.00 |
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | firmware | edn_genbits | 50 | 50 | 100.00 |
| V2 | csrng_commands | edn_genbits | 50 | 50 | 100.00 |
| V2 | genbits | edn_genbits | 50 | 50 | 100.00 |
| V2 | interrupts | edn_intr | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 50 | 50 | 100.00 |
| V2 | stress_all | edn_stress_all | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 390 | 390 | 100.00 | |
| V2S | tl_intg_err | edn_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_config_regwen | sec_cm_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_config_mubi | sec_cm_config_mubi | 0 | 0 | -- |
| V2S | sec_cm_main_sm_fsm_sparse | sec_cm_main_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ack_sm_fsm_sparse | sec_cm_ack_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ctr_redun | sec_cm_ctr_redun | 0 | 0 | -- |
| V2S | sec_cm_main_sm_ctr_local_esc | sec_cm_main_sm_ctr_local_esc | 0 | 0 | -- |
| V2S | sec_cm_cs_rdata_bus_consistency | sec_cm_cs_rdata_bus_consistency | 0 | 0 | -- |
| V2S | sec_cm_tile_link_bus_integrity | sec_cm_tile_link_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| TOTAL | 515 | 565 | 91.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 9 | 100.00 |
| V2S | 9 | 1 | 1 | 11.11 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 88.24 | 97.94 | 95.11 | 98.57 | 87.25 | 80.28 | 60.47 | 91.95 | 89.90 |
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.regwen has 12 failures:
6.edn_stress_all_with_rand_reset.3272505638
Line 65, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/6.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1309897430 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 1309897430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.edn_stress_all_with_rand_reset.841270425
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/8.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 3037338 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 3037338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 10 failures:
0.edn_stress_all_with_rand_reset.1850190602
Line 152, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/0.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10035523115 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x48fa61a4) == 0x1
UVM_INFO @ 10035523115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.edn_stress_all_with_rand_reset.357624485
Line 71, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/2.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10003885983 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x907417a4) == 0x1
UVM_INFO @ 10003885983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code_test has 9 failures:
1.edn_stress_all_with_rand_reset.2544377857
Line 69, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/1.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1820437589 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 1820437589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.edn_stress_all_with_rand_reset.2999647239
Line 70, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/3.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1910655360 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 1910655360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 5 failures:
11.edn_stress_all_with_rand_reset.3146557251
Line 72, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/11.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10003314824 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x4d4edfa4) == 0x1
UVM_INFO @ 10003314824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.edn_stress_all_with_rand_reset.3222353575
Line 154, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/36.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10000889935 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0xa5ade924) == 0x1
UVM_INFO @ 10000889935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code has 5 failures:
15.edn_stress_all_with_rand_reset.3084264763
Line 60, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/15.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 9445248 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 9445248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.edn_stress_all_with_rand_reset.1187618084
Line 78, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/21.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 9371707987 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 9371707987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.main_sm_state has 5 failures:
16.edn_stress_all_with_rand_reset.1875083622
Line 58, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/16.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 264731654 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 264731654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.edn_stress_all_with_rand_reset.1793809189
Line 61, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/18.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1589840578 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 1589840578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.alert_test has 4 failures:
27.edn_stress_all_with_rand_reset.1525973464
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/27.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 94238362 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 94238362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.edn_stress_all_with_rand_reset.272117383
Line 60, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/32.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 417142134 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 417142134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.