d498f91d6d498f91d6| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 20 | 20 | 100.00 |
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |
| V2 | firmware | edn_genbits | 50 | 50 | 100.00 |
| V2 | csrng_commands | edn_genbits | 50 | 50 | 100.00 |
| V2 | genbits | edn_genbits | 50 | 50 | 100.00 |
| V2 | interrupts | edn_intr | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 50 | 50 | 100.00 |
| V2 | stress_all | edn_stress_all | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 5 | 5 | 100.00 |
| edn_csr_rw | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 390 | 390 | 100.00 | |
| V2S | tl_intg_err | edn_tl_intg_err | 20 | 20 | 100.00 |
| V2S | sec_cm_config_regwen | sec_cm_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_config_mubi | sec_cm_config_mubi | 0 | 0 | -- |
| V2S | sec_cm_main_sm_fsm_sparse | sec_cm_main_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ack_sm_fsm_sparse | sec_cm_ack_sm_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ctr_redun | sec_cm_ctr_redun | 0 | 0 | -- |
| V2S | sec_cm_main_sm_ctr_local_esc | sec_cm_main_sm_ctr_local_esc | 0 | 0 | -- |
| V2S | sec_cm_cs_rdata_bus_consistency | sec_cm_cs_rdata_bus_consistency | 0 | 0 | -- |
| V2S | sec_cm_tile_link_bus_integrity | sec_cm_tile_link_bus_integrity | 0 | 0 | -- |
| V2S | TOTAL | 20 | 20 | 100.00 | |
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| TOTAL | 515 | 565 | 91.15 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 9 | 100.00 |
| V2S | 9 | 1 | 1 | 11.11 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 94.01 | 97.94 | 95.11 | 98.57 | 86.95 | 99.34 | 60.47 | 91.95 | 89.23 |
UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 13 failures:
1.edn_stress_all_with_rand_reset.3433371758
Line 89, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/1.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10029437955 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x1dd7f724) == 0x1
UVM_INFO @ 10029437955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.edn_stress_all_with_rand_reset.4166702750
Line 115, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/4.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10001949043 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0xa47a1ca4) == 0x1
UVM_INFO @ 10001949043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.alert_test has 12 failures:
3.edn_stress_all_with_rand_reset.3991190761
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/3.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 9399050 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 9399050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.edn_stress_all_with_rand_reset.2285527018
Line 176, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/5.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 9251210301 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.alert_test
UVM_INFO @ 9251210301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Exit reason: Error: User command failed UVM_FATAL (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=*) == * has 11 failures:
10.edn_stress_all_with_rand_reset.2825837914
Line 69, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/10.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10004696777 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x8ba616a4) == 0x1
UVM_INFO @ 10004696777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.edn_stress_all_with_rand_reset.2017801476
Line 89, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/11.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10097908532 ps: (dv_utils_pkg.sv:147) [csr_utils::csr_spinwait] timeout edn_reg_block.sw_cmd_sts.cmd_rdy (addr=0x2f5475a4) == 0x1
UVM_INFO @ 10097908532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.regwen has 6 failures:
15.edn_stress_all_with_rand_reset.1018286420
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/15.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 10845417 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 10845417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.edn_stress_all_with_rand_reset.2749603499
Line 64, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/26.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 1073107734 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.regwen
UVM_INFO @ 1073107734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.main_sm_state has 3 failures:
0.edn_stress_all_with_rand_reset.3195402991
Line 57, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/0.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 20997974 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 20997974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.edn_stress_all_with_rand_reset.437693160
Line 77, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/14.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7944014265 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.main_sm_state
UVM_INFO @ 7944014265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code has 3 failures:
6.edn_stress_all_with_rand_reset.690026660
Line 149, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/6.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 7532484286 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 7532484286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.edn_stress_all_with_rand_reset.3705557556
Line 86, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/8.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 2030679063 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code
UVM_INFO @ 2030679063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (edn_scoreboard.sv:128) scoreboard [scoreboard] invalid csr: edn_reg_block.err_code_test has 2 failures:
2.edn_stress_all_with_rand_reset.3234011634
Line 66, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/2.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 527202778 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 527202778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.edn_stress_all_with_rand_reset.1424511126
Line 58, in log /container/opentitan-public/scratch/os_regression/edn-sim-xcelium/36.edn_stress_all_with_rand_reset/out/run.log
UVM_FATAL @ 155768039 ps: (edn_scoreboard.sv:128) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] invalid csr: edn_reg_block.err_code_test
UVM_INFO @ 155768039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---