EDN Simulation Results

Wednesday May 18 2022 08:08:47 UTC

GitHub Revision: d498f91d6
Foundry Revision: d498f91d6

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1087921459

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke edn_smoke 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 5 5 100.00
V1 csr_rw edn_csr_rw 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 20 20 100.00
edn_csr_aliasing 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 50 50 100.00
V2 csrng_commands edn_genbits 50 50 100.00
V2 genbits edn_genbits 50 50 100.00
V2 interrupts edn_intr 50 50 100.00
V2 alerts edn_alert 50 50 100.00
V2 errs edn_err 50 50 100.00
V2 stress_all edn_stress_all 50 50 100.00
V2 intr_test edn_intr_test 50 50 100.00
V2 alert_test edn_alert_test 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 5 5 100.00
edn_csr_rw 20 20 100.00
edn_csr_aliasing 5 5 100.00
edn_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 5 5 100.00
edn_csr_rw 20 20 100.00
edn_csr_aliasing 5 5 100.00
edn_same_csr_outstanding 20 20 100.00
V2 TOTAL 390 390 100.00
V2S tl_intg_err edn_tl_intg_err 20 20 100.00
V2S sec_cm_config_regwen sec_cm_config_regwen 0 0 --
V2S sec_cm_config_mubi sec_cm_config_mubi 0 0 --
V2S sec_cm_main_sm_fsm_sparse sec_cm_main_sm_fsm_sparse 0 0 --
V2S sec_cm_ack_sm_fsm_sparse sec_cm_ack_sm_fsm_sparse 0 0 --
V2S sec_cm_ctr_redun sec_cm_ctr_redun 0 0 --
V2S sec_cm_main_sm_ctr_local_esc sec_cm_main_sm_ctr_local_esc 0 0 --
V2S sec_cm_cs_rdata_bus_consistency sec_cm_cs_rdata_bus_consistency 0 0 --
V2S sec_cm_tile_link_bus_integrity sec_cm_tile_link_bus_integrity 0 0 --
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 515 565 91.15

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 9 100.00
V2S 9 1 1 11.11
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.01 97.94 95.11 98.57 86.95 99.34 60.47 91.95 89.23

Failure Buckets

Past Results