EDN Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.960s	14.131us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	14.940us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	16.974us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.040s	524.807us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.500s	38.179us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.400s	74.781us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	16.974us	20	20	100.00
		edn_csr_aliasing	1.500s	38.179us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.870s	62.540us	50	50	100.00
V2	csrng_commands	edn_genbits	1.870s	62.540us	50	50	100.00
V2	genbits	edn_genbits	1.870s	62.540us	50	50	100.00
V2	interrupts	edn_intr	1.200s	21.169us	50	50	100.00
V2	alerts	edn_alert	1.100s	57.626us	50	50	100.00
V2	errs	edn_err	1.550s	51.489us	50	50	100.00
V2	disable	edn_disable	2.050s	100.000us	48	50	96.00
		edn_disable_auto_req_mode	1.120s	109.866us	50	50	100.00
V2	stress_all	edn_stress_all	5.600s	4.168ms	50	50	100.00
V2	intr_test	edn_intr_test	0.920s	82.690us	50	50	100.00
V2	alert_test	edn_alert_test	1.020s	19.339us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.300s	152.589us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.300s	152.589us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	14.940us	5	5	100.00
		edn_csr_rw	0.960s	16.974us	20	20	100.00
		edn_csr_aliasing	1.500s	38.179us	5	5	100.00
		edn_same_csr_outstanding	1.560s	247.855us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	14.940us	5	5	100.00
		edn_csr_rw	0.960s	16.974us	20	20	100.00
		edn_csr_aliasing	1.500s	38.179us	5	5	100.00
		edn_same_csr_outstanding	1.560s	247.855us	20	20	100.00
V2		TOTAL			488	490	99.59
V2S	tl_intg_err	edn_sec_cm	11.610s	803.860us	5	5	100.00
		edn_tl_intg_err	2.680s	223.365us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.930s	51.083us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.100s	57.626us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.610s	803.860us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.610s	803.860us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.610s	803.860us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.100s	57.626us	50	50	100.00
		edn_sec_cm	11.610s	803.860us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.100s	57.626us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.680s	223.365us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	35.560m	573.354ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			678	680	99.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.02	99.03	94.43	96.84	70.39	98.62	99.77	99.07

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test edn_disable has 2 failures.

14.edn_disable.4176020657
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.edn_disable.3514044558
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/29.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---