EDN Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.920s 15.798us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.900s 34.410us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 25.567us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.270s 1.460ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.480s 36.501us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 121.913us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 25.567us 20 20 100.00
edn_csr_aliasing 1.480s 36.501us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.530s 563.100us 50 50 100.00
V2 csrng_commands edn_genbits 1.530s 563.100us 50 50 100.00
V2 genbits edn_genbits 1.530s 563.100us 50 50 100.00
V2 interrupts edn_intr 1.150s 19.729us 50 50 100.00
V2 alerts edn_alert 1.060s 229.925us 50 50 100.00
V2 errs edn_err 1.110s 18.740us 50 50 100.00
V2 disable edn_disable 0.940s 16.222us 50 50 100.00
edn_disable_auto_req_mode 1.060s 37.412us 50 50 100.00
V2 stress_all edn_stress_all 3.750s 346.675us 50 50 100.00
V2 intr_test edn_intr_test 1.070s 28.100us 50 50 100.00
V2 alert_test edn_alert_test 0.990s 29.818us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.390s 2.148ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.390s 2.148ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.900s 34.410us 5 5 100.00
edn_csr_rw 0.960s 25.567us 20 20 100.00
edn_csr_aliasing 1.480s 36.501us 5 5 100.00
edn_same_csr_outstanding 1.360s 59.752us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.900s 34.410us 5 5 100.00
edn_csr_rw 0.960s 25.567us 20 20 100.00
edn_csr_aliasing 1.480s 36.501us 5 5 100.00
edn_same_csr_outstanding 1.360s 59.752us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err edn_sec_cm 6.950s 451.667us 5 5 100.00
edn_tl_intg_err 5.760s 364.574us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.920s 20.912us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.060s 229.925us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.950s 451.667us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.950s 451.667us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.950s 451.667us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.060s 229.925us 50 50 100.00
edn_sec_cm 6.950s 451.667us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.060s 229.925us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.760s 364.574us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 41.304m 397.913ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 679 680 99.85

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.23 99.03 94.02 96.79 73.03 98.62 99.77 98.38

Failure Buckets

Past Results