EDN Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.950s	28.852us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	15.848us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	18.110us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.160s	339.472us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.490s	70.509us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.570s	43.880us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	18.110us	20	20	100.00
		edn_csr_aliasing	1.490s	70.509us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.580s	25.914us	50	50	100.00
V2	csrng_commands	edn_genbits	1.580s	25.914us	50	50	100.00
V2	genbits	edn_genbits	1.580s	25.914us	50	50	100.00
V2	interrupts	edn_intr	1.210s	20.812us	50	50	100.00
V2	alerts	edn_alert	1.100s	55.806us	50	50	100.00
V2	errs	edn_err	1.220s	20.776us	50	50	100.00
V2	disable	edn_disable	0.900s	12.061us	47	50	94.00
		edn_disable_auto_req_mode	1.110s	27.217us	50	50	100.00
V2	stress_all	edn_stress_all	4.130s	202.264us	50	50	100.00
V2	intr_test	edn_intr_test	0.910s	57.971us	50	50	100.00
V2	alert_test	edn_alert_test	1.340s	50.462us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.950s	98.574us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.950s	98.574us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	15.848us	5	5	100.00
		edn_csr_rw	0.940s	18.110us	20	20	100.00
		edn_csr_aliasing	1.490s	70.509us	5	5	100.00
		edn_same_csr_outstanding	1.360s	71.599us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	15.848us	5	5	100.00
		edn_csr_rw	0.940s	18.110us	20	20	100.00
		edn_csr_aliasing	1.490s	70.509us	5	5	100.00
		edn_same_csr_outstanding	1.360s	71.599us	20	20	100.00
V2		TOTAL			487	490	99.39
V2S	tl_intg_err	edn_sec_cm	6.270s	1.437ms	5	5	100.00
		edn_tl_intg_err	4.700s	1.020ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.960s	16.131us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.100s	55.806us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.270s	1.437ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.270s	1.437ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.270s	1.437ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.100s	55.806us	50	50	100.00
		edn_sec_cm	6.270s	1.437ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.100s	55.806us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.700s	1.020ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	48.100m	138.081ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			676	680	99.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.03	94.43	96.79	72.37	98.62	99.77	98.84

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test edn_disable has 3 failures.

11.edn_disable.3328943969
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.edn_disable.917359795
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/13.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 33.edn_stress_all_with_rand_reset.31921097
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8ac0677a-617f-4fcd-85ce-79b811fec9f2
```