EDN Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.970s 22.833us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.880s 80.090us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 15.049us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.860s 178.588us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.460s 149.501us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.760s 58.879us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 15.049us 20 20 100.00
edn_csr_aliasing 1.460s 149.501us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.480s 48.462us 50 50 100.00
V2 csrng_commands edn_genbits 1.480s 48.462us 50 50 100.00
V2 genbits edn_genbits 1.480s 48.462us 50 50 100.00
V2 interrupts edn_intr 1.220s 19.421us 50 50 100.00
V2 alerts edn_alert 1.060s 21.684us 50 50 100.00
V2 errs edn_err 1.080s 17.990us 50 50 100.00
V2 disable edn_disable 1.970s 100.000us 47 50 94.00
edn_disable_auto_req_mode 1.110s 138.197us 50 50 100.00
V2 stress_all edn_stress_all 3.720s 682.066us 50 50 100.00
V2 intr_test edn_intr_test 0.920s 15.353us 50 50 100.00
V2 alert_test edn_alert_test 1.160s 32.520us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.290s 145.831us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.290s 145.831us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.880s 80.090us 5 5 100.00
edn_csr_rw 0.960s 15.049us 20 20 100.00
edn_csr_aliasing 1.460s 149.501us 5 5 100.00
edn_same_csr_outstanding 1.470s 43.673us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.880s 80.090us 5 5 100.00
edn_csr_rw 0.960s 15.049us 20 20 100.00
edn_csr_aliasing 1.460s 149.501us 5 5 100.00
edn_same_csr_outstanding 1.470s 43.673us 20 20 100.00
V2 TOTAL 487 490 99.39
V2S tl_intg_err edn_sec_cm 6.170s 2.160ms 5 5 100.00
edn_tl_intg_err 4.880s 270.061us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.970s 16.778us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.060s 21.684us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.170s 2.160ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.170s 2.160ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.170s 2.160ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.060s 21.684us 50 50 100.00
edn_sec_cm 6.170s 2.160ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.060s 21.684us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.880s 270.061us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 56.532m 909.090ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 677 680 99.56

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.28 99.03 94.43 96.74 73.03 98.62 99.77 98.38

Failure Buckets

Past Results