Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 99.02 92.26 96.79 89.47 98.62 99.77 97.91


Total test records in report: 687
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T542 /workspace/coverage/default/47.edn_alert.2672379542 Sep 27 01:03:32 PM PDT 23 Sep 27 01:03:33 PM PDT 23 177568641 ps
T141 /workspace/coverage/default/90.edn_err.2002865594 Sep 27 01:04:07 PM PDT 23 Sep 27 01:04:08 PM PDT 23 52725267 ps
T543 /workspace/coverage/default/93.edn_err.2125726262 Sep 27 01:04:05 PM PDT 23 Sep 27 01:04:06 PM PDT 23 128318850 ps
T544 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3484940909 Sep 27 01:01:46 PM PDT 23 Sep 27 01:11:52 PM PDT 23 26619249240 ps
T545 /workspace/coverage/default/7.edn_smoke.3863046590 Sep 27 01:02:01 PM PDT 23 Sep 27 01:02:02 PM PDT 23 53372396 ps
T266 /workspace/coverage/default/28.edn_genbits.276385331 Sep 27 01:02:02 PM PDT 23 Sep 27 01:02:05 PM PDT 23 37465806 ps
T546 /workspace/coverage/default/3.edn_regwen.179823311 Sep 27 01:02:28 PM PDT 23 Sep 27 01:02:29 PM PDT 23 12385143 ps
T547 /workspace/coverage/default/23.edn_alert_test.2774214653 Sep 27 01:03:19 PM PDT 23 Sep 27 01:03:21 PM PDT 23 69100545 ps
T155 /workspace/coverage/default/70.edn_err.3666165960 Sep 27 01:03:44 PM PDT 23 Sep 27 01:03:45 PM PDT 23 31704807 ps
T162 /workspace/coverage/default/84.edn_err.372044816 Sep 27 01:04:18 PM PDT 23 Sep 27 01:04:19 PM PDT 23 85820303 ps
T548 /workspace/coverage/default/12.edn_disable.995315084 Sep 27 01:01:11 PM PDT 23 Sep 27 01:01:12 PM PDT 23 14474488 ps
T549 /workspace/coverage/default/30.edn_genbits.2383666592 Sep 27 01:03:03 PM PDT 23 Sep 27 01:03:04 PM PDT 23 180920911 ps
T550 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.205585336 Sep 27 01:01:54 PM PDT 23 Sep 27 01:32:33 PM PDT 23 402161248022 ps
T551 /workspace/coverage/default/10.edn_alert.1264145627 Sep 27 01:09:38 PM PDT 23 Sep 27 01:09:39 PM PDT 23 22279686 ps
T272 /workspace/coverage/default/3.edn_genbits.1236376144 Sep 27 01:01:46 PM PDT 23 Sep 27 01:01:47 PM PDT 23 18179735 ps
T147 /workspace/coverage/default/10.edn_err.1281527238 Sep 27 01:06:02 PM PDT 23 Sep 27 01:06:03 PM PDT 23 32214768 ps
T148 /workspace/coverage/default/14.edn_err.626174475 Sep 27 01:05:01 PM PDT 23 Sep 27 01:05:07 PM PDT 23 30381640 ps
T552 /workspace/coverage/default/10.edn_smoke.3432343029 Sep 27 01:00:26 PM PDT 23 Sep 27 01:00:27 PM PDT 23 11172097 ps
T175 /workspace/coverage/default/18.edn_disable.2376415915 Sep 27 01:01:53 PM PDT 23 Sep 27 01:01:54 PM PDT 23 13013867 ps
T293 /workspace/coverage/default/5.edn_regwen.4182118417 Sep 27 01:14:07 PM PDT 23 Sep 27 01:14:09 PM PDT 23 152847357 ps
T553 /workspace/coverage/default/9.edn_smoke.3650159274 Sep 27 01:15:40 PM PDT 23 Sep 27 01:15:41 PM PDT 23 12310664 ps
T554 /workspace/coverage/default/42.edn_smoke.1859060311 Sep 27 01:01:32 PM PDT 23 Sep 27 01:01:33 PM PDT 23 61294880 ps
T555 /workspace/coverage/default/21.edn_err.441628177 Sep 27 01:02:01 PM PDT 23 Sep 27 01:02:02 PM PDT 23 19745678 ps
T556 /workspace/coverage/default/99.edn_err.510690280 Sep 27 01:04:18 PM PDT 23 Sep 27 01:04:19 PM PDT 23 18517455 ps
T557 /workspace/coverage/default/42.edn_alert.1511421871 Sep 27 01:03:12 PM PDT 23 Sep 27 01:03:14 PM PDT 23 55679276 ps
T558 /workspace/coverage/default/35.edn_intr.2909015270 Sep 27 01:02:31 PM PDT 23 Sep 27 01:02:32 PM PDT 23 19758803 ps
T559 /workspace/coverage/default/5.edn_alert_test.2544313303 Sep 27 01:01:01 PM PDT 23 Sep 27 01:01:02 PM PDT 23 49162362 ps
T560 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1574346926 Sep 27 01:03:51 PM PDT 23 Sep 27 01:09:03 PM PDT 23 54556078465 ps
T561 /workspace/coverage/default/40.edn_alert.188944207 Sep 27 01:02:01 PM PDT 23 Sep 27 01:02:03 PM PDT 23 62480125 ps
T562 /workspace/coverage/default/35.edn_smoke.4175905755 Sep 27 01:02:25 PM PDT 23 Sep 27 01:02:26 PM PDT 23 83780356 ps
T145 /workspace/coverage/default/47.edn_err.943671207 Sep 27 01:04:13 PM PDT 23 Sep 27 01:04:14 PM PDT 23 33710228 ps
T563 /workspace/coverage/default/32.edn_stress_all_with_rand_reset.990832117 Sep 27 01:02:02 PM PDT 23 Sep 27 01:10:45 PM PDT 23 47475237689 ps
T564 /workspace/coverage/default/45.edn_disable.2257921763 Sep 27 01:07:17 PM PDT 23 Sep 27 01:07:18 PM PDT 23 16613346 ps
T565 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2746916573 Sep 27 01:03:03 PM PDT 23 Sep 27 01:30:49 PM PDT 23 138480007366 ps
T136 /workspace/coverage/default/31.edn_err.3125380786 Sep 27 01:02:03 PM PDT 23 Sep 27 01:02:05 PM PDT 23 28135783 ps
T288 /workspace/coverage/default/39.edn_genbits.2464737409 Sep 27 01:04:14 PM PDT 23 Sep 27 01:04:20 PM PDT 23 20015005 ps
T566 /workspace/coverage/default/11.edn_genbits.8210439 Sep 27 01:00:32 PM PDT 23 Sep 27 01:00:33 PM PDT 23 23125726 ps
T567 /workspace/coverage/default/13.edn_err.839423735 Sep 27 01:01:56 PM PDT 23 Sep 27 01:01:57 PM PDT 23 37143032 ps
T568 /workspace/coverage/default/24.edn_stress_all.2352435348 Sep 27 01:02:07 PM PDT 23 Sep 27 01:02:11 PM PDT 23 160414432 ps
T142 /workspace/coverage/default/45.edn_err.1943327928 Sep 27 01:01:32 PM PDT 23 Sep 27 01:01:34 PM PDT 23 40640356 ps
T569 /workspace/coverage/default/10.edn_disable.3951814868 Sep 27 01:10:05 PM PDT 23 Sep 27 01:10:06 PM PDT 23 10097240 ps
T297 /workspace/coverage/default/6.edn_regwen.1434190801 Sep 27 01:01:12 PM PDT 23 Sep 27 01:01:13 PM PDT 23 42830225 ps
T168 /workspace/coverage/default/23.edn_disable.1172891304 Sep 27 01:02:26 PM PDT 23 Sep 27 01:02:27 PM PDT 23 37669032 ps
T249 /workspace/coverage/default/4.edn_err.1163630575 Sep 27 01:15:13 PM PDT 23 Sep 27 01:15:15 PM PDT 23 42361241 ps
T570 /workspace/coverage/default/47.edn_stress_all.1476830389 Sep 27 01:04:32 PM PDT 23 Sep 27 01:04:34 PM PDT 23 310245166 ps
T571 /workspace/coverage/default/38.edn_stress_all.2528322355 Sep 27 01:01:28 PM PDT 23 Sep 27 01:01:31 PM PDT 23 131264111 ps
T572 /workspace/coverage/default/4.edn_alert_test.3924541519 Sep 27 01:01:48 PM PDT 23 Sep 27 01:01:49 PM PDT 23 49251334 ps
T573 /workspace/coverage/default/28.edn_err.3173921760 Sep 27 01:01:02 PM PDT 23 Sep 27 01:01:03 PM PDT 23 31449762 ps
T574 /workspace/coverage/default/19.edn_intr.2337845830 Sep 27 01:02:50 PM PDT 23 Sep 27 01:02:51 PM PDT 23 29216724 ps
T575 /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2267461259 Sep 27 01:00:48 PM PDT 23 Sep 27 01:11:44 PM PDT 23 179187282885 ps
T576 /workspace/coverage/default/9.edn_stress_all.1038598896 Sep 27 01:02:49 PM PDT 23 Sep 27 01:02:51 PM PDT 23 417094473 ps
T577 /workspace/coverage/default/10.edn_intr.3831314222 Sep 27 01:20:12 PM PDT 23 Sep 27 01:20:13 PM PDT 23 66859110 ps
T578 /workspace/coverage/default/4.edn_regwen.205631274 Sep 27 01:10:31 PM PDT 23 Sep 27 01:10:33 PM PDT 23 14641850 ps
T579 /workspace/coverage/default/12.edn_stress_all.18743556 Sep 27 01:03:53 PM PDT 23 Sep 27 01:03:56 PM PDT 23 326530651 ps
T580 /workspace/coverage/default/2.edn_smoke.123077463 Sep 27 01:15:26 PM PDT 23 Sep 27 01:15:27 PM PDT 23 23532401 ps
T581 /workspace/coverage/default/17.edn_smoke.2330224666 Sep 27 01:02:45 PM PDT 23 Sep 27 01:02:46 PM PDT 23 38351061 ps
T582 /workspace/coverage/default/31.edn_intr.4126238155 Sep 27 01:02:33 PM PDT 23 Sep 27 01:02:35 PM PDT 23 20695105 ps
T583 /workspace/coverage/default/36.edn_genbits.3534621391 Sep 27 01:04:16 PM PDT 23 Sep 27 01:04:18 PM PDT 23 43436491 ps
T584 /workspace/coverage/default/2.edn_intr.3592882696 Sep 27 01:08:45 PM PDT 23 Sep 27 01:08:46 PM PDT 23 59308861 ps
T585 /workspace/coverage/default/18.edn_alert.2649334744 Sep 27 01:02:28 PM PDT 23 Sep 27 01:02:29 PM PDT 23 31398307 ps
T586 /workspace/coverage/default/35.edn_stress_all.2209725358 Sep 27 01:03:04 PM PDT 23 Sep 27 01:03:07 PM PDT 23 321814741 ps
T587 /workspace/coverage/default/20.edn_smoke.1281735085 Sep 27 01:02:05 PM PDT 23 Sep 27 01:02:06 PM PDT 23 12704383 ps
T588 /workspace/coverage/default/13.edn_alert.280238264 Sep 27 01:01:32 PM PDT 23 Sep 27 01:01:33 PM PDT 23 90182054 ps
T172 /workspace/coverage/default/11.edn_disable.4084406847 Sep 27 01:02:06 PM PDT 23 Sep 27 01:02:07 PM PDT 23 11596033 ps
T589 /workspace/coverage/default/32.edn_err.3028477364 Sep 27 01:03:45 PM PDT 23 Sep 27 01:03:46 PM PDT 23 42807340 ps
T590 /workspace/coverage/default/48.edn_smoke.728887426 Sep 27 01:04:33 PM PDT 23 Sep 27 01:04:34 PM PDT 23 27228289 ps
T591 /workspace/coverage/default/0.edn_intr.1776747176 Sep 27 01:03:13 PM PDT 23 Sep 27 01:03:15 PM PDT 23 26124047 ps
T592 /workspace/coverage/default/28.edn_alert_test.3687488178 Sep 27 01:03:14 PM PDT 23 Sep 27 01:03:15 PM PDT 23 48761793 ps
T593 /workspace/coverage/default/96.edn_err.1928950209 Sep 27 01:03:47 PM PDT 23 Sep 27 01:03:48 PM PDT 23 66881806 ps
T53 /workspace/coverage/default/0.edn_sec_cm.1259784901 Sep 27 01:00:15 PM PDT 23 Sep 27 01:00:19 PM PDT 23 468371538 ps
T594 /workspace/coverage/default/19.edn_smoke.1920149349 Sep 27 01:02:03 PM PDT 23 Sep 27 01:02:05 PM PDT 23 26057586 ps
T595 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.41284947 Sep 27 01:01:35 PM PDT 23 Sep 27 01:04:59 PM PDT 23 17212812176 ps
T596 /workspace/coverage/default/21.edn_intr.437818846 Sep 27 01:02:12 PM PDT 23 Sep 27 01:02:15 PM PDT 23 22508192 ps
T597 /workspace/coverage/default/36.edn_disable_auto_req_mode.3048452726 Sep 27 01:04:29 PM PDT 23 Sep 27 01:04:30 PM PDT 23 59358304 ps
T598 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2494273618 Sep 27 01:00:36 PM PDT 23 Sep 27 01:10:29 PM PDT 23 60603088895 ps
T599 /workspace/coverage/default/37.edn_stress_all.1293357822 Sep 27 01:02:56 PM PDT 23 Sep 27 01:02:59 PM PDT 23 536544706 ps
T600 /workspace/coverage/default/2.edn_stress_all.1987488231 Sep 27 01:02:04 PM PDT 23 Sep 27 01:02:08 PM PDT 23 164550765 ps
T601 /workspace/coverage/default/27.edn_alert_test.2528960646 Sep 27 01:02:22 PM PDT 23 Sep 27 01:02:23 PM PDT 23 21906546 ps
T602 /workspace/coverage/default/22.edn_genbits.258885918 Sep 27 01:01:30 PM PDT 23 Sep 27 01:01:31 PM PDT 23 15617511 ps
T285 /workspace/coverage/default/43.edn_err.1262076114 Sep 27 01:02:33 PM PDT 23 Sep 27 01:02:35 PM PDT 23 36921854 ps
T603 /workspace/coverage/default/40.edn_intr.1394382208 Sep 27 01:02:57 PM PDT 23 Sep 27 01:02:58 PM PDT 23 47458279 ps
T604 /workspace/coverage/default/7.edn_err.2126437842 Sep 27 01:02:42 PM PDT 23 Sep 27 01:02:43 PM PDT 23 73337484 ps
T605 /workspace/coverage/default/20.edn_err.938413127 Sep 27 01:01:50 PM PDT 23 Sep 27 01:01:51 PM PDT 23 20455696 ps
T606 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1737563332 Sep 27 01:02:57 PM PDT 23 Sep 27 01:21:37 PM PDT 23 72251982918 ps
T54 /workspace/coverage/default/3.edn_sec_cm.968029934 Sep 27 01:08:41 PM PDT 23 Sep 27 01:08:48 PM PDT 23 441927794 ps
T607 /workspace/coverage/default/18.edn_genbits.3714852658 Sep 27 01:02:15 PM PDT 23 Sep 27 01:02:16 PM PDT 23 105324848 ps
T251 /workspace/coverage/default/29.edn_err.3173957084 Sep 27 01:04:01 PM PDT 23 Sep 27 01:04:02 PM PDT 23 24497533 ps
T608 /workspace/coverage/default/44.edn_smoke.20256129 Sep 27 01:01:28 PM PDT 23 Sep 27 01:01:29 PM PDT 23 33178537 ps
T609 /workspace/coverage/default/49.edn_smoke.2651065148 Sep 27 01:03:01 PM PDT 23 Sep 27 01:03:04 PM PDT 23 14920133 ps
T106 /workspace/coverage/default/14.edn_disable.314157407 Sep 27 01:06:49 PM PDT 23 Sep 27 01:06:50 PM PDT 23 15669012 ps
T158 /workspace/coverage/default/82.edn_err.3392120776 Sep 27 01:01:40 PM PDT 23 Sep 27 01:01:41 PM PDT 23 22933912 ps
T610 /workspace/coverage/default/25.edn_smoke.331438711 Sep 27 01:02:15 PM PDT 23 Sep 27 01:02:16 PM PDT 23 65645168 ps
T294 /workspace/coverage/default/20.edn_alert.1284391592 Sep 27 01:01:05 PM PDT 23 Sep 27 01:01:07 PM PDT 23 31770511 ps
T611 /workspace/coverage/default/38.edn_smoke.2780706093 Sep 27 01:02:18 PM PDT 23 Sep 27 01:02:19 PM PDT 23 14807710 ps
T612 /workspace/coverage/default/16.edn_stress_all.1676179584 Sep 27 01:00:48 PM PDT 23 Sep 27 01:00:52 PM PDT 23 130658751 ps
T613 /workspace/coverage/default/23.edn_smoke.3645877331 Sep 27 01:02:04 PM PDT 23 Sep 27 01:02:05 PM PDT 23 23510941 ps
T614 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1974283597 Sep 27 01:01:17 PM PDT 23 Sep 27 01:21:45 PM PDT 23 48494181099 ps
T615 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.725192052 Sep 27 01:02:53 PM PDT 23 Sep 27 01:19:52 PM PDT 23 39066015176 ps
T616 /workspace/coverage/default/31.edn_alert.3351326991 Sep 27 01:01:07 PM PDT 23 Sep 27 01:01:08 PM PDT 23 20862299 ps
T273 /workspace/coverage/default/16.edn_genbits.3402512062 Sep 27 01:03:09 PM PDT 23 Sep 27 01:03:10 PM PDT 23 49525338 ps
T163 /workspace/coverage/default/95.edn_err.3629485665 Sep 27 01:01:39 PM PDT 23 Sep 27 01:01:40 PM PDT 23 68360524 ps
T617 /workspace/coverage/default/2.edn_alert.3196561808 Sep 27 01:01:03 PM PDT 23 Sep 27 01:01:04 PM PDT 23 29516291 ps
T618 /workspace/coverage/default/17.edn_intr.1354601856 Sep 27 01:02:51 PM PDT 23 Sep 27 01:02:52 PM PDT 23 23671830 ps
T619 /workspace/coverage/default/22.edn_alert_test.3544579957 Sep 27 01:03:56 PM PDT 23 Sep 27 01:03:57 PM PDT 23 61116604 ps
T620 /workspace/coverage/default/4.edn_disable.2636790995 Sep 27 01:00:25 PM PDT 23 Sep 27 01:00:26 PM PDT 23 22022214 ps
T271 /workspace/coverage/default/0.edn_genbits.1312974385 Sep 27 01:00:13 PM PDT 23 Sep 27 01:00:15 PM PDT 23 22341327 ps
T621 /workspace/coverage/default/0.edn_smoke.1072825687 Sep 27 01:00:12 PM PDT 23 Sep 27 01:00:13 PM PDT 23 43066705 ps
T622 /workspace/coverage/default/45.edn_intr.3715354165 Sep 27 01:04:48 PM PDT 23 Sep 27 01:04:49 PM PDT 23 21024572 ps
T289 /workspace/coverage/default/4.edn_genbits.3276721023 Sep 27 01:00:25 PM PDT 23 Sep 27 01:00:27 PM PDT 23 14675367 ps
T623 /workspace/coverage/default/10.edn_alert_test.2352253270 Sep 27 01:14:51 PM PDT 23 Sep 27 01:14:52 PM PDT 23 28976158 ps
T624 /workspace/coverage/default/44.edn_alert.509798201 Sep 27 01:01:29 PM PDT 23 Sep 27 01:01:30 PM PDT 23 28380858 ps
T248 /workspace/coverage/default/13.edn_disable.2731167086 Sep 27 01:02:08 PM PDT 23 Sep 27 01:02:09 PM PDT 23 46132128 ps
T625 /workspace/coverage/default/46.edn_stress_all.956436004 Sep 27 01:02:28 PM PDT 23 Sep 27 01:02:31 PM PDT 23 116636271 ps
T626 /workspace/coverage/default/85.edn_err.191034546 Sep 27 01:02:44 PM PDT 23 Sep 27 01:02:45 PM PDT 23 40827352 ps
T627 /workspace/coverage/default/37.edn_disable.1767715297 Sep 27 01:04:48 PM PDT 23 Sep 27 01:04:49 PM PDT 23 40939503 ps
T270 /workspace/coverage/default/23.edn_genbits.1800525531 Sep 27 01:02:30 PM PDT 23 Sep 27 01:02:31 PM PDT 23 20847980 ps
T628 /workspace/coverage/default/49.edn_alert.946678005 Sep 27 01:01:31 PM PDT 23 Sep 27 01:01:33 PM PDT 23 18092781 ps
T629 /workspace/coverage/default/37.edn_intr.3415191432 Sep 27 01:03:57 PM PDT 23 Sep 27 01:03:58 PM PDT 23 19409094 ps
T630 /workspace/coverage/default/46.edn_disable.2160452441 Sep 27 01:03:58 PM PDT 23 Sep 27 01:03:59 PM PDT 23 12691098 ps
T631 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2514012837 Sep 27 01:02:32 PM PDT 23 Sep 27 01:19:48 PM PDT 23 47703909674 ps
T632 /workspace/coverage/default/10.edn_genbits.2544579865 Sep 27 01:13:12 PM PDT 23 Sep 27 01:13:13 PM PDT 23 24173200 ps
T633 /workspace/coverage/default/34.edn_stress_all.2045899010 Sep 27 01:04:41 PM PDT 23 Sep 27 01:04:42 PM PDT 23 250866729 ps
T634 /workspace/coverage/default/12.edn_smoke.2598515880 Sep 27 01:03:24 PM PDT 23 Sep 27 01:03:25 PM PDT 23 13089316 ps
T635 /workspace/coverage/default/30.edn_smoke.3438000700 Sep 27 01:01:38 PM PDT 23 Sep 27 01:01:39 PM PDT 23 22001687 ps
T135 /workspace/coverage/default/44.edn_err.1025988383 Sep 27 01:02:06 PM PDT 23 Sep 27 01:02:07 PM PDT 23 19575348 ps
T636 /workspace/coverage/default/30.edn_stress_all.2293018712 Sep 27 01:02:58 PM PDT 23 Sep 27 01:03:02 PM PDT 23 558270941 ps
T637 /workspace/coverage/default/47.edn_smoke.1897097508 Sep 27 01:04:34 PM PDT 23 Sep 27 01:04:35 PM PDT 23 16949590 ps
T638 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1040748210 Sep 27 01:02:29 PM PDT 23 Sep 27 01:25:12 PM PDT 23 63602123933 ps
T639 /workspace/coverage/default/1.edn_genbits.1858406547 Sep 27 01:01:14 PM PDT 23 Sep 27 01:01:15 PM PDT 23 30879167 ps
T640 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1696037947 Sep 27 01:05:52 PM PDT 23 Sep 27 01:16:04 PM PDT 23 119115974033 ps
T291 /workspace/coverage/default/49.edn_genbits.4062758204 Sep 27 01:03:41 PM PDT 23 Sep 27 01:03:42 PM PDT 23 97336002 ps
T641 /workspace/coverage/default/25.edn_disable.486398537 Sep 27 01:02:24 PM PDT 23 Sep 27 01:02:25 PM PDT 23 31547507 ps
T642 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1191106221 Sep 27 01:02:12 PM PDT 23 Sep 27 01:19:40 PM PDT 23 96648452475 ps
T643 /workspace/coverage/default/26.edn_alert_test.1205650132 Sep 27 01:02:59 PM PDT 23 Sep 27 01:03:00 PM PDT 23 25659831 ps
T644 /workspace/coverage/default/8.edn_intr.4120692224 Sep 27 01:02:45 PM PDT 23 Sep 27 01:02:46 PM PDT 23 29150620 ps
T645 /workspace/coverage/default/69.edn_err.809159348 Sep 27 01:04:55 PM PDT 23 Sep 27 01:04:58 PM PDT 23 31380707 ps
T646 /workspace/coverage/default/14.edn_alert.1751277187 Sep 27 01:07:57 PM PDT 23 Sep 27 01:07:59 PM PDT 23 19836210 ps
T647 /workspace/coverage/default/27.edn_intr.4040339163 Sep 27 01:01:07 PM PDT 23 Sep 27 01:01:08 PM PDT 23 23564658 ps
T648 /workspace/coverage/default/41.edn_err.3516445221 Sep 27 01:01:28 PM PDT 23 Sep 27 01:01:29 PM PDT 23 28700383 ps
T282 /workspace/coverage/default/20.edn_genbits.3966673948 Sep 27 01:01:01 PM PDT 23 Sep 27 01:01:02 PM PDT 23 58050612 ps
T649 /workspace/coverage/default/32.edn_genbits.3618939183 Sep 27 01:03:02 PM PDT 23 Sep 27 01:03:04 PM PDT 23 48422356 ps
T650 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2108889163 Sep 27 01:03:46 PM PDT 23 Sep 27 01:09:03 PM PDT 23 225508184767 ps
T651 /workspace/coverage/default/36.edn_alert_test.3263959779 Sep 27 01:01:14 PM PDT 23 Sep 27 01:01:15 PM PDT 23 67219216 ps
T652 /workspace/coverage/default/0.edn_err.2424702278 Sep 27 01:02:58 PM PDT 23 Sep 27 01:02:59 PM PDT 23 43185864 ps
T304 /workspace/coverage/default/24.edn_alert.3205405714 Sep 27 01:04:10 PM PDT 23 Sep 27 01:04:11 PM PDT 23 41406718 ps
T653 /workspace/coverage/default/29.edn_alert_test.2245648352 Sep 27 01:03:43 PM PDT 23 Sep 27 01:03:44 PM PDT 23 39727799 ps
T165 /workspace/coverage/default/7.edn_disable.173583406 Sep 27 01:15:37 PM PDT 23 Sep 27 01:15:38 PM PDT 23 13710470 ps
T654 /workspace/coverage/default/46.edn_smoke.1956374874 Sep 27 01:08:26 PM PDT 23 Sep 27 01:08:27 PM PDT 23 13071029 ps
T655 /workspace/coverage/default/45.edn_smoke.1706561260 Sep 27 01:02:32 PM PDT 23 Sep 27 01:02:33 PM PDT 23 43159563 ps
T656 /workspace/coverage/default/37.edn_alert.278405548 Sep 27 01:02:56 PM PDT 23 Sep 27 01:02:58 PM PDT 23 31997329 ps
T657 /workspace/coverage/default/42.edn_intr.1379194127 Sep 27 01:02:28 PM PDT 23 Sep 27 01:02:29 PM PDT 23 17814698 ps
T176 /workspace/coverage/default/27.edn_disable.1339394346 Sep 27 01:02:33 PM PDT 23 Sep 27 01:02:34 PM PDT 23 37647778 ps
T658 /workspace/coverage/default/43.edn_stress_all.2887602345 Sep 27 01:02:40 PM PDT 23 Sep 27 01:02:42 PM PDT 23 89666884 ps
T659 /workspace/coverage/default/89.edn_err.456685996 Sep 27 01:02:16 PM PDT 23 Sep 27 01:02:18 PM PDT 23 19399347 ps
T660 /workspace/coverage/default/34.edn_err.3723374718 Sep 27 01:04:13 PM PDT 23 Sep 27 01:04:14 PM PDT 23 32295940 ps
T661 /workspace/coverage/default/22.edn_disable_auto_req_mode.81126986 Sep 27 01:02:15 PM PDT 23 Sep 27 01:02:16 PM PDT 23 59976758 ps
T662 /workspace/coverage/default/0.edn_alert.3339522774 Sep 27 01:03:13 PM PDT 23 Sep 27 01:03:15 PM PDT 23 60959569 ps
T663 /workspace/coverage/default/3.edn_intr.55747568 Sep 27 01:01:03 PM PDT 23 Sep 27 01:01:04 PM PDT 23 19651755 ps
T664 /workspace/coverage/default/88.edn_err.1070324621 Sep 27 01:03:12 PM PDT 23 Sep 27 01:03:13 PM PDT 23 20395126 ps
T665 /workspace/coverage/default/17.edn_err.1853766365 Sep 27 01:11:18 PM PDT 23 Sep 27 01:11:19 PM PDT 23 45668791 ps
T160 /workspace/coverage/default/39.edn_err.3003520255 Sep 27 01:03:15 PM PDT 23 Sep 27 01:03:16 PM PDT 23 32877263 ps
T252 /workspace/coverage/default/20.edn_disable.2634264864 Sep 27 01:02:23 PM PDT 23 Sep 27 01:02:24 PM PDT 23 16389211 ps
T666 /workspace/coverage/default/11.edn_smoke.1914767411 Sep 27 01:07:37 PM PDT 23 Sep 27 01:07:38 PM PDT 23 15155280 ps
T667 /workspace/coverage/default/26.edn_stress_all.2439708192 Sep 27 01:02:50 PM PDT 23 Sep 27 01:02:52 PM PDT 23 67396648 ps
T668 /workspace/coverage/default/39.edn_stress_all.603908024 Sep 27 01:02:50 PM PDT 23 Sep 27 01:02:53 PM PDT 23 134744186 ps
T669 /workspace/coverage/default/17.edn_stress_all.1410061362 Sep 27 01:02:58 PM PDT 23 Sep 27 01:03:02 PM PDT 23 381526577 ps
T670 /workspace/coverage/default/36.edn_intr.3189749679 Sep 27 01:03:16 PM PDT 23 Sep 27 01:03:17 PM PDT 23 37306500 ps
T671 /workspace/coverage/default/41.edn_stress_all.2127108631 Sep 27 01:02:53 PM PDT 23 Sep 27 01:02:55 PM PDT 23 365596590 ps
T672 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3312896465 Sep 27 01:02:06 PM PDT 23 Sep 27 01:07:46 PM PDT 23 29345873279 ps
T673 /workspace/coverage/default/35.edn_alert_test.3283344826 Sep 27 01:03:27 PM PDT 23 Sep 27 01:03:28 PM PDT 23 26858131 ps
T674 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1025997270 Sep 27 01:00:46 PM PDT 23 Sep 27 01:05:03 PM PDT 23 110413072486 ps
T675 /workspace/coverage/default/29.edn_smoke.3185475706 Sep 27 01:02:06 PM PDT 23 Sep 27 01:02:07 PM PDT 23 16927023 ps
T676 /workspace/coverage/default/5.edn_disable.1392287587 Sep 27 01:09:19 PM PDT 23 Sep 27 01:09:20 PM PDT 23 92464459 ps
T677 /workspace/coverage/default/13.edn_stress_all.623908641 Sep 27 01:01:52 PM PDT 23 Sep 27 01:01:54 PM PDT 23 47314434 ps
T678 /workspace/coverage/default/23.edn_err.4214785462 Sep 27 01:02:35 PM PDT 23 Sep 27 01:02:42 PM PDT 23 23756831 ps
T679 /workspace/coverage/default/36.edn_err.2265075155 Sep 27 01:02:17 PM PDT 23 Sep 27 01:02:18 PM PDT 23 23872143 ps
T680 /workspace/coverage/default/11.edn_intr.1150480160 Sep 27 01:01:57 PM PDT 23 Sep 27 01:01:58 PM PDT 23 25683733 ps
T298 /workspace/coverage/default/9.edn_regwen.4009184876 Sep 27 01:02:13 PM PDT 23 Sep 27 01:02:15 PM PDT 23 25601480 ps
T681 /workspace/coverage/default/39.edn_intr.3938163511 Sep 27 01:01:28 PM PDT 23 Sep 27 01:01:30 PM PDT 23 21934284 ps
T173 /workspace/coverage/default/35.edn_disable.2397139404 Sep 27 01:02:40 PM PDT 23 Sep 27 01:02:41 PM PDT 23 22435457 ps
T682 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1067394655 Sep 27 01:04:26 PM PDT 23 Sep 27 01:17:06 PM PDT 23 72489299329 ps
T683 /workspace/coverage/default/26.edn_disable_auto_req_mode.4242849372 Sep 27 01:01:58 PM PDT 23 Sep 27 01:01:59 PM PDT 23 40430500 ps
T283 /workspace/coverage/default/47.edn_disable_auto_req_mode.4168385927 Sep 27 01:02:15 PM PDT 23 Sep 27 01:02:16 PM PDT 23 19616210 ps
T684 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2403268296 Sep 27 01:03:06 PM PDT 23 Sep 27 01:32:10 PM PDT 23 79624516501 ps
T685 /workspace/coverage/default/80.edn_err.3532291500 Sep 27 01:03:19 PM PDT 23 Sep 27 01:03:20 PM PDT 23 51000528 ps
T686 /workspace/coverage/default/74.edn_err.3498148842 Sep 27 01:03:00 PM PDT 23 Sep 27 01:03:01 PM PDT 23 25014257 ps
T687 /workspace/coverage/default/32.edn_intr.1766562547 Sep 27 01:02:40 PM PDT 23 Sep 27 01:02:41 PM PDT 23 19414247 ps

Test location /workspace/coverage/default/20.edn_stress_all.3101254454
Short name T6
Test name
Test status
Simulation time 222153513 ps
CPU time 2.53 seconds
Started Sep 27 01:03:04 PM PDT 23
Finished Sep 27 01:03:07 PM PDT 23
Peak memory 206208 kb
Host smart-39530d24-7e2d-420a-9222-6a8fe0d43544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101254454 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3101254454
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_genbits.57214734
Short name T30
Test name
Test status
Simulation time 26444944 ps
CPU time 1.18 seconds
Started Sep 27 01:04:08 PM PDT 23
Finished Sep 27 01:04:09 PM PDT 23
Peak memory 205508 kb
Host smart-6abf1696-b70c-4d13-b00f-9e589cb4859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57214734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.57214734
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.675809186
Short name T8
Test name
Test status
Simulation time 38712618 ps
CPU time 1.21 seconds
Started Sep 27 01:04:48 PM PDT 23
Finished Sep 27 01:04:50 PM PDT 23
Peak memory 228852 kb
Host smart-a49e1a61-6b91-4aff-86a3-d98d66d37325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675809186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.675809186
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3654034573
Short name T25
Test name
Test status
Simulation time 15774331840 ps
CPU time 322.22 seconds
Started Sep 27 01:01:19 PM PDT 23
Finished Sep 27 01:06:45 PM PDT 23
Peak memory 215984 kb
Host smart-3dedc3c6-6860-4649-a939-96339cdb93b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654034573 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3654034573
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1030105083
Short name T14
Test name
Test status
Simulation time 51266469 ps
CPU time 0.91 seconds
Started Sep 27 01:03:58 PM PDT 23
Finished Sep 27 01:03:59 PM PDT 23
Peak memory 215060 kb
Host smart-6d92cd84-7bbd-40d6-971e-af364a785252
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030105083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1030105083
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1876547439
Short name T22
Test name
Test status
Simulation time 178909817 ps
CPU time 3.27 seconds
Started Sep 27 01:10:14 PM PDT 23
Finished Sep 27 01:10:18 PM PDT 23
Peak memory 232424 kb
Host smart-1e03ebfb-643a-4d60-8dfc-bf407e1d8b81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876547439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1876547439
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/48.edn_disable.293884702
Short name T1
Test name
Test status
Simulation time 17404597 ps
CPU time 0.83 seconds
Started Sep 27 01:02:02 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 214888 kb
Host smart-42f08dd9-55e2-4268-bfe2-c5a403d780c1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293884702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.293884702
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/16.edn_alert.647115969
Short name T33
Test name
Test status
Simulation time 39697568 ps
CPU time 0.97 seconds
Started Sep 27 01:08:47 PM PDT 23
Finished Sep 27 01:08:49 PM PDT 23
Peak memory 206488 kb
Host smart-1fdbeb74-c328-49f2-8b0a-30eef9c1b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647115969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.647115969
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/17.edn_genbits.1005401932
Short name T11
Test name
Test status
Simulation time 48024434 ps
CPU time 1.39 seconds
Started Sep 27 01:00:44 PM PDT 23
Finished Sep 27 01:00:45 PM PDT 23
Peak memory 205860 kb
Host smart-96b1edfa-3c63-4934-b358-d05b6440aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005401932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1005401932
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.3696217296
Short name T99
Test name
Test status
Simulation time 13781916 ps
CPU time 0.88 seconds
Started Sep 27 01:11:33 PM PDT 23
Finished Sep 27 01:11:34 PM PDT 23
Peak memory 205100 kb
Host smart-d58f32da-790f-41b4-a385-0a5ddeceef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696217296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3696217296
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/34.edn_intr.1451550175
Short name T41
Test name
Test status
Simulation time 26796863 ps
CPU time 0.86 seconds
Started Sep 27 01:03:23 PM PDT 23
Finished Sep 27 01:03:24 PM PDT 23
Peak memory 214904 kb
Host smart-e26847bd-ca74-4308-819b-e6c3eda97852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451550175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1451550175
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.942667399
Short name T274
Test name
Test status
Simulation time 289822042 ps
CPU time 1.6 seconds
Started Sep 27 01:14:13 PM PDT 23
Finished Sep 27 01:14:15 PM PDT 23
Peak memory 205876 kb
Host smart-6ee7479b-7c1f-4831-952d-2f41e874035f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942667399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.942667399
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/default/30.edn_disable.2958844971
Short name T75
Test name
Test status
Simulation time 48820052 ps
CPU time 0.82 seconds
Started Sep 27 01:08:44 PM PDT 23
Finished Sep 27 01:08:45 PM PDT 23
Peak memory 214920 kb
Host smart-ba390998-c585-4550-9993-1333809bb9ac
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958844971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2958844971
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.544462600
Short name T128
Test name
Test status
Simulation time 153954228876 ps
CPU time 1707.57 seconds
Started Sep 27 01:01:38 PM PDT 23
Finished Sep 27 01:30:06 PM PDT 23
Peak memory 219096 kb
Host smart-486aa1cf-ceb0-42e0-bf11-c342a503f912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544462600 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.544462600
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable.995315084
Short name T548
Test name
Test status
Simulation time 14474488 ps
CPU time 0.89 seconds
Started Sep 27 01:01:11 PM PDT 23
Finished Sep 27 01:01:12 PM PDT 23
Peak memory 215016 kb
Host smart-922dcf8c-9e1e-4070-8fcc-fac6217b990f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995315084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.995315084
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.314157407
Short name T106
Test name
Test status
Simulation time 15669012 ps
CPU time 0.79 seconds
Started Sep 27 01:06:49 PM PDT 23
Finished Sep 27 01:06:50 PM PDT 23
Peak memory 214752 kb
Host smart-92f8e501-748b-469a-bc61-8ad400185f66
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314157407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.314157407
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable.2706210619
Short name T77
Test name
Test status
Simulation time 41048099 ps
CPU time 0.73 seconds
Started Sep 27 01:04:16 PM PDT 23
Finished Sep 27 01:04:17 PM PDT 23
Peak memory 214740 kb
Host smart-dceed87f-24b8-454e-9d9f-2368420069f6
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706210619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2706210619
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1468883214
Short name T10
Test name
Test status
Simulation time 19025785 ps
CPU time 0.96 seconds
Started Sep 27 01:03:37 PM PDT 23
Finished Sep 27 01:03:38 PM PDT 23
Peak memory 215136 kb
Host smart-446b2206-fabf-43c6-8948-28fc57647db6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468883214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1468883214
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_intr.1304381180
Short name T58
Test name
Test status
Simulation time 17789764 ps
CPU time 1.15 seconds
Started Sep 27 01:02:16 PM PDT 23
Finished Sep 27 01:02:17 PM PDT 23
Peak memory 225848 kb
Host smart-c8e6097f-65f9-4555-9042-d52251a72466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304381180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1304381180
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.560889811
Short name T206
Test name
Test status
Simulation time 95622341 ps
CPU time 1.12 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:23 PM PDT 23
Peak memory 205788 kb
Host smart-eb50a32d-c9b6-4f34-9c29-c8c4d4cdba25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560889811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.560889811
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/24.edn_intr.3125435944
Short name T65
Test name
Test status
Simulation time 26569374 ps
CPU time 0.91 seconds
Started Sep 27 01:02:44 PM PDT 23
Finished Sep 27 01:02:46 PM PDT 23
Peak memory 214892 kb
Host smart-7f838ae1-b1ca-4d4a-8300-e9eab3e983d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125435944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3125435944
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/47.edn_disable.1270835267
Short name T34
Test name
Test status
Simulation time 11945774 ps
CPU time 0.84 seconds
Started Sep 27 01:01:52 PM PDT 23
Finished Sep 27 01:01:53 PM PDT 23
Peak memory 214884 kb
Host smart-ad6c7a19-f920-4b3e-97cd-3ac8f80924c8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270835267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1270835267
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/2.edn_genbits.1081483890
Short name T269
Test name
Test status
Simulation time 26417978 ps
CPU time 0.97 seconds
Started Sep 27 01:00:23 PM PDT 23
Finished Sep 27 01:00:24 PM PDT 23
Peak memory 205944 kb
Host smart-d0e2cd91-bb7b-48ea-a65e-8be45254d668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081483890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1081483890
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.4009184876
Short name T298
Test name
Test status
Simulation time 25601480 ps
CPU time 1.04 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:02:15 PM PDT 23
Peak memory 205708 kb
Host smart-a31ea9cb-9228-45cb-aad0-a2b9f72403b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009184876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4009184876
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/35.edn_disable.2397139404
Short name T173
Test name
Test status
Simulation time 22435457 ps
CPU time 0.87 seconds
Started Sep 27 01:02:40 PM PDT 23
Finished Sep 27 01:02:41 PM PDT 23
Peak memory 214924 kb
Host smart-2dc08b73-2011-4b10-a222-4b42610a5912
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397139404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2397139404
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.2731167086
Short name T248
Test name
Test status
Simulation time 46132128 ps
CPU time 0.78 seconds
Started Sep 27 01:02:08 PM PDT 23
Finished Sep 27 01:02:09 PM PDT 23
Peak memory 215028 kb
Host smart-851d211a-56bd-4652-bdee-e95f5c132e7c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731167086 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2731167086
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.1393863195
Short name T59
Test name
Test status
Simulation time 19153270 ps
CPU time 0.81 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:06 PM PDT 23
Peak memory 214820 kb
Host smart-c5406262-9bdb-4029-a3f7-ba1ba1804634
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393863195 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1393863195
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.486398537
Short name T641
Test name
Test status
Simulation time 31547507 ps
CPU time 0.91 seconds
Started Sep 27 01:02:24 PM PDT 23
Finished Sep 27 01:02:25 PM PDT 23
Peak memory 214964 kb
Host smart-99185dbc-a3fd-4a85-ae3a-803ac84efb86
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486398537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.486398537
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert.332124690
Short name T40
Test name
Test status
Simulation time 56913778 ps
CPU time 0.9 seconds
Started Sep 27 01:02:38 PM PDT 23
Finished Sep 27 01:02:39 PM PDT 23
Peak memory 205660 kb
Host smart-3dc6a7a6-46c3-4acc-a1bf-324ea16a889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332124690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.332124690
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert.1291030009
Short name T296
Test name
Test status
Simulation time 27324291 ps
CPU time 0.94 seconds
Started Sep 27 01:01:05 PM PDT 23
Finished Sep 27 01:01:06 PM PDT 23
Peak memory 205436 kb
Host smart-60b75d28-6163-4c6c-9b77-0d28b587ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291030009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1291030009
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert.188944207
Short name T561
Test name
Test status
Simulation time 62480125 ps
CPU time 0.91 seconds
Started Sep 27 01:02:01 PM PDT 23
Finished Sep 27 01:02:03 PM PDT 23
Peak memory 205552 kb
Host smart-4a9e73e1-59b8-4763-9716-bac73317e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188944207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.188944207
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/29.edn_genbits.3481854440
Short name T91
Test name
Test status
Simulation time 34287566 ps
CPU time 1.06 seconds
Started Sep 27 01:01:34 PM PDT 23
Finished Sep 27 01:01:35 PM PDT 23
Peak memory 205720 kb
Host smart-b95e5a64-11b6-4264-aebb-8b3451b10d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481854440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3481854440
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_genbits.2464737409
Short name T288
Test name
Test status
Simulation time 20015005 ps
CPU time 0.97 seconds
Started Sep 27 01:04:14 PM PDT 23
Finished Sep 27 01:04:20 PM PDT 23
Peak memory 205580 kb
Host smart-cae95e2c-b135-49cb-b311-cde0932cbb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464737409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2464737409
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4168385927
Short name T283
Test name
Test status
Simulation time 19616210 ps
CPU time 0.99 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:16 PM PDT 23
Peak memory 215160 kb
Host smart-d64da1bc-74d0-44cc-b1c3-e35db35b12fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168385927 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4168385927
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/76.edn_err.1644964593
Short name T133
Test name
Test status
Simulation time 62827315 ps
CPU time 1.03 seconds
Started Sep 27 01:03:09 PM PDT 23
Finished Sep 27 01:03:10 PM PDT 23
Peak memory 216460 kb
Host smart-09851665-0139-4614-96cd-21a25d9da1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644964593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1644964593
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/14.edn_alert_test.26917512
Short name T101
Test name
Test status
Simulation time 43829195 ps
CPU time 1.04 seconds
Started Sep 27 01:03:51 PM PDT 23
Finished Sep 27 01:03:52 PM PDT 23
Peak memory 205060 kb
Host smart-123a1ece-1d43-493e-81c0-3595dd982801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26917512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.26917512
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_genbits.2712914663
Short name T259
Test name
Test status
Simulation time 28820191 ps
CPU time 1.12 seconds
Started Sep 27 01:01:31 PM PDT 23
Finished Sep 27 01:01:32 PM PDT 23
Peak memory 206000 kb
Host smart-36349990-7d85-4ef5-b1e4-c9f213244177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712914663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2712914663
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_genbits.276385331
Short name T266
Test name
Test status
Simulation time 37465806 ps
CPU time 1 seconds
Started Sep 27 01:02:02 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 205748 kb
Host smart-f5eed566-4f4e-4fea-90cc-248237a4c2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276385331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.276385331
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_genbits.3276721023
Short name T289
Test name
Test status
Simulation time 14675367 ps
CPU time 1.03 seconds
Started Sep 27 01:00:25 PM PDT 23
Finished Sep 27 01:00:27 PM PDT 23
Peak memory 205812 kb
Host smart-b2b0d2bd-d732-4e8a-8dfe-c3ee29080857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276721023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3276721023
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_err.1262076114
Short name T285
Test name
Test status
Simulation time 36921854 ps
CPU time 1.35 seconds
Started Sep 27 01:02:33 PM PDT 23
Finished Sep 27 01:02:35 PM PDT 23
Peak memory 215040 kb
Host smart-4ec4a2ff-776c-466e-8e47-4e2d39400d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262076114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1262076114
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1337144242
Short name T279
Test name
Test status
Simulation time 82192040 ps
CPU time 2.12 seconds
Started Sep 27 01:14:39 PM PDT 23
Finished Sep 27 01:14:41 PM PDT 23
Peak memory 205856 kb
Host smart-bf59ba37-af32-437a-a682-c37ffc38d1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337144242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1337144242
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1312974385
Short name T271
Test name
Test status
Simulation time 22341327 ps
CPU time 1.3 seconds
Started Sep 27 01:00:13 PM PDT 23
Finished Sep 27 01:00:15 PM PDT 23
Peak memory 206032 kb
Host smart-7152bf78-2a45-4307-9c29-13db8f1e9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312974385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1312974385
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.301132697
Short name T109
Test name
Test status
Simulation time 21812338 ps
CPU time 0.84 seconds
Started Sep 27 01:03:48 PM PDT 23
Finished Sep 27 01:03:49 PM PDT 23
Peak memory 205036 kb
Host smart-5f2b2f73-4cf2-4545-abc0-621616e7e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301132697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.301132697
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/14.edn_genbits.1413302656
Short name T13
Test name
Test status
Simulation time 429605246 ps
CPU time 1.48 seconds
Started Sep 27 01:01:57 PM PDT 23
Finished Sep 27 01:01:58 PM PDT 23
Peak memory 206140 kb
Host smart-cfd42018-11fd-440a-95e8-699573f37b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413302656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1413302656
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2687714052
Short name T26
Test name
Test status
Simulation time 78740720786 ps
CPU time 291.86 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:07:05 PM PDT 23
Peak memory 215260 kb
Host smart-969108ff-f3be-4ffd-9d8b-873a9250fa94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687714052 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2687714052
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.3196561808
Short name T617
Test name
Test status
Simulation time 29516291 ps
CPU time 0.92 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 206472 kb
Host smart-e1f21a40-b4df-43fe-ae6f-12ca98f1ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196561808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3196561808
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_err.852012952
Short name T121
Test name
Test status
Simulation time 67971814 ps
CPU time 1.1 seconds
Started Sep 27 01:03:09 PM PDT 23
Finished Sep 27 01:03:11 PM PDT 23
Peak memory 228884 kb
Host smart-3314c149-d676-4f07-a2e1-a7892176ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852012952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.852012952
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/20.edn_alert.1284391592
Short name T294
Test name
Test status
Simulation time 31770511 ps
CPU time 1 seconds
Started Sep 27 01:01:05 PM PDT 23
Finished Sep 27 01:01:07 PM PDT 23
Peak memory 206544 kb
Host smart-37095408-254f-41fe-a5ee-9269f8cdd85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284391592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1284391592
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert.3205405714
Short name T304
Test name
Test status
Simulation time 41406718 ps
CPU time 0.89 seconds
Started Sep 27 01:04:10 PM PDT 23
Finished Sep 27 01:04:11 PM PDT 23
Peak memory 205224 kb
Host smart-f0894a50-1d9a-4d53-a228-f0d58d27e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205405714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3205405714
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_err.1579320696
Short name T132
Test name
Test status
Simulation time 24310304 ps
CPU time 1.12 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 214800 kb
Host smart-584dd51d-9c36-40ce-b010-919a786ee570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579320696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1579320696
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1236376144
Short name T272
Test name
Test status
Simulation time 18179735 ps
CPU time 1.18 seconds
Started Sep 27 01:01:46 PM PDT 23
Finished Sep 27 01:01:47 PM PDT 23
Peak memory 205980 kb
Host smart-9c499355-26f4-45ec-bf1c-aac63c63ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236376144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1236376144
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2530549394
Short name T267
Test name
Test status
Simulation time 96828193573 ps
CPU time 602.62 seconds
Started Sep 27 01:04:43 PM PDT 23
Finished Sep 27 01:14:46 PM PDT 23
Peak memory 215540 kb
Host smart-701901f5-c28f-4c6f-a747-a169510c5fee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530549394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2530549394
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_genbits.3270671603
Short name T90
Test name
Test status
Simulation time 61032695 ps
CPU time 0.94 seconds
Started Sep 27 01:04:13 PM PDT 23
Finished Sep 27 01:04:14 PM PDT 23
Peak memory 204572 kb
Host smart-0c12aaa8-00d6-4349-8fd5-be559fea2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270671603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3270671603
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_genbits.1696746014
Short name T140
Test name
Test status
Simulation time 174715103 ps
CPU time 1 seconds
Started Sep 27 01:04:33 PM PDT 23
Finished Sep 27 01:04:34 PM PDT 23
Peak memory 205580 kb
Host smart-3cd69490-72bd-46ae-afa0-93d920b55037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696746014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1696746014
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.681599434
Short name T214
Test name
Test status
Simulation time 11360966 ps
CPU time 0.84 seconds
Started Sep 27 01:14:32 PM PDT 23
Finished Sep 27 01:14:33 PM PDT 23
Peak memory 205768 kb
Host smart-77d5a1b3-9f51-407c-a7f8-3003e2d470a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681599434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.681599434
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/12.edn_err.1521631530
Short name T202
Test name
Test status
Simulation time 18316864 ps
CPU time 1.29 seconds
Started Sep 27 01:01:13 PM PDT 23
Finished Sep 27 01:01:14 PM PDT 23
Peak memory 216044 kb
Host smart-16feb951-71b0-4f8f-831d-cff132f92ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521631530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1521631530
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.3774706801
Short name T55
Test name
Test status
Simulation time 18533538 ps
CPU time 0.99 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 215148 kb
Host smart-5958cce1-6803-402b-8192-efe901ef27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774706801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3774706801
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/12.edn_intr.3129332470
Short name T465
Test name
Test status
Simulation time 20654550 ps
CPU time 0.86 seconds
Started Sep 27 01:02:51 PM PDT 23
Finished Sep 27 01:02:52 PM PDT 23
Peak memory 215096 kb
Host smart-3e3c3b22-cd07-4efb-98e8-27d5aa92c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129332470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3129332470
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.2598401617
Short name T164
Test name
Test status
Simulation time 12397541 ps
CPU time 0.86 seconds
Started Sep 27 01:02:11 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 214880 kb
Host smart-b53c7d02-f2df-4102-97c6-f77d10789521
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598401617 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2598401617
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.2733832715
Short name T167
Test name
Test status
Simulation time 12870544 ps
CPU time 0.88 seconds
Started Sep 27 01:07:50 PM PDT 23
Finished Sep 27 01:07:51 PM PDT 23
Peak memory 215048 kb
Host smart-4ce60101-ebc8-4761-9057-6aa052af0076
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733832715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2733832715
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.1601052690
Short name T67
Test name
Test status
Simulation time 16308973 ps
CPU time 0.82 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:47 PM PDT 23
Peak memory 214928 kb
Host smart-77caacd6-3c54-469c-968c-a39f6b3fa693
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601052690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1601052690
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.2998069168
Short name T104
Test name
Test status
Simulation time 34895026 ps
CPU time 0.9 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:30 PM PDT 23
Peak memory 214852 kb
Host smart-62aaaff4-2561-4130-9a91-97f895f6dfeb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998069168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2998069168
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3437590369
Short name T424
Test name
Test status
Simulation time 130740517 ps
CPU time 3.39 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:30 PM PDT 23
Peak memory 205820 kb
Host smart-4c4adb68-3685-47e3-9159-b6dfe67a56bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437590369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3437590369
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1278441961
Short name T131
Test name
Test status
Simulation time 16012272 ps
CPU time 0.92 seconds
Started Sep 27 01:14:14 PM PDT 23
Finished Sep 27 01:14:15 PM PDT 23
Peak memory 205784 kb
Host smart-7de27f23-ba31-4fde-ba5b-fc84292d0ddd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278441961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1278441961
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.118866145
Short name T189
Test name
Test status
Simulation time 17575695 ps
CPU time 0.99 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:23 PM PDT 23
Peak memory 205796 kb
Host smart-53dee323-0971-4897-88bb-64bbe193d3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118866145 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.118866145
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.426320383
Short name T399
Test name
Test status
Simulation time 20891123 ps
CPU time 0.83 seconds
Started Sep 27 01:14:31 PM PDT 23
Finished Sep 27 01:14:32 PM PDT 23
Peak memory 205704 kb
Host smart-158309fa-ecf1-4ee1-b6fb-3cf8b8a0657c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426320383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.426320383
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2072878145
Short name T231
Test name
Test status
Simulation time 64188331 ps
CPU time 0.92 seconds
Started Sep 27 01:14:16 PM PDT 23
Finished Sep 27 01:14:17 PM PDT 23
Peak memory 205708 kb
Host smart-f69c7ea0-e768-4029-8f7f-0f8b007dde67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072878145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2072878145
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1275336917
Short name T380
Test name
Test status
Simulation time 49245235 ps
CPU time 3.12 seconds
Started Sep 27 01:14:16 PM PDT 23
Finished Sep 27 01:14:19 PM PDT 23
Peak memory 214160 kb
Host smart-104e7a23-8274-4862-8249-57b3b0cd00a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275336917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1275336917
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1198847547
Short name T427
Test name
Test status
Simulation time 64694979 ps
CPU time 1.84 seconds
Started Sep 27 01:14:31 PM PDT 23
Finished Sep 27 01:14:33 PM PDT 23
Peak memory 205896 kb
Host smart-4af313b3-b45d-4163-812f-f19bac5d555c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198847547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1198847547
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2412185397
Short name T381
Test name
Test status
Simulation time 200994690 ps
CPU time 1.04 seconds
Started Sep 27 01:14:23 PM PDT 23
Finished Sep 27 01:14:24 PM PDT 23
Peak memory 205784 kb
Host smart-b7c95d2f-940d-4612-9c21-b0e1f88bda7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412185397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2412185397
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3506698608
Short name T423
Test name
Test status
Simulation time 61008089 ps
CPU time 3.2 seconds
Started Sep 27 01:14:32 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 205792 kb
Host smart-d683f417-80a1-46f2-a7ea-ca8ecf4c20ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506698608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3506698608
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2754937264
Short name T205
Test name
Test status
Simulation time 23665164 ps
CPU time 0.89 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 205860 kb
Host smart-c21ffdb5-8b50-40e2-bd7c-3f2b84a445e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754937264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2754937264
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1576966886
Short name T184
Test name
Test status
Simulation time 37092446 ps
CPU time 1.3 seconds
Started Sep 27 01:14:24 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 214128 kb
Host smart-87410438-8c2a-4946-ae5f-95e479ac5577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576966886 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1576966886
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3012975059
Short name T394
Test name
Test status
Simulation time 58921048 ps
CPU time 0.85 seconds
Started Sep 27 01:14:17 PM PDT 23
Finished Sep 27 01:14:18 PM PDT 23
Peak memory 205780 kb
Host smart-ac5ef550-bacd-4506-b787-1ca8f39e9ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012975059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3012975059
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3224449618
Short name T408
Test name
Test status
Simulation time 26889235 ps
CPU time 0.81 seconds
Started Sep 27 01:14:11 PM PDT 23
Finished Sep 27 01:14:12 PM PDT 23
Peak memory 205608 kb
Host smart-c6591ea6-4705-4528-9b01-03889a6a8fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224449618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3224449618
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2001379066
Short name T416
Test name
Test status
Simulation time 15243415 ps
CPU time 1.07 seconds
Started Sep 27 01:14:13 PM PDT 23
Finished Sep 27 01:14:14 PM PDT 23
Peak memory 206056 kb
Host smart-47a8c45d-b613-4a31-b61d-929bf3d4e844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001379066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2001379066
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2210912136
Short name T393
Test name
Test status
Simulation time 99317237 ps
CPU time 2.55 seconds
Started Sep 27 01:14:38 PM PDT 23
Finished Sep 27 01:14:41 PM PDT 23
Peak memory 214176 kb
Host smart-a3601aff-3ae4-46b7-bb48-1e44798298ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210912136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2210912136
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.322361443
Short name T398
Test name
Test status
Simulation time 272552951 ps
CPU time 2.16 seconds
Started Sep 27 01:14:36 PM PDT 23
Finished Sep 27 01:14:38 PM PDT 23
Peak memory 205912 kb
Host smart-c4d8a03b-d8c4-4b6d-a483-4aeb5ac1c612
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322361443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.322361443
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2110976683
Short name T234
Test name
Test status
Simulation time 35716299 ps
CPU time 1.49 seconds
Started Sep 27 01:15:09 PM PDT 23
Finished Sep 27 01:15:11 PM PDT 23
Peak memory 222328 kb
Host smart-a4a376a1-fbcc-4f31-8c64-c3e66e69b6fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110976683 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2110976683
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1400881574
Short name T414
Test name
Test status
Simulation time 19448725 ps
CPU time 0.79 seconds
Started Sep 27 01:14:29 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 205668 kb
Host smart-bc2c9a92-5354-4d6e-b888-3b9f8f12a955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400881574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1400881574
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2112830659
Short name T362
Test name
Test status
Simulation time 14580783 ps
CPU time 0.82 seconds
Started Sep 27 01:14:51 PM PDT 23
Finished Sep 27 01:14:52 PM PDT 23
Peak memory 205760 kb
Host smart-0eb1a271-eee2-4667-ad94-ecb30c9420e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112830659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2112830659
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3583609980
Short name T185
Test name
Test status
Simulation time 375490847 ps
CPU time 1.29 seconds
Started Sep 27 01:15:34 PM PDT 23
Finished Sep 27 01:15:35 PM PDT 23
Peak memory 205896 kb
Host smart-78802843-4adb-4829-aad8-d00c8093ebae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583609980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3583609980
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3091842475
Short name T359
Test name
Test status
Simulation time 27106288 ps
CPU time 1.47 seconds
Started Sep 27 01:15:01 PM PDT 23
Finished Sep 27 01:15:03 PM PDT 23
Peak memory 214216 kb
Host smart-0b42f1c7-c499-4f80-868e-9193baba9c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091842475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3091842475
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2406592023
Short name T237
Test name
Test status
Simulation time 57129452 ps
CPU time 1.72 seconds
Started Sep 27 01:14:58 PM PDT 23
Finished Sep 27 01:15:00 PM PDT 23
Peak memory 205796 kb
Host smart-299683c0-a82a-4998-a72f-31741a228c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406592023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2406592023
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.660271822
Short name T374
Test name
Test status
Simulation time 15301974 ps
CPU time 0.93 seconds
Started Sep 27 01:15:22 PM PDT 23
Finished Sep 27 01:15:23 PM PDT 23
Peak memory 205928 kb
Host smart-9a72f240-0f2a-4f1f-9db7-1531e5590659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660271822 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.660271822
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.820845055
Short name T235
Test name
Test status
Simulation time 15253112 ps
CPU time 0.88 seconds
Started Sep 27 01:15:03 PM PDT 23
Finished Sep 27 01:15:04 PM PDT 23
Peak memory 205816 kb
Host smart-687badf3-efba-4822-9e6c-c333c26b77b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820845055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.820845055
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4146915360
Short name T327
Test name
Test status
Simulation time 14873225 ps
CPU time 0.82 seconds
Started Sep 27 01:15:40 PM PDT 23
Finished Sep 27 01:15:41 PM PDT 23
Peak memory 205796 kb
Host smart-f174f21a-c508-4720-9590-96bae7a2b8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146915360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4146915360
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1237846692
Short name T352
Test name
Test status
Simulation time 31664133 ps
CPU time 1.09 seconds
Started Sep 27 01:15:02 PM PDT 23
Finished Sep 27 01:15:03 PM PDT 23
Peak memory 205828 kb
Host smart-134f1901-c967-422f-a2df-101312f595ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237846692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1237846692
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2507879833
Short name T209
Test name
Test status
Simulation time 51242158 ps
CPU time 1.76 seconds
Started Sep 27 01:15:35 PM PDT 23
Finished Sep 27 01:15:37 PM PDT 23
Peak memory 214072 kb
Host smart-117be6d9-1475-4a5a-b46b-6d84c6eb1819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507879833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2507879833
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.68418829
Short name T211
Test name
Test status
Simulation time 99444237 ps
CPU time 1.53 seconds
Started Sep 27 01:14:59 PM PDT 23
Finished Sep 27 01:15:01 PM PDT 23
Peak memory 205840 kb
Host smart-3b5830e9-6886-44f1-837d-bcbea827f3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68418829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.68418829
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3065559840
Short name T339
Test name
Test status
Simulation time 54257018 ps
CPU time 1.23 seconds
Started Sep 27 01:14:20 PM PDT 23
Finished Sep 27 01:14:21 PM PDT 23
Peak memory 213992 kb
Host smart-5b1d6f1b-7382-4df5-baea-6ce875e2b908
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065559840 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3065559840
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3797656757
Short name T375
Test name
Test status
Simulation time 42824160 ps
CPU time 0.8 seconds
Started Sep 27 01:14:31 PM PDT 23
Finished Sep 27 01:14:32 PM PDT 23
Peak memory 205852 kb
Host smart-86d526de-ac3d-47b6-9981-10671f164bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797656757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3797656757
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2225636345
Short name T395
Test name
Test status
Simulation time 77466883 ps
CPU time 0.77 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 205604 kb
Host smart-0e47f28c-d86d-4e3f-8b0d-ae82e98ecb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225636345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2225636345
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4282446798
Short name T188
Test name
Test status
Simulation time 83272535 ps
CPU time 1.09 seconds
Started Sep 27 01:14:44 PM PDT 23
Finished Sep 27 01:14:45 PM PDT 23
Peak memory 205816 kb
Host smart-90cc1d56-eaab-493a-9029-e8a0a71ea349
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282446798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4282446798
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4136347409
Short name T354
Test name
Test status
Simulation time 198350344 ps
CPU time 2.97 seconds
Started Sep 27 01:14:25 PM PDT 23
Finished Sep 27 01:14:29 PM PDT 23
Peak memory 214224 kb
Host smart-5d65c1d8-cf64-49c5-85b5-793d74d434b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136347409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4136347409
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2399287956
Short name T278
Test name
Test status
Simulation time 171826856 ps
CPU time 1.43 seconds
Started Sep 27 01:14:18 PM PDT 23
Finished Sep 27 01:14:19 PM PDT 23
Peak memory 205848 kb
Host smart-5c9c7b2f-823b-4d57-8464-5fb66cfb166d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399287956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2399287956
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.580801811
Short name T371
Test name
Test status
Simulation time 20875839 ps
CPU time 1.4 seconds
Started Sep 27 01:15:24 PM PDT 23
Finished Sep 27 01:15:26 PM PDT 23
Peak memory 214176 kb
Host smart-44dec476-45e8-4219-8f16-6abcb190e988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580801811 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.580801811
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.231794394
Short name T376
Test name
Test status
Simulation time 111676589 ps
CPU time 0.85 seconds
Started Sep 27 01:14:22 PM PDT 23
Finished Sep 27 01:14:23 PM PDT 23
Peak memory 205800 kb
Host smart-5cf5bfdb-c7cc-4c73-b9fb-86016e4457c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231794394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.231794394
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1890892235
Short name T382
Test name
Test status
Simulation time 14183488 ps
CPU time 0.83 seconds
Started Sep 27 01:14:20 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 205652 kb
Host smart-e445bbe5-ffe0-4978-858f-15567698b27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890892235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1890892235
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3412409672
Short name T370
Test name
Test status
Simulation time 37334871 ps
CPU time 1.05 seconds
Started Sep 27 01:14:42 PM PDT 23
Finished Sep 27 01:14:43 PM PDT 23
Peak memory 205860 kb
Host smart-fdc9754c-f59d-44a9-901c-4dea4dda267b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412409672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3412409672
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.495095191
Short name T340
Test name
Test status
Simulation time 133141685 ps
CPU time 2.53 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:24 PM PDT 23
Peak memory 214100 kb
Host smart-ad6a191a-6cb8-490b-945a-3bc033787235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495095191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.495095191
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1475923824
Short name T180
Test name
Test status
Simulation time 337937391 ps
CPU time 2.26 seconds
Started Sep 27 01:14:33 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 205880 kb
Host smart-170e5829-3c7f-4c4e-8851-121485cd076c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475923824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1475923824
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1607914592
Short name T348
Test name
Test status
Simulation time 92807070 ps
CPU time 1.7 seconds
Started Sep 27 01:15:02 PM PDT 23
Finished Sep 27 01:15:04 PM PDT 23
Peak memory 222292 kb
Host smart-b3b5cc82-e3da-4d0e-8727-3d07855dd128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607914592 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1607914592
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3539473715
Short name T366
Test name
Test status
Simulation time 41336695 ps
CPU time 0.74 seconds
Started Sep 27 01:14:38 PM PDT 23
Finished Sep 27 01:14:39 PM PDT 23
Peak memory 205632 kb
Host smart-f041b31f-d01f-40a6-b784-6b1f127887a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539473715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3539473715
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2701305285
Short name T326
Test name
Test status
Simulation time 11759186 ps
CPU time 0.84 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:28 PM PDT 23
Peak memory 205780 kb
Host smart-aa73c904-8ad4-4b9e-adff-a6166fd4b012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701305285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2701305285
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1358339306
Short name T415
Test name
Test status
Simulation time 29179016 ps
CPU time 1.04 seconds
Started Sep 27 01:14:39 PM PDT 23
Finished Sep 27 01:14:40 PM PDT 23
Peak memory 205956 kb
Host smart-6fb2b54b-5394-4511-acc0-f68cb917dbad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358339306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1358339306
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1572565732
Short name T378
Test name
Test status
Simulation time 138073343 ps
CPU time 3.8 seconds
Started Sep 27 01:14:24 PM PDT 23
Finished Sep 27 01:14:28 PM PDT 23
Peak memory 214084 kb
Host smart-3c44ee21-b525-48e9-b3cc-00f15f313da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572565732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1572565732
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1570204170
Short name T429
Test name
Test status
Simulation time 209890385 ps
CPU time 1.44 seconds
Started Sep 27 01:15:15 PM PDT 23
Finished Sep 27 01:15:16 PM PDT 23
Peak memory 205844 kb
Host smart-7b73000a-4b24-4625-8ce5-5dfae569994f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570204170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1570204170
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3095306176
Short name T372
Test name
Test status
Simulation time 20181563 ps
CPU time 1.11 seconds
Started Sep 27 01:14:28 PM PDT 23
Finished Sep 27 01:14:29 PM PDT 23
Peak memory 214116 kb
Host smart-767287e7-4dcf-409e-ac51-b5c68d907c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095306176 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3095306176
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2909649377
Short name T407
Test name
Test status
Simulation time 15175134 ps
CPU time 0.89 seconds
Started Sep 27 01:15:07 PM PDT 23
Finished Sep 27 01:15:08 PM PDT 23
Peak memory 205868 kb
Host smart-7e2233d4-d0c5-43aa-86f2-cf6992060b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909649377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2909649377
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.572516422
Short name T391
Test name
Test status
Simulation time 35430459 ps
CPU time 0.82 seconds
Started Sep 27 01:15:48 PM PDT 23
Finished Sep 27 01:15:49 PM PDT 23
Peak memory 205600 kb
Host smart-87383fc9-d4ed-400d-b3c0-69762cf2b602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572516422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.572516422
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.681223478
Short name T240
Test name
Test status
Simulation time 29023012 ps
CPU time 1 seconds
Started Sep 27 01:15:47 PM PDT 23
Finished Sep 27 01:15:49 PM PDT 23
Peak memory 205788 kb
Host smart-455e89e5-4163-4451-8b6d-e572b4b1abc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681223478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.681223478
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.381066188
Short name T410
Test name
Test status
Simulation time 66820063 ps
CPU time 2.07 seconds
Started Sep 27 01:14:24 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 217068 kb
Host smart-d9c8eb4a-d603-4d91-b26d-60e0d590701f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381066188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.381066188
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2153967738
Short name T198
Test name
Test status
Simulation time 154256567 ps
CPU time 2.22 seconds
Started Sep 27 01:14:30 PM PDT 23
Finished Sep 27 01:14:33 PM PDT 23
Peak memory 205880 kb
Host smart-b2e3e038-67e6-44c9-a342-6d0ac503e40e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153967738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2153967738
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1895488646
Short name T350
Test name
Test status
Simulation time 77632228 ps
CPU time 1.09 seconds
Started Sep 27 01:15:05 PM PDT 23
Finished Sep 27 01:15:06 PM PDT 23
Peak memory 214160 kb
Host smart-789612b8-09ee-4f11-9594-d9a12de63b7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895488646 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1895488646
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.190055518
Short name T221
Test name
Test status
Simulation time 15224154 ps
CPU time 0.93 seconds
Started Sep 27 01:15:14 PM PDT 23
Finished Sep 27 01:15:15 PM PDT 23
Peak memory 205868 kb
Host smart-04bac074-21bf-4f4d-a40e-c023d9a65e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190055518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.190055518
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.454910932
Short name T373
Test name
Test status
Simulation time 19629246 ps
CPU time 0.8 seconds
Started Sep 27 01:14:35 PM PDT 23
Finished Sep 27 01:14:36 PM PDT 23
Peak memory 205788 kb
Host smart-cfc1213b-944d-49a1-aef9-92b1a4527029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454910932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.454910932
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2405552378
Short name T238
Test name
Test status
Simulation time 27516937 ps
CPU time 0.97 seconds
Started Sep 27 01:15:22 PM PDT 23
Finished Sep 27 01:15:24 PM PDT 23
Peak memory 205868 kb
Host smart-82f153d8-b07f-4d29-a4de-0d10e4e99877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405552378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2405552378
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1854311176
Short name T187
Test name
Test status
Simulation time 428622352 ps
CPU time 3.92 seconds
Started Sep 27 01:15:05 PM PDT 23
Finished Sep 27 01:15:09 PM PDT 23
Peak memory 213916 kb
Host smart-37c6cc20-cf5b-4968-b28c-9c05cacb5d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854311176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1854311176
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.529221484
Short name T357
Test name
Test status
Simulation time 18114120 ps
CPU time 1.02 seconds
Started Sep 27 01:15:51 PM PDT 23
Finished Sep 27 01:15:52 PM PDT 23
Peak memory 214260 kb
Host smart-6a3dd3a3-abc7-4802-9edb-8ced099a3755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529221484 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.529221484
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2131464759
Short name T222
Test name
Test status
Simulation time 14032010 ps
CPU time 0.89 seconds
Started Sep 27 01:15:47 PM PDT 23
Finished Sep 27 01:15:48 PM PDT 23
Peak memory 205872 kb
Host smart-8876f7dc-5ca0-4de8-9d5c-ebc67b861605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131464759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2131464759
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1759057365
Short name T323
Test name
Test status
Simulation time 30063728 ps
CPU time 0.84 seconds
Started Sep 27 01:15:26 PM PDT 23
Finished Sep 27 01:15:27 PM PDT 23
Peak memory 205664 kb
Host smart-f693c1b7-3a3a-486d-b4de-b72f8451cdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759057365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1759057365
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4274058476
Short name T212
Test name
Test status
Simulation time 19084406 ps
CPU time 1.13 seconds
Started Sep 27 01:15:36 PM PDT 23
Finished Sep 27 01:15:37 PM PDT 23
Peak memory 205840 kb
Host smart-67f4b845-9ec7-4188-a72a-deb019fd6077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274058476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4274058476
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3810437487
Short name T397
Test name
Test status
Simulation time 395712929 ps
CPU time 3.66 seconds
Started Sep 27 01:15:24 PM PDT 23
Finished Sep 27 01:15:28 PM PDT 23
Peak memory 214224 kb
Host smart-b4df02f2-ec9b-41c4-91ca-91a14c710b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810437487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3810437487
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.159454677
Short name T332
Test name
Test status
Simulation time 734540437 ps
CPU time 6.41 seconds
Started Sep 27 01:15:02 PM PDT 23
Finished Sep 27 01:15:09 PM PDT 23
Peak memory 205860 kb
Host smart-f0043df6-4b74-4611-b7ae-0d80208f5193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159454677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.159454677
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.81788558
Short name T179
Test name
Test status
Simulation time 85948500 ps
CPU time 1.23 seconds
Started Sep 27 01:15:05 PM PDT 23
Finished Sep 27 01:15:06 PM PDT 23
Peak memory 214172 kb
Host smart-a9eebd71-e99f-4cd0-ade6-67f98ffcebe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81788558 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.81788558
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3164038105
Short name T223
Test name
Test status
Simulation time 39631237 ps
CPU time 0.83 seconds
Started Sep 27 01:16:37 PM PDT 23
Finished Sep 27 01:16:38 PM PDT 23
Peak memory 205660 kb
Host smart-1e45bc1d-cae0-410b-a286-f5bf788c9345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164038105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3164038105
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.415028171
Short name T197
Test name
Test status
Simulation time 15046028 ps
CPU time 0.82 seconds
Started Sep 27 01:15:58 PM PDT 23
Finished Sep 27 01:15:59 PM PDT 23
Peak memory 205788 kb
Host smart-ff49afbe-66c4-4da5-b50e-5a3b4a9188ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415028171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.415028171
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.845779800
Short name T409
Test name
Test status
Simulation time 21237782 ps
CPU time 1.16 seconds
Started Sep 27 01:16:29 PM PDT 23
Finished Sep 27 01:16:31 PM PDT 23
Peak memory 205884 kb
Host smart-139cba7d-1303-4f15-9801-58e6a8506334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845779800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.845779800
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1778672142
Short name T195
Test name
Test status
Simulation time 256097261 ps
CPU time 2.08 seconds
Started Sep 27 01:16:01 PM PDT 23
Finished Sep 27 01:16:03 PM PDT 23
Peak memory 214136 kb
Host smart-5abcfdd7-5fc4-44ee-9cc5-d160fa55e4a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778672142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1778672142
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3419731035
Short name T422
Test name
Test status
Simulation time 109953252 ps
CPU time 1.32 seconds
Started Sep 27 01:15:44 PM PDT 23
Finished Sep 27 01:15:46 PM PDT 23
Peak memory 205856 kb
Host smart-aeca3983-6097-4655-bdd0-e484afefcea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419731035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3419731035
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2167401586
Short name T358
Test name
Test status
Simulation time 37766767 ps
CPU time 1.1 seconds
Started Sep 27 01:16:34 PM PDT 23
Finished Sep 27 01:16:35 PM PDT 23
Peak memory 214080 kb
Host smart-63e80f44-fd0a-45ab-bbed-2730660719be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167401586 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2167401586
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1096661326
Short name T383
Test name
Test status
Simulation time 34261530 ps
CPU time 0.82 seconds
Started Sep 27 01:16:30 PM PDT 23
Finished Sep 27 01:16:31 PM PDT 23
Peak memory 205840 kb
Host smart-3749b6f5-569c-45bf-9603-db1838e06ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096661326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1096661326
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1934473330
Short name T386
Test name
Test status
Simulation time 26653336 ps
CPU time 0.84 seconds
Started Sep 27 01:16:40 PM PDT 23
Finished Sep 27 01:16:41 PM PDT 23
Peak memory 205736 kb
Host smart-e014ed2a-b15c-4727-bc10-fd88c7f0117a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934473330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1934473330
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2278069818
Short name T392
Test name
Test status
Simulation time 16907501 ps
CPU time 1.05 seconds
Started Sep 27 01:16:43 PM PDT 23
Finished Sep 27 01:16:44 PM PDT 23
Peak memory 205748 kb
Host smart-be8abaca-0116-4691-8bed-5cab9f414e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278069818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2278069818
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.77600074
Short name T413
Test name
Test status
Simulation time 48793631 ps
CPU time 3.02 seconds
Started Sep 27 01:16:52 PM PDT 23
Finished Sep 27 01:16:55 PM PDT 23
Peak memory 214080 kb
Host smart-3c4e0d28-09b3-4bc3-aa43-465d93c3fa62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77600074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.77600074
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3297777239
Short name T275
Test name
Test status
Simulation time 169771110 ps
CPU time 1.95 seconds
Started Sep 27 01:15:31 PM PDT 23
Finished Sep 27 01:15:33 PM PDT 23
Peak memory 205960 kb
Host smart-de9110d3-875a-4f13-b753-2141e3749bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297777239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3297777239
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3388786361
Short name T216
Test name
Test status
Simulation time 309950955 ps
CPU time 1.24 seconds
Started Sep 27 01:15:07 PM PDT 23
Finished Sep 27 01:15:08 PM PDT 23
Peak memory 205832 kb
Host smart-a78e7ce0-734c-4f59-a644-d827287215f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388786361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3388786361
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3134001684
Short name T224
Test name
Test status
Simulation time 35526278 ps
CPU time 1.96 seconds
Started Sep 27 01:14:57 PM PDT 23
Finished Sep 27 01:14:59 PM PDT 23
Peak memory 205956 kb
Host smart-d24edecd-5e6a-42c1-b478-8ef707c72efe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134001684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3134001684
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1469228484
Short name T220
Test name
Test status
Simulation time 29477978 ps
CPU time 0.89 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 205828 kb
Host smart-42b370a0-0b19-44cd-b247-ff0065cd3bd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469228484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1469228484
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2023339908
Short name T419
Test name
Test status
Simulation time 14351016 ps
CPU time 0.92 seconds
Started Sep 27 01:15:41 PM PDT 23
Finished Sep 27 01:15:42 PM PDT 23
Peak memory 205860 kb
Host smart-9c9426e9-7577-4fa8-8042-1cc982d5932d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023339908 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2023339908
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1001407866
Short name T219
Test name
Test status
Simulation time 41117946 ps
CPU time 0.88 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 205860 kb
Host smart-06abc32d-266a-4261-a514-ecb68d42d8e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001407866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1001407866
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2991747283
Short name T230
Test name
Test status
Simulation time 49895176 ps
CPU time 0.83 seconds
Started Sep 27 01:14:34 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 205760 kb
Host smart-12ab7516-b4f4-4c14-a1f1-271345c53f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991747283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2991747283
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2239369247
Short name T239
Test name
Test status
Simulation time 52319380 ps
CPU time 1.28 seconds
Started Sep 27 01:16:09 PM PDT 23
Finished Sep 27 01:16:11 PM PDT 23
Peak memory 205876 kb
Host smart-6f432298-ae3c-46da-8ac9-4241102f9fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239369247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2239369247
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4004222590
Short name T342
Test name
Test status
Simulation time 20326179 ps
CPU time 1.34 seconds
Started Sep 27 01:14:35 PM PDT 23
Finished Sep 27 01:14:37 PM PDT 23
Peak memory 213956 kb
Host smart-0a1f34b4-0988-47ff-b1df-9e4cbdb643cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004222590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4004222590
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2106649306
Short name T425
Test name
Test status
Simulation time 24092042 ps
CPU time 0.82 seconds
Started Sep 27 01:14:38 PM PDT 23
Finished Sep 27 01:14:42 PM PDT 23
Peak memory 205784 kb
Host smart-8ae22967-c54e-4f22-9919-537b6fea28c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106649306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2106649306
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1508015519
Short name T384
Test name
Test status
Simulation time 16431575 ps
CPU time 0.86 seconds
Started Sep 27 01:15:13 PM PDT 23
Finished Sep 27 01:15:15 PM PDT 23
Peak memory 205804 kb
Host smart-dd4b9d3d-19a1-4671-8bf9-b8dfc2a2e818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508015519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1508015519
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4272387723
Short name T388
Test name
Test status
Simulation time 42764686 ps
CPU time 0.74 seconds
Started Sep 27 01:14:37 PM PDT 23
Finished Sep 27 01:14:38 PM PDT 23
Peak memory 205624 kb
Host smart-eea1bb52-c9a4-4a65-8dc4-0e5c17bc01bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272387723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4272387723
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2029490660
Short name T331
Test name
Test status
Simulation time 18263300 ps
CPU time 0.81 seconds
Started Sep 27 01:14:25 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 205724 kb
Host smart-e069cff8-0a90-4d3b-9679-6b4ea9b3b1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029490660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2029490660
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3887592743
Short name T406
Test name
Test status
Simulation time 59753450 ps
CPU time 0.77 seconds
Started Sep 27 01:14:55 PM PDT 23
Finished Sep 27 01:14:56 PM PDT 23
Peak memory 205852 kb
Host smart-cab2e8f6-c89b-426a-b34f-c4ec299546d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887592743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3887592743
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3058844881
Short name T333
Test name
Test status
Simulation time 11829657 ps
CPU time 0.81 seconds
Started Sep 27 01:14:34 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 205756 kb
Host smart-1c2c359e-2b41-4653-99ff-34534ca17d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058844881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3058844881
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4126606901
Short name T390
Test name
Test status
Simulation time 15595367 ps
CPU time 0.85 seconds
Started Sep 27 01:14:59 PM PDT 23
Finished Sep 27 01:15:00 PM PDT 23
Peak memory 205768 kb
Host smart-76ffce65-3979-4575-8138-97b2b4540556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126606901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4126606901
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1500762246
Short name T365
Test name
Test status
Simulation time 34702410 ps
CPU time 0.81 seconds
Started Sep 27 01:14:42 PM PDT 23
Finished Sep 27 01:14:43 PM PDT 23
Peak memory 205772 kb
Host smart-90db78c4-c0c1-4573-b5a7-9ff702d64772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500762246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1500762246
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1728593564
Short name T213
Test name
Test status
Simulation time 32245398 ps
CPU time 0.8 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 205616 kb
Host smart-75da749d-5df1-4600-81a4-3517cd4bad70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728593564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1728593564
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1988411024
Short name T338
Test name
Test status
Simulation time 26314934 ps
CPU time 0.73 seconds
Started Sep 27 01:15:16 PM PDT 23
Finished Sep 27 01:15:17 PM PDT 23
Peak memory 205624 kb
Host smart-3bbac63c-b8f0-4ab4-8182-94bcd8d84abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988411024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1988411024
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2933599656
Short name T217
Test name
Test status
Simulation time 33627265 ps
CPU time 1.35 seconds
Started Sep 27 01:16:51 PM PDT 23
Finished Sep 27 01:16:53 PM PDT 23
Peak memory 205896 kb
Host smart-45d1649f-4621-4211-a556-4df7b3fb27eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933599656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2933599656
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2781564355
Short name T336
Test name
Test status
Simulation time 406791717 ps
CPU time 2.87 seconds
Started Sep 27 01:16:43 PM PDT 23
Finished Sep 27 01:16:46 PM PDT 23
Peak memory 205876 kb
Host smart-8f191f26-0a22-4459-b2a6-a6c21b0d51ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781564355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2781564355
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.487574420
Short name T379
Test name
Test status
Simulation time 70180675 ps
CPU time 0.88 seconds
Started Sep 27 01:15:23 PM PDT 23
Finished Sep 27 01:15:24 PM PDT 23
Peak memory 205864 kb
Host smart-67b39b33-6ad3-4755-97c3-f50f508a72c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487574420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.487574420
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.415343630
Short name T420
Test name
Test status
Simulation time 106612368 ps
CPU time 1.9 seconds
Started Sep 27 01:15:51 PM PDT 23
Finished Sep 27 01:15:53 PM PDT 23
Peak memory 214036 kb
Host smart-9fa30757-40a1-46d8-8d11-1482cc3bfcad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415343630 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.415343630
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1888362726
Short name T335
Test name
Test status
Simulation time 20273912 ps
CPU time 0.79 seconds
Started Sep 27 01:15:39 PM PDT 23
Finished Sep 27 01:15:40 PM PDT 23
Peak memory 205680 kb
Host smart-7eb71a0a-626a-4bc6-8b50-0e522c34048e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888362726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1888362726
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4196000645
Short name T328
Test name
Test status
Simulation time 11553702 ps
CPU time 0.77 seconds
Started Sep 27 01:15:54 PM PDT 23
Finished Sep 27 01:16:00 PM PDT 23
Peak memory 205792 kb
Host smart-e3ccf044-a6f3-422c-a450-b45961f0a02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196000645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4196000645
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2187678951
Short name T226
Test name
Test status
Simulation time 35648880 ps
CPU time 0.9 seconds
Started Sep 27 01:16:42 PM PDT 23
Finished Sep 27 01:16:43 PM PDT 23
Peak memory 205796 kb
Host smart-e885500a-0a7f-494f-a403-f0a5780bc549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187678951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2187678951
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.195064302
Short name T367
Test name
Test status
Simulation time 46254182 ps
CPU time 2.13 seconds
Started Sep 27 01:15:38 PM PDT 23
Finished Sep 27 01:15:40 PM PDT 23
Peak memory 214192 kb
Host smart-58ec694d-0e64-4db2-9bb6-0f433832fd91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195064302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.195064302
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.460496524
Short name T277
Test name
Test status
Simulation time 207026700 ps
CPU time 2.38 seconds
Started Sep 27 01:16:09 PM PDT 23
Finished Sep 27 01:16:11 PM PDT 23
Peak memory 205836 kb
Host smart-8912ce9c-59f7-4dad-b50e-d293dac53e89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460496524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.460496524
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1487933925
Short name T421
Test name
Test status
Simulation time 17065618 ps
CPU time 0.91 seconds
Started Sep 27 01:15:15 PM PDT 23
Finished Sep 27 01:15:17 PM PDT 23
Peak memory 205696 kb
Host smart-548f6771-f677-4587-9d29-37d3616edf3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487933925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1487933925
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.764355893
Short name T418
Test name
Test status
Simulation time 11675938 ps
CPU time 0.82 seconds
Started Sep 27 01:14:32 PM PDT 23
Finished Sep 27 01:14:33 PM PDT 23
Peak memory 205800 kb
Host smart-14785b7e-dd69-4056-908a-c8ab69117443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764355893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.764355893
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2682681599
Short name T337
Test name
Test status
Simulation time 20475904 ps
CPU time 0.96 seconds
Started Sep 27 01:14:25 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 205764 kb
Host smart-387332f9-de78-46ab-afa0-4aa93ef85bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682681599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2682681599
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.575513558
Short name T387
Test name
Test status
Simulation time 33484616 ps
CPU time 0.82 seconds
Started Sep 27 01:14:53 PM PDT 23
Finished Sep 27 01:14:54 PM PDT 23
Peak memory 205792 kb
Host smart-ba254f2b-6bc6-4b16-8ca6-1717e814b7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575513558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.575513558
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3181711039
Short name T330
Test name
Test status
Simulation time 13128735 ps
CPU time 0.84 seconds
Started Sep 27 01:15:01 PM PDT 23
Finished Sep 27 01:15:02 PM PDT 23
Peak memory 205740 kb
Host smart-b8646471-9b7e-479a-8ffd-304db3d99506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181711039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3181711039
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1904148339
Short name T369
Test name
Test status
Simulation time 27056902 ps
CPU time 0.88 seconds
Started Sep 27 01:14:30 PM PDT 23
Finished Sep 27 01:14:31 PM PDT 23
Peak memory 205652 kb
Host smart-e1f08eab-eb10-43c7-97ee-f987f11a1f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904148339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1904148339
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4105362462
Short name T334
Test name
Test status
Simulation time 11398767 ps
CPU time 0.82 seconds
Started Sep 27 01:14:25 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 205340 kb
Host smart-10d13da6-02ce-42fc-a566-206db45e7eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105362462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4105362462
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.157501496
Short name T325
Test name
Test status
Simulation time 19008438 ps
CPU time 0.85 seconds
Started Sep 27 01:15:20 PM PDT 23
Finished Sep 27 01:15:21 PM PDT 23
Peak memory 205772 kb
Host smart-f51dd3e0-5e10-4a74-ab11-18b43701e50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157501496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.157501496
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1448136295
Short name T417
Test name
Test status
Simulation time 14736189 ps
CPU time 0.85 seconds
Started Sep 27 01:15:10 PM PDT 23
Finished Sep 27 01:15:12 PM PDT 23
Peak memory 205892 kb
Host smart-289982af-e136-4194-96c1-fa54c674d30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448136295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1448136295
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2039674429
Short name T341
Test name
Test status
Simulation time 37479529 ps
CPU time 0.75 seconds
Started Sep 27 01:14:33 PM PDT 23
Finished Sep 27 01:14:34 PM PDT 23
Peak memory 205612 kb
Host smart-5cf67e6c-7329-46c4-b4c0-d31fd322b6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039674429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2039674429
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2629158193
Short name T389
Test name
Test status
Simulation time 16267867 ps
CPU time 0.98 seconds
Started Sep 27 01:15:01 PM PDT 23
Finished Sep 27 01:15:02 PM PDT 23
Peak memory 205912 kb
Host smart-bdcb70a1-d74a-4676-a15d-9f123636e64e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629158193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2629158193
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.855794228
Short name T363
Test name
Test status
Simulation time 110813188 ps
CPU time 3.19 seconds
Started Sep 27 01:14:34 PM PDT 23
Finished Sep 27 01:14:37 PM PDT 23
Peak memory 205860 kb
Host smart-5aeda036-2ec1-4ffd-97ad-794b08bb76d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855794228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.855794228
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3251901628
Short name T215
Test name
Test status
Simulation time 110076198 ps
CPU time 0.8 seconds
Started Sep 27 01:15:46 PM PDT 23
Finished Sep 27 01:15:47 PM PDT 23
Peak memory 205612 kb
Host smart-a73c265e-a484-4b56-a200-56399b1366a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251901628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3251901628
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1870530425
Short name T400
Test name
Test status
Simulation time 44324017 ps
CPU time 1.12 seconds
Started Sep 27 01:16:17 PM PDT 23
Finished Sep 27 01:16:18 PM PDT 23
Peak memory 214100 kb
Host smart-4338932b-2f52-4515-81d7-95b2b527716a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870530425 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1870530425
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1623934671
Short name T207
Test name
Test status
Simulation time 44899947 ps
CPU time 0.77 seconds
Started Sep 27 01:15:23 PM PDT 23
Finished Sep 27 01:15:24 PM PDT 23
Peak memory 205508 kb
Host smart-da23b126-7770-4192-be03-7c52d1e24dbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623934671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1623934671
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3069932052
Short name T228
Test name
Test status
Simulation time 46494458 ps
CPU time 0.84 seconds
Started Sep 27 01:15:58 PM PDT 23
Finished Sep 27 01:15:59 PM PDT 23
Peak memory 205792 kb
Host smart-2f177ad6-6d78-4aa2-97e9-aa5d1bb95d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069932052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3069932052
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4071275863
Short name T351
Test name
Test status
Simulation time 170047410 ps
CPU time 0.9 seconds
Started Sep 27 01:16:18 PM PDT 23
Finished Sep 27 01:16:20 PM PDT 23
Peak memory 205676 kb
Host smart-4d11e508-8da4-4de7-9ea3-0867235ba526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071275863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4071275863
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3746662893
Short name T183
Test name
Test status
Simulation time 530482088 ps
CPU time 2.16 seconds
Started Sep 27 01:15:51 PM PDT 23
Finished Sep 27 01:15:53 PM PDT 23
Peak memory 214056 kb
Host smart-c0ae289b-e85e-4f7c-a35e-f8710ee3d879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746662893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3746662893
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1421303106
Short name T229
Test name
Test status
Simulation time 160958551 ps
CPU time 2.23 seconds
Started Sep 27 01:15:27 PM PDT 23
Finished Sep 27 01:15:30 PM PDT 23
Peak memory 205848 kb
Host smart-795d8be2-a881-4115-8f0c-ad5f83211e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421303106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1421303106
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2186480990
Short name T412
Test name
Test status
Simulation time 20518283 ps
CPU time 0.82 seconds
Started Sep 27 01:15:07 PM PDT 23
Finished Sep 27 01:15:08 PM PDT 23
Peak memory 205808 kb
Host smart-14653a72-2d8c-4e2f-9da8-c6e71d9cd750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186480990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2186480990
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1201719951
Short name T344
Test name
Test status
Simulation time 79771068 ps
CPU time 0.79 seconds
Started Sep 27 01:15:24 PM PDT 23
Finished Sep 27 01:15:25 PM PDT 23
Peak memory 205620 kb
Host smart-b1b12aa5-4bee-4137-a948-87025ac4b62f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201719951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1201719951
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3834672786
Short name T402
Test name
Test status
Simulation time 68665635 ps
CPU time 0.74 seconds
Started Sep 27 01:14:53 PM PDT 23
Finished Sep 27 01:14:54 PM PDT 23
Peak memory 205592 kb
Host smart-41c504f4-75cc-4a74-8ce4-c18df4e9169e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834672786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3834672786
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1843958554
Short name T404
Test name
Test status
Simulation time 48580600 ps
CPU time 0.83 seconds
Started Sep 27 01:15:14 PM PDT 23
Finished Sep 27 01:15:16 PM PDT 23
Peak memory 205664 kb
Host smart-94ccb9f5-8643-47c8-be98-fcb2328d79ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843958554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1843958554
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.496326884
Short name T343
Test name
Test status
Simulation time 35889380 ps
CPU time 0.78 seconds
Started Sep 27 01:14:27 PM PDT 23
Finished Sep 27 01:14:28 PM PDT 23
Peak memory 205596 kb
Host smart-aac28700-9102-47a8-80ec-c7935cd8962e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496326884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.496326884
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2011103828
Short name T349
Test name
Test status
Simulation time 26756268 ps
CPU time 0.8 seconds
Started Sep 27 01:14:20 PM PDT 23
Finished Sep 27 01:14:21 PM PDT 23
Peak memory 205544 kb
Host smart-a2bc6338-3f29-4ac9-a41e-88c4948be6a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011103828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2011103828
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2612613018
Short name T385
Test name
Test status
Simulation time 53772730 ps
CPU time 0.86 seconds
Started Sep 27 01:15:08 PM PDT 23
Finished Sep 27 01:15:09 PM PDT 23
Peak memory 205664 kb
Host smart-9ff5116e-7d2c-4715-bee5-224335ef0fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612613018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2612613018
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3724510196
Short name T236
Test name
Test status
Simulation time 40854538 ps
CPU time 0.77 seconds
Started Sep 27 01:14:24 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 205644 kb
Host smart-5e489c35-6702-4ba2-ada4-d0137290ce51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724510196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3724510196
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2391438063
Short name T353
Test name
Test status
Simulation time 15942281 ps
CPU time 0.85 seconds
Started Sep 27 01:14:57 PM PDT 23
Finished Sep 27 01:14:58 PM PDT 23
Peak memory 205712 kb
Host smart-0fd3925d-3bc0-44bc-b0ec-8f7fb7c540d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391438063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2391438063
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4280389231
Short name T346
Test name
Test status
Simulation time 13954112 ps
CPU time 0.85 seconds
Started Sep 27 01:14:25 PM PDT 23
Finished Sep 27 01:14:26 PM PDT 23
Peak memory 205272 kb
Host smart-f2351a53-f78b-4644-a43e-886af47189a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280389231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4280389231
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3717786659
Short name T227
Test name
Test status
Simulation time 62930941 ps
CPU time 0.98 seconds
Started Sep 27 01:16:35 PM PDT 23
Finished Sep 27 01:16:37 PM PDT 23
Peak memory 213992 kb
Host smart-604907c9-e8cf-412d-8f8c-3e0f504d7520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717786659 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3717786659
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.842013125
Short name T355
Test name
Test status
Simulation time 13511780 ps
CPU time 0.87 seconds
Started Sep 27 01:16:29 PM PDT 23
Finished Sep 27 01:16:31 PM PDT 23
Peak memory 205788 kb
Host smart-25a3d10b-c9d5-4ec6-8c41-7cacd4747259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842013125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.842013125
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2166557870
Short name T324
Test name
Test status
Simulation time 19911617 ps
CPU time 0.77 seconds
Started Sep 27 01:16:51 PM PDT 23
Finished Sep 27 01:16:51 PM PDT 23
Peak memory 205540 kb
Host smart-106ae6a1-8609-4776-8ec1-cb8cd199f2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166557870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2166557870
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3558411802
Short name T232
Test name
Test status
Simulation time 57801997 ps
CPU time 1.04 seconds
Started Sep 27 01:16:56 PM PDT 23
Finished Sep 27 01:16:58 PM PDT 23
Peak memory 205892 kb
Host smart-ea82f66b-4439-46f8-a87c-560e395ef2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558411802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3558411802
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1601618259
Short name T194
Test name
Test status
Simulation time 149475475 ps
CPU time 2.28 seconds
Started Sep 27 01:16:07 PM PDT 23
Finished Sep 27 01:16:09 PM PDT 23
Peak memory 214128 kb
Host smart-c950078a-3c0f-4f0e-ba12-1d9b0b9b3463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601618259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1601618259
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2284927788
Short name T130
Test name
Test status
Simulation time 50428721 ps
CPU time 1.63 seconds
Started Sep 27 01:16:29 PM PDT 23
Finished Sep 27 01:16:31 PM PDT 23
Peak memory 205796 kb
Host smart-b1d7beaf-2723-4be6-971c-305fbf6acda5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284927788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2284927788
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3187299866
Short name T196
Test name
Test status
Simulation time 78523547 ps
CPU time 1.13 seconds
Started Sep 27 01:14:20 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 214184 kb
Host smart-62bde785-8c09-4ebf-b23a-9e497b280a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187299866 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3187299866
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3174822023
Short name T403
Test name
Test status
Simulation time 13591761 ps
CPU time 0.88 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:22 PM PDT 23
Peak memory 205748 kb
Host smart-d5a92414-97f6-479e-bec8-e790497e87b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174822023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3174822023
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.77298954
Short name T401
Test name
Test status
Simulation time 181408644 ps
CPU time 0.84 seconds
Started Sep 27 01:14:54 PM PDT 23
Finished Sep 27 01:14:55 PM PDT 23
Peak memory 205776 kb
Host smart-1f36ff8d-0f9d-460c-b748-bcc7a33b9c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77298954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.77298954
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1066575816
Short name T405
Test name
Test status
Simulation time 34080808 ps
CPU time 1.31 seconds
Started Sep 27 01:14:13 PM PDT 23
Finished Sep 27 01:14:15 PM PDT 23
Peak memory 205844 kb
Host smart-2e5f01e7-c7bf-4bde-92a9-6f18be58c444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066575816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1066575816
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1003502808
Short name T368
Test name
Test status
Simulation time 76271225 ps
CPU time 2.57 seconds
Started Sep 27 01:16:42 PM PDT 23
Finished Sep 27 01:16:45 PM PDT 23
Peak memory 214116 kb
Host smart-e014323f-17d6-48bf-a2f2-2b0125b54b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003502808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1003502808
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.956330769
Short name T208
Test name
Test status
Simulation time 70720661 ps
CPU time 1.49 seconds
Started Sep 27 01:14:20 PM PDT 23
Finished Sep 27 01:14:21 PM PDT 23
Peak memory 205788 kb
Host smart-b0a986c1-4016-4911-adf9-e0cd97dae2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956330769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.956330769
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.263192305
Short name T360
Test name
Test status
Simulation time 41609215 ps
CPU time 1.2 seconds
Started Sep 27 01:15:24 PM PDT 23
Finished Sep 27 01:15:25 PM PDT 23
Peak memory 214152 kb
Host smart-462b30b6-838b-40e9-a428-82080f653ab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263192305 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.263192305
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1952480139
Short name T225
Test name
Test status
Simulation time 52919255 ps
CPU time 0.81 seconds
Started Sep 27 01:14:19 PM PDT 23
Finished Sep 27 01:14:20 PM PDT 23
Peak memory 205800 kb
Host smart-f636e43d-1351-401d-ade0-09bfde7c0cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952480139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1952480139
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2056229661
Short name T347
Test name
Test status
Simulation time 29408273 ps
CPU time 0.77 seconds
Started Sep 27 01:14:35 PM PDT 23
Finished Sep 27 01:14:36 PM PDT 23
Peak memory 205616 kb
Host smart-7437bf73-32a8-4702-a207-34cf32899d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056229661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2056229661
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3486178959
Short name T428
Test name
Test status
Simulation time 52611985 ps
CPU time 1.21 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 205840 kb
Host smart-fa7576fc-bf10-4c50-9f0e-d2f57b7773ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486178959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3486178959
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2855463772
Short name T233
Test name
Test status
Simulation time 100596625 ps
CPU time 1.59 seconds
Started Sep 27 01:14:28 PM PDT 23
Finished Sep 27 01:14:30 PM PDT 23
Peak memory 214176 kb
Host smart-777c68e6-e8d7-4b1c-b7b1-990c2386fe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855463772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2855463772
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1604268900
Short name T276
Test name
Test status
Simulation time 353738476 ps
CPU time 2.76 seconds
Started Sep 27 01:14:26 PM PDT 23
Finished Sep 27 01:14:29 PM PDT 23
Peak memory 205800 kb
Host smart-2a7dc6e6-d30e-4d20-9129-2f2415c16aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604268900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1604268900
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1655589226
Short name T210
Test name
Test status
Simulation time 15957221 ps
CPU time 1.14 seconds
Started Sep 27 01:14:29 PM PDT 23
Finished Sep 27 01:14:31 PM PDT 23
Peak memory 214184 kb
Host smart-f2051ef7-9867-4c16-b388-09ceda909f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655589226 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1655589226
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1907178056
Short name T218
Test name
Test status
Simulation time 15141232 ps
CPU time 1 seconds
Started Sep 27 01:14:27 PM PDT 23
Finished Sep 27 01:14:29 PM PDT 23
Peak memory 205820 kb
Host smart-51ae7614-2eb9-42ea-a75d-b159a8c75b44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907178056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1907178056
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4112705680
Short name T345
Test name
Test status
Simulation time 13339861 ps
CPU time 0.85 seconds
Started Sep 27 01:14:29 PM PDT 23
Finished Sep 27 01:14:30 PM PDT 23
Peak memory 205684 kb
Host smart-4c31b740-2a18-460a-b9b7-a0f88a097abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112705680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4112705680
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4136885673
Short name T396
Test name
Test status
Simulation time 133863383 ps
CPU time 1.14 seconds
Started Sep 27 01:14:30 PM PDT 23
Finished Sep 27 01:14:32 PM PDT 23
Peak memory 205936 kb
Host smart-1d4e2a69-f674-42fe-8708-1aca830e8a79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136885673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4136885673
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3295301942
Short name T426
Test name
Test status
Simulation time 142773664 ps
CPU time 2.37 seconds
Started Sep 27 01:14:27 PM PDT 23
Finished Sep 27 01:14:30 PM PDT 23
Peak memory 214200 kb
Host smart-78ca1133-cbc6-4322-9fa0-e08230f647a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295301942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3295301942
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.182159315
Short name T186
Test name
Test status
Simulation time 50569290 ps
CPU time 1.65 seconds
Started Sep 27 01:14:21 PM PDT 23
Finished Sep 27 01:14:23 PM PDT 23
Peak memory 205772 kb
Host smart-cb3a69fa-c4ef-4ecf-8ecb-95189d6638b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182159315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.182159315
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3322098879
Short name T356
Test name
Test status
Simulation time 18849454 ps
CPU time 1.39 seconds
Started Sep 27 01:14:40 PM PDT 23
Finished Sep 27 01:14:42 PM PDT 23
Peak memory 214208 kb
Host smart-0c0d58b0-f6a8-45f7-a492-877c314e4242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322098879 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3322098879
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2884283814
Short name T411
Test name
Test status
Simulation time 19043748 ps
CPU time 0.81 seconds
Started Sep 27 01:14:19 PM PDT 23
Finished Sep 27 01:14:20 PM PDT 23
Peak memory 205632 kb
Host smart-6d87b6f2-5fd0-4277-9479-29bcaaae1a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884283814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2884283814
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4158264356
Short name T329
Test name
Test status
Simulation time 25555823 ps
CPU time 0.83 seconds
Started Sep 27 01:14:10 PM PDT 23
Finished Sep 27 01:14:11 PM PDT 23
Peak memory 205732 kb
Host smart-d4e2c6bd-588b-46e1-a1df-8a8f99af1cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158264356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4158264356
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2901790195
Short name T377
Test name
Test status
Simulation time 22769560 ps
CPU time 1.13 seconds
Started Sep 27 01:14:46 PM PDT 23
Finished Sep 27 01:14:47 PM PDT 23
Peak memory 205856 kb
Host smart-8a44cb28-132b-4f3b-8459-4a912ebeff60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901790195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2901790195
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.203914305
Short name T361
Test name
Test status
Simulation time 679629133 ps
CPU time 4.05 seconds
Started Sep 27 01:14:23 PM PDT 23
Finished Sep 27 01:14:27 PM PDT 23
Peak memory 214200 kb
Host smart-0296381e-0091-4213-a1b2-87135d4831d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203914305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.203914305
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.225081537
Short name T364
Test name
Test status
Simulation time 310250712 ps
CPU time 1.45 seconds
Started Sep 27 01:14:43 PM PDT 23
Finished Sep 27 01:14:45 PM PDT 23
Peak memory 205844 kb
Host smart-cd1517da-eb0a-402e-a739-679ac94ec212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225081537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.225081537
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3339522774
Short name T662
Test name
Test status
Simulation time 60959569 ps
CPU time 0.92 seconds
Started Sep 27 01:03:13 PM PDT 23
Finished Sep 27 01:03:15 PM PDT 23
Peak memory 206344 kb
Host smart-3a5b5907-2329-4617-acf2-c1e305194492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339522774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3339522774
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2386453931
Short name T524
Test name
Test status
Simulation time 15218763 ps
CPU time 0.96 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:09 PM PDT 23
Peak memory 205220 kb
Host smart-4e278457-2133-43eb-bdd1-3b891faa1407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386453931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2386453931
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.2424702278
Short name T652
Test name
Test status
Simulation time 43185864 ps
CPU time 0.9 seconds
Started Sep 27 01:02:58 PM PDT 23
Finished Sep 27 01:02:59 PM PDT 23
Peak memory 215992 kb
Host smart-7979640a-6c65-43e4-98ab-1ea7e6e8e913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424702278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2424702278
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1776747176
Short name T591
Test name
Test status
Simulation time 26124047 ps
CPU time 0.86 seconds
Started Sep 27 01:03:13 PM PDT 23
Finished Sep 27 01:03:15 PM PDT 23
Peak memory 214880 kb
Host smart-7c06f94e-9d93-48ca-a570-6ed950706159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776747176 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1776747176
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1259784901
Short name T53
Test name
Test status
Simulation time 468371538 ps
CPU time 3.86 seconds
Started Sep 27 01:00:15 PM PDT 23
Finished Sep 27 01:00:19 PM PDT 23
Peak memory 234672 kb
Host smart-67e40545-25f3-4041-aa63-e59ac54c263a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259784901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1259784901
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1072825687
Short name T621
Test name
Test status
Simulation time 43066705 ps
CPU time 0.87 seconds
Started Sep 27 01:00:12 PM PDT 23
Finished Sep 27 01:00:13 PM PDT 23
Peak memory 205052 kb
Host smart-bb01be56-8b6b-415e-b94e-389436d08d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072825687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1072825687
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2193746025
Short name T504
Test name
Test status
Simulation time 41410034 ps
CPU time 1.36 seconds
Started Sep 27 01:01:08 PM PDT 23
Finished Sep 27 01:01:09 PM PDT 23
Peak memory 206432 kb
Host smart-3cc08303-5972-4539-80ef-ac275fa9aeb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193746025 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2193746025
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1040748210
Short name T638
Test name
Test status
Simulation time 63602123933 ps
CPU time 1362.62 seconds
Started Sep 27 01:02:29 PM PDT 23
Finished Sep 27 01:25:12 PM PDT 23
Peak memory 217368 kb
Host smart-a5a27f44-103a-4659-90b5-73d91d27f7c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040748210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1040748210
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2647977248
Short name T81
Test name
Test status
Simulation time 149800744 ps
CPU time 1.01 seconds
Started Sep 27 01:01:01 PM PDT 23
Finished Sep 27 01:01:03 PM PDT 23
Peak memory 206532 kb
Host smart-e3e2ca57-273b-4b01-b649-3f5f024c87a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647977248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2647977248
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1272593064
Short name T529
Test name
Test status
Simulation time 27664773 ps
CPU time 0.89 seconds
Started Sep 27 01:01:04 PM PDT 23
Finished Sep 27 01:01:05 PM PDT 23
Peak memory 204892 kb
Host smart-4708707c-79d5-484c-8f14-3809e493972e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272593064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1272593064
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4077294827
Short name T79
Test name
Test status
Simulation time 41786787 ps
CPU time 0.82 seconds
Started Sep 27 01:07:49 PM PDT 23
Finished Sep 27 01:07:49 PM PDT 23
Peak memory 214908 kb
Host smart-88f6447a-2a4d-43ce-b33a-e2dfeb98d4ca
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077294827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4077294827
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.806891344
Short name T152
Test name
Test status
Simulation time 18356925 ps
CPU time 1.11 seconds
Started Sep 27 01:13:00 PM PDT 23
Finished Sep 27 01:13:02 PM PDT 23
Peak memory 222380 kb
Host smart-fdf4fe02-df9b-447c-a670-7d5804cc7d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806891344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.806891344
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1858406547
Short name T639
Test name
Test status
Simulation time 30879167 ps
CPU time 0.99 seconds
Started Sep 27 01:01:14 PM PDT 23
Finished Sep 27 01:01:15 PM PDT 23
Peak memory 205644 kb
Host smart-847da793-4efd-4b34-8470-3bd14ebf522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858406547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1858406547
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2426557176
Short name T119
Test name
Test status
Simulation time 19714614 ps
CPU time 1.01 seconds
Started Sep 27 01:00:25 PM PDT 23
Finished Sep 27 01:00:26 PM PDT 23
Peak memory 215124 kb
Host smart-740c3a49-3e9e-4be5-a06c-bfa268ec2a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426557176 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2426557176
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3218374658
Short name T299
Test name
Test status
Simulation time 15497912 ps
CPU time 0.92 seconds
Started Sep 27 01:08:24 PM PDT 23
Finished Sep 27 01:08:25 PM PDT 23
Peak memory 205256 kb
Host smart-ca0585fc-c1be-4df6-accf-eb1adfd5f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218374658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3218374658
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.3731397242
Short name T19
Test name
Test status
Simulation time 53229682 ps
CPU time 0.84 seconds
Started Sep 27 01:07:20 PM PDT 23
Finished Sep 27 01:07:21 PM PDT 23
Peak memory 205172 kb
Host smart-df4735f8-2f7c-48a3-9482-885327b4ac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731397242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3731397242
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1339781801
Short name T262
Test name
Test status
Simulation time 169115832 ps
CPU time 1.34 seconds
Started Sep 27 01:00:30 PM PDT 23
Finished Sep 27 01:00:31 PM PDT 23
Peak memory 205800 kb
Host smart-4ba52a08-4fff-4b7e-8889-6c87ed148519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339781801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1339781801
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3730427475
Short name T127
Test name
Test status
Simulation time 55916346940 ps
CPU time 1266.88 seconds
Started Sep 27 01:02:16 PM PDT 23
Finished Sep 27 01:23:23 PM PDT 23
Peak memory 215972 kb
Host smart-eb939cf6-0d0e-4062-be27-82569ef7feee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730427475 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3730427475
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1264145627
Short name T551
Test name
Test status
Simulation time 22279686 ps
CPU time 0.97 seconds
Started Sep 27 01:09:38 PM PDT 23
Finished Sep 27 01:09:39 PM PDT 23
Peak memory 205576 kb
Host smart-397696a5-0b05-4146-ae85-ea995abd19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264145627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1264145627
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2352253270
Short name T623
Test name
Test status
Simulation time 28976158 ps
CPU time 0.92 seconds
Started Sep 27 01:14:51 PM PDT 23
Finished Sep 27 01:14:52 PM PDT 23
Peak memory 205024 kb
Host smart-a9d1b54e-cd43-4f55-89a7-b46c7254d34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352253270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2352253270
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3951814868
Short name T569
Test name
Test status
Simulation time 10097240 ps
CPU time 0.83 seconds
Started Sep 27 01:10:05 PM PDT 23
Finished Sep 27 01:10:06 PM PDT 23
Peak memory 214864 kb
Host smart-50617953-64df-4fa6-add8-4d5525b79d07
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951814868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3951814868
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1513128255
Short name T96
Test name
Test status
Simulation time 55533391 ps
CPU time 0.93 seconds
Started Sep 27 01:14:02 PM PDT 23
Finished Sep 27 01:14:03 PM PDT 23
Peak memory 215096 kb
Host smart-2f2d39f4-0e77-4f4b-9444-82e73504a6ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513128255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1513128255
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1281527238
Short name T147
Test name
Test status
Simulation time 32214768 ps
CPU time 0.93 seconds
Started Sep 27 01:06:02 PM PDT 23
Finished Sep 27 01:06:03 PM PDT 23
Peak memory 221700 kb
Host smart-7c17621a-ce86-4b08-9e9d-1fa496d1b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281527238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1281527238
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2544579865
Short name T632
Test name
Test status
Simulation time 24173200 ps
CPU time 0.96 seconds
Started Sep 27 01:13:12 PM PDT 23
Finished Sep 27 01:13:13 PM PDT 23
Peak memory 206032 kb
Host smart-9b7857bb-635e-4af2-b83f-04364a591565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544579865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2544579865
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3831314222
Short name T577
Test name
Test status
Simulation time 66859110 ps
CPU time 0.93 seconds
Started Sep 27 01:20:12 PM PDT 23
Finished Sep 27 01:20:13 PM PDT 23
Peak memory 221056 kb
Host smart-14232671-ef81-42e7-86e3-a9c5ccf99b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831314222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3831314222
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3432343029
Short name T552
Test name
Test status
Simulation time 11172097 ps
CPU time 0.88 seconds
Started Sep 27 01:00:26 PM PDT 23
Finished Sep 27 01:00:27 PM PDT 23
Peak memory 205172 kb
Host smart-634b58d0-c106-4bc8-92fc-b81b3c847b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432343029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3432343029
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.812268978
Short name T261
Test name
Test status
Simulation time 487706589 ps
CPU time 2.86 seconds
Started Sep 27 01:01:50 PM PDT 23
Finished Sep 27 01:01:53 PM PDT 23
Peak memory 206320 kb
Host smart-662747f8-ef5c-4404-8a08-9c4e602c71f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812268978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.812268978
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2703937296
Short name T27
Test name
Test status
Simulation time 927944694443 ps
CPU time 2690.09 seconds
Started Sep 27 01:16:06 PM PDT 23
Finished Sep 27 02:00:59 PM PDT 23
Peak memory 223468 kb
Host smart-e69abdad-a258-4089-9223-4cfbad0b0e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703937296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2703937296
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert_test.4264250229
Short name T533
Test name
Test status
Simulation time 19494594 ps
CPU time 0.91 seconds
Started Sep 27 01:02:36 PM PDT 23
Finished Sep 27 01:02:37 PM PDT 23
Peak memory 204976 kb
Host smart-360f4b25-ca0c-4946-a3ed-f4a297191900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264250229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4264250229
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.4084406847
Short name T172
Test name
Test status
Simulation time 11596033 ps
CPU time 0.86 seconds
Started Sep 27 01:02:06 PM PDT 23
Finished Sep 27 01:02:07 PM PDT 23
Peak memory 214816 kb
Host smart-ed0ad3b4-8dd6-4222-871c-ed2714fb793c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084406847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4084406847
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3946872921
Short name T250
Test name
Test status
Simulation time 23953884 ps
CPU time 0.93 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 214928 kb
Host smart-f709d33b-aa8a-423c-8e79-7b9ce5812717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946872921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3946872921
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.8210439
Short name T566
Test name
Test status
Simulation time 23125726 ps
CPU time 0.93 seconds
Started Sep 27 01:00:32 PM PDT 23
Finished Sep 27 01:00:33 PM PDT 23
Peak memory 205204 kb
Host smart-78a7ea2a-8c18-4723-b971-f6cf1ebbb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8210439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.8210439
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1150480160
Short name T680
Test name
Test status
Simulation time 25683733 ps
CPU time 0.91 seconds
Started Sep 27 01:01:57 PM PDT 23
Finished Sep 27 01:01:58 PM PDT 23
Peak memory 214832 kb
Host smart-7af5d194-f979-49c7-b03a-769f6addc3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150480160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1150480160
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1914767411
Short name T666
Test name
Test status
Simulation time 15155280 ps
CPU time 0.89 seconds
Started Sep 27 01:07:37 PM PDT 23
Finished Sep 27 01:07:38 PM PDT 23
Peak memory 205088 kb
Host smart-b6cb4916-c550-4d89-a2a6-7fd190c51dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914767411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1914767411
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3541009219
Short name T532
Test name
Test status
Simulation time 272355684 ps
CPU time 1.89 seconds
Started Sep 27 01:01:59 PM PDT 23
Finished Sep 27 01:02:03 PM PDT 23
Peak memory 206480 kb
Host smart-0e7adb82-d812-4056-9cbd-1b228a77edda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541009219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3541009219
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3930507247
Short name T264
Test name
Test status
Simulation time 121179449833 ps
CPU time 1514.49 seconds
Started Sep 27 01:01:05 PM PDT 23
Finished Sep 27 01:26:19 PM PDT 23
Peak memory 221100 kb
Host smart-51a3a29b-c242-41f7-9aed-42a97bd2e40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930507247 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3930507247
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.3216190747
Short name T471
Test name
Test status
Simulation time 60117000 ps
CPU time 0.95 seconds
Started Sep 27 01:01:08 PM PDT 23
Finished Sep 27 01:01:10 PM PDT 23
Peak memory 205616 kb
Host smart-611f42a5-f910-4388-a44e-2d555de5cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216190747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3216190747
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3692875684
Short name T467
Test name
Test status
Simulation time 14142546 ps
CPU time 0.87 seconds
Started Sep 27 01:02:22 PM PDT 23
Finished Sep 27 01:02:23 PM PDT 23
Peak memory 205604 kb
Host smart-14d1b5a5-27c3-4e89-a45c-f2e0e3672d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692875684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3692875684
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3674469192
Short name T42
Test name
Test status
Simulation time 25554473 ps
CPU time 0.97 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:08 PM PDT 23
Peak memory 215036 kb
Host smart-8451add9-f7ef-49ab-8c05-a7b43075dec8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674469192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3674469192
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.3662498355
Short name T95
Test name
Test status
Simulation time 56250204 ps
CPU time 0.99 seconds
Started Sep 27 01:04:07 PM PDT 23
Finished Sep 27 01:04:09 PM PDT 23
Peak memory 205424 kb
Host smart-40245cde-28c4-4c5a-8f2f-ebb007472c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662498355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3662498355
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2598515880
Short name T634
Test name
Test status
Simulation time 13089316 ps
CPU time 0.87 seconds
Started Sep 27 01:03:24 PM PDT 23
Finished Sep 27 01:03:25 PM PDT 23
Peak memory 205256 kb
Host smart-67f0a93b-fc6d-44aa-b18d-037345a7b513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598515880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2598515880
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.18743556
Short name T579
Test name
Test status
Simulation time 326530651 ps
CPU time 2.86 seconds
Started Sep 27 01:03:53 PM PDT 23
Finished Sep 27 01:03:56 PM PDT 23
Peak memory 206432 kb
Host smart-d1462e8e-ae13-471d-82c3-bf9682446fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18743556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.18743556
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_alert.280238264
Short name T588
Test name
Test status
Simulation time 90182054 ps
CPU time 0.89 seconds
Started Sep 27 01:01:32 PM PDT 23
Finished Sep 27 01:01:33 PM PDT 23
Peak memory 206368 kb
Host smart-d54d8879-af6c-4b1e-b39e-d960bbf79ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280238264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.280238264
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2241425101
Short name T469
Test name
Test status
Simulation time 56696821 ps
CPU time 0.9 seconds
Started Sep 27 01:03:04 PM PDT 23
Finished Sep 27 01:03:05 PM PDT 23
Peak memory 205620 kb
Host smart-04558c52-b167-484d-848a-8a954f49de24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241425101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2241425101
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.839423735
Short name T567
Test name
Test status
Simulation time 37143032 ps
CPU time 0.81 seconds
Started Sep 27 01:01:56 PM PDT 23
Finished Sep 27 01:01:57 PM PDT 23
Peak memory 215920 kb
Host smart-f3e18961-bc67-46e2-88ae-f60534389c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839423735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.839423735
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1362857376
Short name T317
Test name
Test status
Simulation time 13306811 ps
CPU time 0.93 seconds
Started Sep 27 01:01:05 PM PDT 23
Finished Sep 27 01:01:06 PM PDT 23
Peak memory 205400 kb
Host smart-c053959c-1480-4ff2-8607-acf7d8e14175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362857376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1362857376
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1799778719
Short name T166
Test name
Test status
Simulation time 35868962 ps
CPU time 0.87 seconds
Started Sep 27 01:00:32 PM PDT 23
Finished Sep 27 01:00:33 PM PDT 23
Peak memory 214712 kb
Host smart-94a55bff-b13e-457f-beb6-b2786eaa3fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799778719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1799778719
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1839033762
Short name T436
Test name
Test status
Simulation time 22972337 ps
CPU time 0.9 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 205060 kb
Host smart-1208cd23-b767-40a7-aa8f-7751e31082d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839033762 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1839033762
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.623908641
Short name T677
Test name
Test status
Simulation time 47314434 ps
CPU time 1.01 seconds
Started Sep 27 01:01:52 PM PDT 23
Finished Sep 27 01:01:54 PM PDT 23
Peak memory 205032 kb
Host smart-b380d86a-dad7-4e63-88ee-36fcff78175d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623908641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.623908641
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.725192052
Short name T615
Test name
Test status
Simulation time 39066015176 ps
CPU time 1012.57 seconds
Started Sep 27 01:02:53 PM PDT 23
Finished Sep 27 01:19:52 PM PDT 23
Peak memory 215296 kb
Host smart-1382e9c7-dcca-43e9-84e4-b0df6157c791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725192052 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.725192052
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert.1751277187
Short name T646
Test name
Test status
Simulation time 19836210 ps
CPU time 0.95 seconds
Started Sep 27 01:07:57 PM PDT 23
Finished Sep 27 01:07:59 PM PDT 23
Peak memory 206456 kb
Host smart-bedfb3d7-c680-468f-ac31-5aecaa24e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751277187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1751277187
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_err.626174475
Short name T148
Test name
Test status
Simulation time 30381640 ps
CPU time 0.82 seconds
Started Sep 27 01:05:01 PM PDT 23
Finished Sep 27 01:05:07 PM PDT 23
Peak memory 215940 kb
Host smart-ad2f38e2-871b-4250-936e-5430d4f43fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626174475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.626174475
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.2275358817
Short name T432
Test name
Test status
Simulation time 20558692 ps
CPU time 1.11 seconds
Started Sep 27 01:02:14 PM PDT 23
Finished Sep 27 01:02:15 PM PDT 23
Peak memory 221748 kb
Host smart-a9903bcc-9df7-4a67-8b4c-6e0bf3447cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275358817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2275358817
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.600210479
Short name T314
Test name
Test status
Simulation time 12399105 ps
CPU time 0.87 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 205448 kb
Host smart-8c7b9839-2f1a-4bc2-a6e2-bc271e2f7c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600210479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.600210479
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3897365090
Short name T495
Test name
Test status
Simulation time 209608477 ps
CPU time 2.71 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 206428 kb
Host smart-b8572602-2b56-48b1-af90-bc2823d26b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897365090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3897365090
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_alert.499702270
Short name T256
Test name
Test status
Simulation time 19724842 ps
CPU time 1.02 seconds
Started Sep 27 01:02:40 PM PDT 23
Finished Sep 27 01:02:41 PM PDT 23
Peak memory 205568 kb
Host smart-2d87ac1f-630c-4600-a45d-9693a8fe1125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499702270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.499702270
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3593909017
Short name T309
Test name
Test status
Simulation time 29186906 ps
CPU time 0.82 seconds
Started Sep 27 01:02:24 PM PDT 23
Finished Sep 27 01:02:25 PM PDT 23
Peak memory 204512 kb
Host smart-092fb005-27b1-461c-94ca-dd5a5e76a208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593909017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3593909017
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2184476553
Short name T28
Test name
Test status
Simulation time 21798308 ps
CPU time 0.84 seconds
Started Sep 27 01:02:10 PM PDT 23
Finished Sep 27 01:02:11 PM PDT 23
Peak memory 214800 kb
Host smart-d8244d44-9f59-42c2-af7e-5727a12707b2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184476553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2184476553
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3454529588
Short name T68
Test name
Test status
Simulation time 29030737 ps
CPU time 1.13 seconds
Started Sep 27 01:02:55 PM PDT 23
Finished Sep 27 01:02:57 PM PDT 23
Peak memory 215112 kb
Host smart-342ba8a6-e88e-4afb-b407-c26d1db2efb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454529588 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3454529588
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2137770092
Short name T44
Test name
Test status
Simulation time 28505349 ps
CPU time 1.3 seconds
Started Sep 27 01:03:38 PM PDT 23
Finished Sep 27 01:03:39 PM PDT 23
Peak memory 222380 kb
Host smart-6b64c950-7c4a-428a-b592-aeef7d241b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137770092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2137770092
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.444755156
Short name T287
Test name
Test status
Simulation time 31376873 ps
CPU time 0.91 seconds
Started Sep 27 01:03:24 PM PDT 23
Finished Sep 27 01:03:25 PM PDT 23
Peak memory 205444 kb
Host smart-d522c9fc-d591-4527-863d-fc3815baf5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444755156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.444755156
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.208989711
Short name T477
Test name
Test status
Simulation time 35397697 ps
CPU time 0.89 seconds
Started Sep 27 01:03:23 PM PDT 23
Finished Sep 27 01:03:24 PM PDT 23
Peak memory 214724 kb
Host smart-021ed942-e780-4b35-aa9a-27fccbd17974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208989711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.208989711
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1644754268
Short name T318
Test name
Test status
Simulation time 50158976 ps
CPU time 0.83 seconds
Started Sep 27 01:03:02 PM PDT 23
Finished Sep 27 01:03:03 PM PDT 23
Peak memory 204980 kb
Host smart-77570bb6-ed42-4b07-aa9b-698c2daf0ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644754268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1644754268
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.81170570
Short name T174
Test name
Test status
Simulation time 64078132 ps
CPU time 1.11 seconds
Started Sep 27 01:02:43 PM PDT 23
Finished Sep 27 01:02:44 PM PDT 23
Peak memory 205424 kb
Host smart-b880081e-5999-4862-8039-e0fa1d0c1dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81170570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.81170570
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2494273618
Short name T598
Test name
Test status
Simulation time 60603088895 ps
CPU time 593.28 seconds
Started Sep 27 01:00:36 PM PDT 23
Finished Sep 27 01:10:29 PM PDT 23
Peak memory 215068 kb
Host smart-c8b56f7a-c2e4-40f5-b85d-4027e7a29c12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494273618 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2494273618
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert_test.660688731
Short name T496
Test name
Test status
Simulation time 21944811 ps
CPU time 1 seconds
Started Sep 27 01:14:39 PM PDT 23
Finished Sep 27 01:14:40 PM PDT 23
Peak memory 205660 kb
Host smart-a30d0b62-9826-4bad-898a-892b08a625cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660688731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.660688731
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2668950411
Short name T103
Test name
Test status
Simulation time 10065336 ps
CPU time 0.82 seconds
Started Sep 27 01:00:48 PM PDT 23
Finished Sep 27 01:00:50 PM PDT 23
Peak memory 214932 kb
Host smart-66d80c29-dfa4-48b2-9a74-da1e2c18eca2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668950411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2668950411
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2631580156
Short name T243
Test name
Test status
Simulation time 23142046 ps
CPU time 0.9 seconds
Started Sep 27 01:03:06 PM PDT 23
Finished Sep 27 01:03:07 PM PDT 23
Peak memory 215256 kb
Host smart-2a108d53-b488-4798-add8-df4d1b861f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631580156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2631580156
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3402512062
Short name T273
Test name
Test status
Simulation time 49525338 ps
CPU time 1.15 seconds
Started Sep 27 01:03:09 PM PDT 23
Finished Sep 27 01:03:10 PM PDT 23
Peak memory 205708 kb
Host smart-d3e4adac-f6bd-4c1a-b2e1-94b0456b2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402512062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3402512062
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2876756420
Short name T56
Test name
Test status
Simulation time 44069838 ps
CPU time 0.84 seconds
Started Sep 27 01:07:04 PM PDT 23
Finished Sep 27 01:07:05 PM PDT 23
Peak memory 214824 kb
Host smart-b23b6c3a-099f-44c6-9e7e-015cdea6c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876756420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2876756420
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3914284433
Short name T451
Test name
Test status
Simulation time 44812243 ps
CPU time 0.87 seconds
Started Sep 27 01:00:45 PM PDT 23
Finished Sep 27 01:00:47 PM PDT 23
Peak memory 205316 kb
Host smart-334532e1-f401-4e14-906f-2fe939d9b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914284433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3914284433
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1676179584
Short name T612
Test name
Test status
Simulation time 130658751 ps
CPU time 2.83 seconds
Started Sep 27 01:00:48 PM PDT 23
Finished Sep 27 01:00:52 PM PDT 23
Peak memory 206304 kb
Host smart-a597f880-533b-4c2e-9737-9a1ec7e02c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676179584 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1676179584
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1025997270
Short name T674
Test name
Test status
Simulation time 110413072486 ps
CPU time 256.37 seconds
Started Sep 27 01:00:46 PM PDT 23
Finished Sep 27 01:05:03 PM PDT 23
Peak memory 215196 kb
Host smart-2e244cb0-fc1d-4951-bd38-bef361a233cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025997270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1025997270
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.3879305635
Short name T16
Test name
Test status
Simulation time 60932901 ps
CPU time 0.95 seconds
Started Sep 27 01:03:12 PM PDT 23
Finished Sep 27 01:03:14 PM PDT 23
Peak memory 205484 kb
Host smart-8cca8f0d-43ae-4289-8864-98c7c3ca84b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879305635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3879305635
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2629631798
Short name T534
Test name
Test status
Simulation time 65733707 ps
CPU time 0.8 seconds
Started Sep 27 01:11:45 PM PDT 23
Finished Sep 27 01:11:46 PM PDT 23
Peak memory 204820 kb
Host smart-39cda7ad-5e27-47ea-9922-bd8f79575414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629631798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2629631798
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3884828537
Short name T31
Test name
Test status
Simulation time 33325145 ps
CPU time 0.79 seconds
Started Sep 27 01:10:04 PM PDT 23
Finished Sep 27 01:10:05 PM PDT 23
Peak memory 206660 kb
Host smart-a4083785-1bb4-47ed-bb45-f4e237cf8307
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884828537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3884828537
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.1853766365
Short name T665
Test name
Test status
Simulation time 45668791 ps
CPU time 1.21 seconds
Started Sep 27 01:11:18 PM PDT 23
Finished Sep 27 01:11:19 PM PDT 23
Peak memory 227820 kb
Host smart-4233f5c0-2f30-4b6c-9d51-9bb80f1e9644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853766365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1853766365
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.1354601856
Short name T618
Test name
Test status
Simulation time 23671830 ps
CPU time 0.86 seconds
Started Sep 27 01:02:51 PM PDT 23
Finished Sep 27 01:02:52 PM PDT 23
Peak memory 215164 kb
Host smart-ecc7cc4c-4612-4915-871e-5534b328a1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354601856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1354601856
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2330224666
Short name T581
Test name
Test status
Simulation time 38351061 ps
CPU time 0.83 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:46 PM PDT 23
Peak memory 204968 kb
Host smart-a023ad57-d15c-4341-87ca-e57b473574a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330224666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2330224666
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1410061362
Short name T669
Test name
Test status
Simulation time 381526577 ps
CPU time 4.02 seconds
Started Sep 27 01:02:58 PM PDT 23
Finished Sep 27 01:03:02 PM PDT 23
Peak memory 206560 kb
Host smart-0c874a09-9b1c-4479-ab7d-3975dd9b1806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410061362 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1410061362
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2267461259
Short name T575
Test name
Test status
Simulation time 179187282885 ps
CPU time 655.33 seconds
Started Sep 27 01:00:48 PM PDT 23
Finished Sep 27 01:11:44 PM PDT 23
Peak memory 216020 kb
Host smart-b206e6be-dca6-4008-a896-ec3098f4ce46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267461259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2267461259
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.2649334744
Short name T585
Test name
Test status
Simulation time 31398307 ps
CPU time 0.96 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:29 PM PDT 23
Peak memory 206444 kb
Host smart-387f4cfa-2473-4890-9165-e3ba9fb90468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649334744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2649334744
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2129052589
Short name T487
Test name
Test status
Simulation time 15163357 ps
CPU time 0.86 seconds
Started Sep 27 01:01:54 PM PDT 23
Finished Sep 27 01:01:56 PM PDT 23
Peak memory 204960 kb
Host smart-39c31fd7-2bfb-4065-a9cf-ed1c706078f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129052589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2129052589
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2376415915
Short name T175
Test name
Test status
Simulation time 13013867 ps
CPU time 0.88 seconds
Started Sep 27 01:01:53 PM PDT 23
Finished Sep 27 01:01:54 PM PDT 23
Peak memory 214964 kb
Host smart-fe6fca02-1f8d-4bf1-9f72-f40c4fc62c2b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376415915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2376415915
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2608870697
Short name T245
Test name
Test status
Simulation time 29353204 ps
CPU time 1.21 seconds
Started Sep 27 01:01:51 PM PDT 23
Finished Sep 27 01:01:52 PM PDT 23
Peak memory 217412 kb
Host smart-c49d10ba-9bc7-4909-b6fd-da71699aebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608870697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2608870697
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3714852658
Short name T607
Test name
Test status
Simulation time 105324848 ps
CPU time 0.97 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:16 PM PDT 23
Peak memory 205380 kb
Host smart-f1eeea9e-9839-4d4d-8420-44cef8d8a9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714852658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3714852658
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1381718155
Short name T171
Test name
Test status
Simulation time 37989194 ps
CPU time 0.85 seconds
Started Sep 27 01:01:59 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 214648 kb
Host smart-298c9778-f2f8-41d6-aac4-3409baaba657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381718155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1381718155
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1189072865
Short name T464
Test name
Test status
Simulation time 24581908 ps
CPU time 0.87 seconds
Started Sep 27 01:01:11 PM PDT 23
Finished Sep 27 01:01:12 PM PDT 23
Peak memory 205308 kb
Host smart-cad3cd60-f6af-4fe6-a5ec-b1286e8d4e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189072865 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1189072865
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.419529920
Short name T517
Test name
Test status
Simulation time 34990069 ps
CPU time 1.2 seconds
Started Sep 27 01:03:12 PM PDT 23
Finished Sep 27 01:03:14 PM PDT 23
Peak memory 205260 kb
Host smart-3d1bbc37-7c3f-4b8b-8a17-6c554c1c1231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419529920 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.419529920
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2915650193
Short name T478
Test name
Test status
Simulation time 54896572012 ps
CPU time 1152.74 seconds
Started Sep 27 01:01:58 PM PDT 23
Finished Sep 27 01:21:11 PM PDT 23
Peak memory 216008 kb
Host smart-4683ecf4-b515-491f-91c0-c4a8630e88e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915650193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2915650193
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.3769794396
Short name T110
Test name
Test status
Simulation time 61206851 ps
CPU time 1.04 seconds
Started Sep 27 01:01:55 PM PDT 23
Finished Sep 27 01:01:56 PM PDT 23
Peak memory 206536 kb
Host smart-e907097a-f3ea-4f7e-949d-1b7db66e9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769794396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3769794396
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.873206101
Short name T510
Test name
Test status
Simulation time 105649085 ps
CPU time 0.9 seconds
Started Sep 27 01:02:46 PM PDT 23
Finished Sep 27 01:02:47 PM PDT 23
Peak memory 204952 kb
Host smart-ff9c982a-e1fb-4d22-8fcc-200402d18eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873206101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.873206101
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2196581303
Short name T149
Test name
Test status
Simulation time 11310279 ps
CPU time 0.84 seconds
Started Sep 27 01:02:34 PM PDT 23
Finished Sep 27 01:02:35 PM PDT 23
Peak memory 214792 kb
Host smart-bdaf3110-a76f-4feb-940b-a1f0143927f9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196581303 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2196581303
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1919831933
Short name T247
Test name
Test status
Simulation time 30965307 ps
CPU time 0.99 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:06 PM PDT 23
Peak memory 215024 kb
Host smart-5bca7ef4-1f41-48b9-acd2-91a4524001c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919831933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1919831933
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.221228415
Short name T268
Test name
Test status
Simulation time 56107618 ps
CPU time 1.07 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:16 PM PDT 23
Peak memory 205784 kb
Host smart-76bd4e26-67f4-4eb7-ba4a-c7cb432d1655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221228415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.221228415
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2337845830
Short name T574
Test name
Test status
Simulation time 29216724 ps
CPU time 0.99 seconds
Started Sep 27 01:02:50 PM PDT 23
Finished Sep 27 01:02:51 PM PDT 23
Peak memory 221884 kb
Host smart-dc836f5c-86ee-42b3-80d5-f5bc9d9e068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337845830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2337845830
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1920149349
Short name T594
Test name
Test status
Simulation time 26057586 ps
CPU time 0.85 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 205476 kb
Host smart-e8ecc0c7-8a4e-4478-84e6-410f4082a8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920149349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1920149349
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1732168552
Short name T242
Test name
Test status
Simulation time 169688771 ps
CPU time 3.76 seconds
Started Sep 27 01:01:05 PM PDT 23
Finished Sep 27 01:01:09 PM PDT 23
Peak memory 205948 kb
Host smart-b523d726-2759-4955-a7a6-ba548bb8b0a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732168552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1732168552
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1406238655
Short name T458
Test name
Test status
Simulation time 23453043384 ps
CPU time 515.48 seconds
Started Sep 27 01:01:02 PM PDT 23
Finished Sep 27 01:09:38 PM PDT 23
Peak memory 215632 kb
Host smart-fb6c4da3-d69a-42b5-84d4-194eb5f0359a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406238655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1406238655
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert_test.3709047012
Short name T501
Test name
Test status
Simulation time 45061441 ps
CPU time 0.86 seconds
Started Sep 27 01:19:50 PM PDT 23
Finished Sep 27 01:19:51 PM PDT 23
Peak memory 205040 kb
Host smart-8730b047-c6f5-4948-80c6-caaec5ddc62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709047012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3709047012
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_intr.3592882696
Short name T584
Test name
Test status
Simulation time 59308861 ps
CPU time 0.83 seconds
Started Sep 27 01:08:45 PM PDT 23
Finished Sep 27 01:08:46 PM PDT 23
Peak memory 214896 kb
Host smart-c235935e-00e5-4657-a6d6-e3af2596580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592882696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3592882696
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3664587147
Short name T300
Test name
Test status
Simulation time 23219096 ps
CPU time 0.86 seconds
Started Sep 27 01:01:57 PM PDT 23
Finished Sep 27 01:01:58 PM PDT 23
Peak memory 205160 kb
Host smart-7c811697-1155-4aaa-9838-ef3a01e18627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664587147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3664587147
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1818638528
Short name T23
Test name
Test status
Simulation time 357112947 ps
CPU time 6.13 seconds
Started Sep 27 01:00:23 PM PDT 23
Finished Sep 27 01:00:29 PM PDT 23
Peak memory 234312 kb
Host smart-e9865ab6-f7a0-403e-8cf1-e5c84dba3ba3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818638528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1818638528
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.123077463
Short name T580
Test name
Test status
Simulation time 23532401 ps
CPU time 0.82 seconds
Started Sep 27 01:15:26 PM PDT 23
Finished Sep 27 01:15:27 PM PDT 23
Peak memory 205028 kb
Host smart-79c91022-837b-4e5a-9d9c-ac49085676f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123077463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.123077463
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1987488231
Short name T600
Test name
Test status
Simulation time 164550765 ps
CPU time 3.52 seconds
Started Sep 27 01:02:04 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 206472 kb
Host smart-01d30258-5aab-40e1-ab52-dd7bb67b94da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987488231 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1987488231
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1237433833
Short name T438
Test name
Test status
Simulation time 98708774947 ps
CPU time 865.86 seconds
Started Sep 27 01:15:40 PM PDT 23
Finished Sep 27 01:30:06 PM PDT 23
Peak memory 217532 kb
Host smart-398dd6c0-1942-48ee-987b-e9672c4985f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237433833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1237433833
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.2164503661
Short name T435
Test name
Test status
Simulation time 18461756 ps
CPU time 0.96 seconds
Started Sep 27 01:01:51 PM PDT 23
Finished Sep 27 01:01:52 PM PDT 23
Peak memory 205628 kb
Host smart-5662ea37-941e-4f08-8d07-ddffd3848031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164503661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2164503661
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2634264864
Short name T252
Test name
Test status
Simulation time 16389211 ps
CPU time 0.89 seconds
Started Sep 27 01:02:23 PM PDT 23
Finished Sep 27 01:02:24 PM PDT 23
Peak memory 214920 kb
Host smart-64a2fe5d-9869-4888-9521-53a37c087f1e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634264864 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2634264864
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.938413127
Short name T605
Test name
Test status
Simulation time 20455696 ps
CPU time 0.88 seconds
Started Sep 27 01:01:50 PM PDT 23
Finished Sep 27 01:01:51 PM PDT 23
Peak memory 216024 kb
Host smart-79cff2ca-233f-43c9-a68b-29445273f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938413127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.938413127
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3966673948
Short name T282
Test name
Test status
Simulation time 58050612 ps
CPU time 0.93 seconds
Started Sep 27 01:01:01 PM PDT 23
Finished Sep 27 01:01:02 PM PDT 23
Peak memory 205756 kb
Host smart-851e9928-3129-4b4a-9b24-0c13a30bda71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966673948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3966673948
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3816116295
Short name T488
Test name
Test status
Simulation time 21844617 ps
CPU time 1.04 seconds
Started Sep 27 01:02:20 PM PDT 23
Finished Sep 27 01:02:21 PM PDT 23
Peak memory 214884 kb
Host smart-2c560377-eec1-4002-a24c-2dbd32672f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816116295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3816116295
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1281735085
Short name T587
Test name
Test status
Simulation time 12704383 ps
CPU time 0.85 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:06 PM PDT 23
Peak memory 204972 kb
Host smart-d95fecd8-4660-4486-925e-15921aa10d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281735085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1281735085
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1191106221
Short name T642
Test name
Test status
Simulation time 96648452475 ps
CPU time 1047.6 seconds
Started Sep 27 01:02:12 PM PDT 23
Finished Sep 27 01:19:40 PM PDT 23
Peak memory 216352 kb
Host smart-2169806e-f385-4db8-be60-5bf6e03783c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191106221 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1191106221
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert_test.2392895346
Short name T181
Test name
Test status
Simulation time 58474762 ps
CPU time 0.78 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 204388 kb
Host smart-28a13d80-0665-4838-892c-5db023d95c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392895346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2392895346
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2936665133
Short name T246
Test name
Test status
Simulation time 13094637 ps
CPU time 0.88 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 215032 kb
Host smart-2acc8384-d8d0-4a30-a87e-2c24bbd34db8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936665133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2936665133
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.441628177
Short name T555
Test name
Test status
Simulation time 19745678 ps
CPU time 1.04 seconds
Started Sep 27 01:02:01 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 216120 kb
Host smart-12e997b5-a8d8-4cbe-9734-9dfbffa02ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441628177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.441628177
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.437818846
Short name T596
Test name
Test status
Simulation time 22508192 ps
CPU time 1.05 seconds
Started Sep 27 01:02:12 PM PDT 23
Finished Sep 27 01:02:15 PM PDT 23
Peak memory 221740 kb
Host smart-a1b27b39-d1b3-4379-a4d4-dba1d1a06f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437818846 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.437818846
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1739036216
Short name T62
Test name
Test status
Simulation time 13398010 ps
CPU time 0.88 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 204996 kb
Host smart-fd7d30f5-7679-4b49-88dc-0ec04f583e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739036216 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1739036216
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3619881755
Short name T199
Test name
Test status
Simulation time 36403737 ps
CPU time 1.29 seconds
Started Sep 27 01:01:27 PM PDT 23
Finished Sep 27 01:01:28 PM PDT 23
Peak memory 205944 kb
Host smart-0d7ed379-70dc-49c1-84b9-5ec093420462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619881755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3619881755
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3312896465
Short name T672
Test name
Test status
Simulation time 29345873279 ps
CPU time 340.08 seconds
Started Sep 27 01:02:06 PM PDT 23
Finished Sep 27 01:07:46 PM PDT 23
Peak memory 215524 kb
Host smart-8d8814d7-9fcc-48dc-a59e-205dd1add1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312896465 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3312896465
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.3567163080
Short name T491
Test name
Test status
Simulation time 36028625 ps
CPU time 0.97 seconds
Started Sep 27 01:01:55 PM PDT 23
Finished Sep 27 01:01:56 PM PDT 23
Peak memory 206496 kb
Host smart-cb255f41-e328-479d-a80b-133dc54f74c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567163080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3567163080
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3544579957
Short name T619
Test name
Test status
Simulation time 61116604 ps
CPU time 0.85 seconds
Started Sep 27 01:03:56 PM PDT 23
Finished Sep 27 01:03:57 PM PDT 23
Peak memory 205596 kb
Host smart-7bcc2e53-2283-4d85-a565-f582b6429056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544579957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3544579957
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.81126986
Short name T661
Test name
Test status
Simulation time 59976758 ps
CPU time 0.94 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:16 PM PDT 23
Peak memory 215132 kb
Host smart-b8f75247-ede1-4175-8a77-0f6399bfff7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81126986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_dis
able_auto_req_mode.81126986
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3055126130
Short name T151
Test name
Test status
Simulation time 22562527 ps
CPU time 0.94 seconds
Started Sep 27 01:02:00 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 216036 kb
Host smart-0aad90aa-f23a-4772-8265-ca8309d0d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055126130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3055126130
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.258885918
Short name T602
Test name
Test status
Simulation time 15617511 ps
CPU time 0.96 seconds
Started Sep 27 01:01:30 PM PDT 23
Finished Sep 27 01:01:31 PM PDT 23
Peak memory 205832 kb
Host smart-120d0c31-4424-4271-9d50-70ea8ecb1ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258885918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.258885918
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2236489682
Short name T178
Test name
Test status
Simulation time 24282463 ps
CPU time 0.86 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 215072 kb
Host smart-3241c401-7d4a-4274-84f5-d130c9a3d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236489682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2236489682
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4149646678
Short name T97
Test name
Test status
Simulation time 59625616 ps
CPU time 0.78 seconds
Started Sep 27 01:03:27 PM PDT 23
Finished Sep 27 01:03:28 PM PDT 23
Peak memory 204964 kb
Host smart-2f369b83-967f-4786-9b58-0bbe8175fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149646678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4149646678
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.988123202
Short name T241
Test name
Test status
Simulation time 935830633 ps
CPU time 3.95 seconds
Started Sep 27 01:02:02 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 206100 kb
Host smart-7d25184b-3c2b-4224-8531-8b6c9edf3eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988123202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.988123202
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3484940909
Short name T544
Test name
Test status
Simulation time 26619249240 ps
CPU time 605.74 seconds
Started Sep 27 01:01:46 PM PDT 23
Finished Sep 27 01:11:52 PM PDT 23
Peak memory 215948 kb
Host smart-2d0ea7a1-9bdd-4948-9be8-6ecf03c0ed91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484940909 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3484940909
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.1767300829
Short name T255
Test name
Test status
Simulation time 34906878 ps
CPU time 0.99 seconds
Started Sep 27 01:02:32 PM PDT 23
Finished Sep 27 01:02:33 PM PDT 23
Peak memory 206512 kb
Host smart-a6f72a21-3ce6-4594-b702-d8e22eed245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767300829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1767300829
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2774214653
Short name T547
Test name
Test status
Simulation time 69100545 ps
CPU time 0.91 seconds
Started Sep 27 01:03:19 PM PDT 23
Finished Sep 27 01:03:21 PM PDT 23
Peak memory 204952 kb
Host smart-9c6d9246-9a6d-40f0-8e06-0b19dfc35a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774214653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2774214653
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1172891304
Short name T168
Test name
Test status
Simulation time 37669032 ps
CPU time 0.81 seconds
Started Sep 27 01:02:26 PM PDT 23
Finished Sep 27 01:02:27 PM PDT 23
Peak memory 214688 kb
Host smart-342f394d-f528-44fd-b2c8-c439194e6fa2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172891304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1172891304
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.4214785462
Short name T678
Test name
Test status
Simulation time 23756831 ps
CPU time 1.2 seconds
Started Sep 27 01:02:35 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 230508 kb
Host smart-50a29337-d47d-4518-9c35-bf096df21301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214785462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4214785462
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1800525531
Short name T270
Test name
Test status
Simulation time 20847980 ps
CPU time 0.99 seconds
Started Sep 27 01:02:30 PM PDT 23
Finished Sep 27 01:02:31 PM PDT 23
Peak memory 205904 kb
Host smart-0b322f92-c86e-4f4d-999c-a980b38a497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800525531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1800525531
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3274214643
Short name T118
Test name
Test status
Simulation time 20776846 ps
CPU time 0.88 seconds
Started Sep 27 01:02:55 PM PDT 23
Finished Sep 27 01:02:56 PM PDT 23
Peak memory 215096 kb
Host smart-8f87811c-e9f6-47ae-a97e-debcd43ecd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274214643 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3274214643
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3645877331
Short name T613
Test name
Test status
Simulation time 23510941 ps
CPU time 0.87 seconds
Started Sep 27 01:02:04 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 205196 kb
Host smart-c24e8dc7-2021-4586-b24e-1ef0a93014d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645877331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3645877331
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1972882271
Short name T439
Test name
Test status
Simulation time 340238236 ps
CPU time 1.87 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:09 PM PDT 23
Peak memory 206652 kb
Host smart-bb96b5d7-65ef-4668-b59b-4d9c960e96df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972882271 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1972882271
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2403268296
Short name T684
Test name
Test status
Simulation time 79624516501 ps
CPU time 1742.31 seconds
Started Sep 27 01:03:06 PM PDT 23
Finished Sep 27 01:32:10 PM PDT 23
Peak memory 220076 kb
Host smart-0afddc8f-ebe0-4044-8660-6c2f69853654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403268296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2403268296
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert_test.1134943111
Short name T448
Test name
Test status
Simulation time 64390000 ps
CPU time 0.86 seconds
Started Sep 27 01:02:44 PM PDT 23
Finished Sep 27 01:02:45 PM PDT 23
Peak memory 205876 kb
Host smart-3b06bf99-7a40-4ed1-8df8-a54cd79d7d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134943111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1134943111
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_genbits.1712661440
Short name T313
Test name
Test status
Simulation time 22623644 ps
CPU time 0.86 seconds
Started Sep 27 01:03:32 PM PDT 23
Finished Sep 27 01:03:33 PM PDT 23
Peak memory 205180 kb
Host smart-0f1f84d7-2017-4aa1-91e8-0089a7cc1f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712661440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1712661440
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.1674887398
Short name T483
Test name
Test status
Simulation time 39874538 ps
CPU time 0.82 seconds
Started Sep 27 01:01:33 PM PDT 23
Finished Sep 27 01:01:34 PM PDT 23
Peak memory 204904 kb
Host smart-ea41c64d-fa68-4910-9596-4cd31385e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674887398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1674887398
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2352435348
Short name T568
Test name
Test status
Simulation time 160414432 ps
CPU time 3.43 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:11 PM PDT 23
Peak memory 206168 kb
Host smart-1900c4c1-131f-40db-9663-b501ee7fa300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352435348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2352435348
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1262306366
Short name T265
Test name
Test status
Simulation time 792846107647 ps
CPU time 948.8 seconds
Started Sep 27 01:02:31 PM PDT 23
Finished Sep 27 01:18:20 PM PDT 23
Peak memory 216576 kb
Host smart-45a0b17d-5697-4f58-a0f1-22170c863a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262306366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1262306366
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.913634673
Short name T305
Test name
Test status
Simulation time 18735976 ps
CPU time 0.96 seconds
Started Sep 27 01:01:04 PM PDT 23
Finished Sep 27 01:01:05 PM PDT 23
Peak memory 205444 kb
Host smart-e9eacac1-0213-45cd-805b-3e1846748e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913634673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.913634673
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2530261258
Short name T522
Test name
Test status
Simulation time 18514866 ps
CPU time 0.95 seconds
Started Sep 27 01:02:36 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 205520 kb
Host smart-c5d5c08f-fde9-42b0-9ed5-e856dab84217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530261258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2530261258
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_err.3656853513
Short name T88
Test name
Test status
Simulation time 28958245 ps
CPU time 1.21 seconds
Started Sep 27 01:01:06 PM PDT 23
Finished Sep 27 01:01:07 PM PDT 23
Peak memory 217300 kb
Host smart-8667b8e4-9746-40e2-b3c6-ab000fffcc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656853513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3656853513
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.761528902
Short name T290
Test name
Test status
Simulation time 18575351 ps
CPU time 0.96 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:07 PM PDT 23
Peak memory 205448 kb
Host smart-31a8b45f-af61-4ab4-98c3-a992d41c2e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761528902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.761528902
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_smoke.331438711
Short name T610
Test name
Test status
Simulation time 65645168 ps
CPU time 0.84 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:16 PM PDT 23
Peak memory 205100 kb
Host smart-6ae123e8-9de8-4d72-afaf-0cf06d3b4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331438711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.331438711
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.577730819
Short name T521
Test name
Test status
Simulation time 106482400 ps
CPU time 1.64 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 206004 kb
Host smart-f66cfc38-deb6-4a16-a0c4-a93fdbafb237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577730819 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.577730819
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1768239917
Short name T122
Test name
Test status
Simulation time 51027663494 ps
CPU time 284.23 seconds
Started Sep 27 01:01:06 PM PDT 23
Finished Sep 27 01:05:51 PM PDT 23
Peak memory 215560 kb
Host smart-1a8d85eb-1894-4489-841c-b64a941c3027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768239917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1768239917
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.3002355897
Short name T82
Test name
Test status
Simulation time 31551070 ps
CPU time 0.87 seconds
Started Sep 27 01:03:10 PM PDT 23
Finished Sep 27 01:03:11 PM PDT 23
Peak memory 205360 kb
Host smart-d3fc66a9-7aba-4c86-b82c-1363b0143f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002355897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3002355897
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1205650132
Short name T643
Test name
Test status
Simulation time 25659831 ps
CPU time 0.93 seconds
Started Sep 27 01:02:59 PM PDT 23
Finished Sep 27 01:03:00 PM PDT 23
Peak memory 205572 kb
Host smart-f9e23cf4-a3a8-4f80-bbf0-83a45082335b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205650132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1205650132
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3164614187
Short name T73
Test name
Test status
Simulation time 11862551 ps
CPU time 0.83 seconds
Started Sep 27 01:02:19 PM PDT 23
Finished Sep 27 01:02:20 PM PDT 23
Peak memory 214932 kb
Host smart-0f999d45-65f2-4f41-8f7b-dad663610514
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164614187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3164614187
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4242849372
Short name T683
Test name
Test status
Simulation time 40430500 ps
CPU time 1.01 seconds
Started Sep 27 01:01:58 PM PDT 23
Finished Sep 27 01:01:59 PM PDT 23
Peak memory 214976 kb
Host smart-3cc9dfc1-bcff-456c-bf0c-73518eb47e0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242849372 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4242849372
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3877623082
Short name T150
Test name
Test status
Simulation time 42766543 ps
CPU time 1.07 seconds
Started Sep 27 01:02:41 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 217276 kb
Host smart-e942ebb1-f0ef-4d3d-88e3-e53d23186324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877623082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3877623082
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2963848901
Short name T3
Test name
Test status
Simulation time 14587520 ps
CPU time 0.89 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 205328 kb
Host smart-03d2874c-c3d1-45e7-a81c-850e1861f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963848901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2963848901
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1143457367
Short name T46
Test name
Test status
Simulation time 33810535 ps
CPU time 0.91 seconds
Started Sep 27 01:02:10 PM PDT 23
Finished Sep 27 01:02:15 PM PDT 23
Peak memory 221676 kb
Host smart-8948942e-2b80-4dfc-a346-a26913889672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143457367 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1143457367
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4126359261
Short name T513
Test name
Test status
Simulation time 102958370 ps
CPU time 0.81 seconds
Started Sep 27 01:02:59 PM PDT 23
Finished Sep 27 01:03:00 PM PDT 23
Peak memory 205132 kb
Host smart-b165fe6b-3b44-4796-a74b-dcd25bf8e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126359261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4126359261
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2439708192
Short name T667
Test name
Test status
Simulation time 67396648 ps
CPU time 1.77 seconds
Started Sep 27 01:02:50 PM PDT 23
Finished Sep 27 01:02:52 PM PDT 23
Peak memory 205104 kb
Host smart-ec18c2c8-d429-4b23-9ae7-10e805037366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439708192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2439708192
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3662189732
Short name T108
Test name
Test status
Simulation time 186903999658 ps
CPU time 1013.75 seconds
Started Sep 27 01:01:08 PM PDT 23
Finished Sep 27 01:18:02 PM PDT 23
Peak memory 218232 kb
Host smart-1c42e520-fac3-4a11-b8ff-af3061c30664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662189732 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3662189732
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.162997039
Short name T447
Test name
Test status
Simulation time 61458368 ps
CPU time 0.98 seconds
Started Sep 27 01:04:12 PM PDT 23
Finished Sep 27 01:04:23 PM PDT 23
Peak memory 205484 kb
Host smart-fd62982e-0ea2-4bc2-95b3-ad955c91bf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162997039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.162997039
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2528960646
Short name T601
Test name
Test status
Simulation time 21906546 ps
CPU time 0.83 seconds
Started Sep 27 01:02:22 PM PDT 23
Finished Sep 27 01:02:23 PM PDT 23
Peak memory 205596 kb
Host smart-c828914a-f87e-4011-8411-24c4299ff732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528960646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2528960646
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1339394346
Short name T176
Test name
Test status
Simulation time 37647778 ps
CPU time 0.82 seconds
Started Sep 27 01:02:33 PM PDT 23
Finished Sep 27 01:02:34 PM PDT 23
Peak memory 214884 kb
Host smart-b8a4006c-38e7-41a1-a1ce-5753cb1b5acb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339394346 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1339394346
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1844362850
Short name T49
Test name
Test status
Simulation time 36958965 ps
CPU time 1.03 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:05 PM PDT 23
Peak memory 222052 kb
Host smart-5b149e9b-a7ec-45d8-91e8-0fd590b3c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844362850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1844362850
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2331616689
Short name T39
Test name
Test status
Simulation time 217946779 ps
CPU time 1.12 seconds
Started Sep 27 01:02:16 PM PDT 23
Finished Sep 27 01:02:22 PM PDT 23
Peak memory 205620 kb
Host smart-850029c2-2454-4b81-8191-ec0a0ce421c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331616689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2331616689
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4040339163
Short name T647
Test name
Test status
Simulation time 23564658 ps
CPU time 0.98 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:08 PM PDT 23
Peak memory 222008 kb
Host smart-3352157a-fd85-4ef6-99fb-57e5c160dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040339163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4040339163
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2050192096
Short name T492
Test name
Test status
Simulation time 18942692 ps
CPU time 0.86 seconds
Started Sep 27 01:04:01 PM PDT 23
Finished Sep 27 01:04:03 PM PDT 23
Peak memory 204336 kb
Host smart-290c62fd-5e1a-4b17-bf5a-e3eab38217d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050192096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2050192096
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1520826654
Short name T204
Test name
Test status
Simulation time 77616975 ps
CPU time 1.59 seconds
Started Sep 27 01:01:54 PM PDT 23
Finished Sep 27 01:01:57 PM PDT 23
Peak memory 205752 kb
Host smart-3786f21f-a40e-454c-9c0b-e2107cb25c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520826654 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1520826654
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3838546181
Short name T263
Test name
Test status
Simulation time 214509254187 ps
CPU time 346.67 seconds
Started Sep 27 01:02:18 PM PDT 23
Finished Sep 27 01:08:05 PM PDT 23
Peak memory 215860 kb
Host smart-decbf3cb-cd60-43b8-9fa0-bcdd851aa635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838546181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3838546181
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.3072117452
Short name T520
Test name
Test status
Simulation time 33406235 ps
CPU time 0.96 seconds
Started Sep 27 01:03:13 PM PDT 23
Finished Sep 27 01:03:15 PM PDT 23
Peak memory 205576 kb
Host smart-0ca41ae8-8b82-46fe-ae15-40295967288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072117452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3072117452
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3687488178
Short name T592
Test name
Test status
Simulation time 48761793 ps
CPU time 0.79 seconds
Started Sep 27 01:03:14 PM PDT 23
Finished Sep 27 01:03:15 PM PDT 23
Peak memory 204892 kb
Host smart-e358e51a-cca4-4a14-a2e5-68c607fc7ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687488178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3687488178
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.293286316
Short name T526
Test name
Test status
Simulation time 12772063 ps
CPU time 0.83 seconds
Started Sep 27 01:04:08 PM PDT 23
Finished Sep 27 01:04:09 PM PDT 23
Peak memory 214956 kb
Host smart-18dd30e2-8777-4975-b933-b83e77337ee8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293286316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.293286316
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3173921760
Short name T573
Test name
Test status
Simulation time 31449762 ps
CPU time 0.86 seconds
Started Sep 27 01:01:02 PM PDT 23
Finished Sep 27 01:01:03 PM PDT 23
Peak memory 214948 kb
Host smart-293caed3-49d7-435e-9ea9-8d2d2f65a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173921760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3173921760
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_intr.155366784
Short name T515
Test name
Test status
Simulation time 32076944 ps
CPU time 0.85 seconds
Started Sep 27 01:03:01 PM PDT 23
Finished Sep 27 01:03:02 PM PDT 23
Peak memory 214952 kb
Host smart-55425b6e-6d08-4f50-9da9-82f2e298a2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155366784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.155366784
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.845342593
Short name T100
Test name
Test status
Simulation time 43686359 ps
CPU time 0.78 seconds
Started Sep 27 01:04:09 PM PDT 23
Finished Sep 27 01:04:10 PM PDT 23
Peak memory 204952 kb
Host smart-050982bd-48cd-4588-9e32-213e022a32f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845342593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.845342593
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1090323363
Short name T125
Test name
Test status
Simulation time 2233119123 ps
CPU time 3.19 seconds
Started Sep 27 01:01:56 PM PDT 23
Finished Sep 27 01:01:59 PM PDT 23
Peak memory 206560 kb
Host smart-44ff862f-74b2-40a4-bbc7-54a5a7774a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090323363 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1090323363
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3269041785
Short name T490
Test name
Test status
Simulation time 33757026973 ps
CPU time 810.03 seconds
Started Sep 27 01:03:23 PM PDT 23
Finished Sep 27 01:16:54 PM PDT 23
Peak memory 215812 kb
Host smart-04ad8356-3317-4126-a5ae-f0bd10ab514f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269041785 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3269041785
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.3926760396
Short name T303
Test name
Test status
Simulation time 60973867 ps
CPU time 0.98 seconds
Started Sep 27 01:04:03 PM PDT 23
Finished Sep 27 01:04:04 PM PDT 23
Peak memory 205696 kb
Host smart-62ac251b-c376-4067-86a3-11909ce4c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926760396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3926760396
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2245648352
Short name T653
Test name
Test status
Simulation time 39727799 ps
CPU time 0.82 seconds
Started Sep 27 01:03:43 PM PDT 23
Finished Sep 27 01:03:44 PM PDT 23
Peak memory 205808 kb
Host smart-fe93acbb-a921-4fb5-b68f-5b2ed7d13768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245648352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2245648352
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.221066148
Short name T51
Test name
Test status
Simulation time 16637999 ps
CPU time 0.85 seconds
Started Sep 27 01:01:35 PM PDT 23
Finished Sep 27 01:01:36 PM PDT 23
Peak memory 214800 kb
Host smart-e3d3d476-fc10-493d-8bbe-824420be441b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221066148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.221066148
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.3173957084
Short name T251
Test name
Test status
Simulation time 24497533 ps
CPU time 0.96 seconds
Started Sep 27 01:04:01 PM PDT 23
Finished Sep 27 01:04:02 PM PDT 23
Peak memory 215044 kb
Host smart-876f479b-f5c3-460d-8543-ca05d57dc5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173957084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3173957084
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.607901765
Short name T431
Test name
Test status
Simulation time 31122148 ps
CPU time 0.96 seconds
Started Sep 27 01:01:34 PM PDT 23
Finished Sep 27 01:01:35 PM PDT 23
Peak memory 222384 kb
Host smart-5fa3884a-5cb7-4415-8a74-d15b02f0cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607901765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.607901765
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3185475706
Short name T675
Test name
Test status
Simulation time 16927023 ps
CPU time 0.91 seconds
Started Sep 27 01:02:06 PM PDT 23
Finished Sep 27 01:02:07 PM PDT 23
Peak memory 205384 kb
Host smart-58b14d5a-b1b9-42a1-9a98-c097fca1d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185475706 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3185475706
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.342636681
Short name T528
Test name
Test status
Simulation time 493360926 ps
CPU time 3.64 seconds
Started Sep 27 01:02:39 PM PDT 23
Finished Sep 27 01:02:43 PM PDT 23
Peak memory 206592 kb
Host smart-64e4fd10-8a82-4e19-8a71-e7a358871053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342636681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.342636681
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.41284947
Short name T595
Test name
Test status
Simulation time 17212812176 ps
CPU time 203.93 seconds
Started Sep 27 01:01:35 PM PDT 23
Finished Sep 27 01:04:59 PM PDT 23
Peak memory 216160 kb
Host smart-0f26894d-9a20-46c9-91f6-9b5fc92f57dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284947 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.41284947
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.1857771750
Short name T494
Test name
Test status
Simulation time 142292367 ps
CPU time 0.92 seconds
Started Sep 27 01:03:06 PM PDT 23
Finished Sep 27 01:03:08 PM PDT 23
Peak memory 205516 kb
Host smart-0cd75fe3-e985-4219-bd89-265d1d8f103e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857771750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1857771750
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1568404298
Short name T94
Test name
Test status
Simulation time 78173540 ps
CPU time 0.96 seconds
Started Sep 27 01:20:23 PM PDT 23
Finished Sep 27 01:20:24 PM PDT 23
Peak memory 205556 kb
Host smart-f7ee957f-abcc-45e8-acc4-dd682c0080f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568404298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1568404298
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2792810272
Short name T161
Test name
Test status
Simulation time 15491508 ps
CPU time 0.83 seconds
Started Sep 27 01:03:52 PM PDT 23
Finished Sep 27 01:03:53 PM PDT 23
Peak memory 214864 kb
Host smart-37cbea33-46ad-4db2-b19a-d68ba2715e07
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792810272 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2792810272
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.3853552450
Short name T452
Test name
Test status
Simulation time 28101636 ps
CPU time 0.82 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 215736 kb
Host smart-34f5ca43-24a7-4764-89e1-2efea33f40e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853552450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3853552450
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_intr.55747568
Short name T663
Test name
Test status
Simulation time 19651755 ps
CPU time 1.02 seconds
Started Sep 27 01:01:03 PM PDT 23
Finished Sep 27 01:01:04 PM PDT 23
Peak memory 215088 kb
Host smart-616100d1-a1b7-4dbe-bc77-e5513ded8ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55747568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.55747568
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.179823311
Short name T546
Test name
Test status
Simulation time 12385143 ps
CPU time 0.87 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:29 PM PDT 23
Peak memory 205232 kb
Host smart-ce609141-4057-462e-92b6-9be8c75cce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179823311 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.179823311
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.968029934
Short name T54
Test name
Test status
Simulation time 441927794 ps
CPU time 7.02 seconds
Started Sep 27 01:08:41 PM PDT 23
Finished Sep 27 01:08:48 PM PDT 23
Peak memory 233640 kb
Host smart-8c455253-586f-4757-8869-5a2c77889496
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968029934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.968029934
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2641366999
Short name T485
Test name
Test status
Simulation time 58020346 ps
CPU time 0.79 seconds
Started Sep 27 01:15:09 PM PDT 23
Finished Sep 27 01:15:11 PM PDT 23
Peak memory 205072 kb
Host smart-f525e9cc-b131-4d05-81d3-540f0553da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641366999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2641366999
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2412892613
Short name T444
Test name
Test status
Simulation time 217607813 ps
CPU time 1.87 seconds
Started Sep 27 01:01:00 PM PDT 23
Finished Sep 27 01:01:03 PM PDT 23
Peak memory 205732 kb
Host smart-bbe60cfc-ab34-4fac-86da-5ea75aafce33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412892613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2412892613
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3691439227
Short name T440
Test name
Test status
Simulation time 221404607090 ps
CPU time 1056.27 seconds
Started Sep 27 01:01:20 PM PDT 23
Finished Sep 27 01:18:56 PM PDT 23
Peak memory 216884 kb
Host smart-07788ecc-6d0b-4f08-bb70-f8f069547cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691439227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3691439227
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.643068506
Short name T306
Test name
Test status
Simulation time 53697919 ps
CPU time 0.88 seconds
Started Sep 27 01:10:05 PM PDT 23
Finished Sep 27 01:10:06 PM PDT 23
Peak memory 205564 kb
Host smart-600ffcf4-f63a-4a26-bee4-fc615e6fe92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643068506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.643068506
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3174795057
Short name T319
Test name
Test status
Simulation time 47798004 ps
CPU time 0.87 seconds
Started Sep 27 01:04:08 PM PDT 23
Finished Sep 27 01:04:15 PM PDT 23
Peak memory 204048 kb
Host smart-801e9b5e-3fe0-4946-8127-3b5da01b95cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174795057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3174795057
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.3034155497
Short name T307
Test name
Test status
Simulation time 28984746 ps
CPU time 1 seconds
Started Sep 27 01:04:36 PM PDT 23
Finished Sep 27 01:04:38 PM PDT 23
Peak memory 228968 kb
Host smart-454a2bbf-9d29-4958-bb81-dfb04f3bccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034155497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3034155497
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2383666592
Short name T549
Test name
Test status
Simulation time 180920911 ps
CPU time 0.84 seconds
Started Sep 27 01:03:03 PM PDT 23
Finished Sep 27 01:03:04 PM PDT 23
Peak memory 205548 kb
Host smart-3637ffde-36d4-46f8-8e9b-f63675fc2a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383666592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2383666592
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3240405062
Short name T459
Test name
Test status
Simulation time 28700238 ps
CPU time 1.1 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:47 PM PDT 23
Peak memory 214056 kb
Host smart-fd2527c9-ac94-4d58-a15d-8b2404035a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240405062 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3240405062
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3438000700
Short name T635
Test name
Test status
Simulation time 22001687 ps
CPU time 0.85 seconds
Started Sep 27 01:01:38 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 205216 kb
Host smart-01177477-32a0-44f0-aa9c-b862baf93e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438000700 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3438000700
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2293018712
Short name T636
Test name
Test status
Simulation time 558270941 ps
CPU time 2.89 seconds
Started Sep 27 01:02:58 PM PDT 23
Finished Sep 27 01:03:02 PM PDT 23
Peak memory 206512 kb
Host smart-a6392bed-2279-4bac-8a85-d8dbdfa3fcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293018712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2293018712
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.205585336
Short name T550
Test name
Test status
Simulation time 402161248022 ps
CPU time 1838.35 seconds
Started Sep 27 01:01:54 PM PDT 23
Finished Sep 27 01:32:33 PM PDT 23
Peak memory 219788 kb
Host smart-7602a47d-b080-4be0-99fc-43c8381188e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205585336 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.205585336
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3351326991
Short name T616
Test name
Test status
Simulation time 20862299 ps
CPU time 1.01 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:08 PM PDT 23
Peak memory 206472 kb
Host smart-3c316213-bef2-4e73-9139-6c9a23c0be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351326991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3351326991
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1676925109
Short name T83
Test name
Test status
Simulation time 50814484 ps
CPU time 0.91 seconds
Started Sep 27 01:02:53 PM PDT 23
Finished Sep 27 01:02:54 PM PDT 23
Peak memory 205508 kb
Host smart-2770668d-c3bb-4655-a5ac-5fadb1cd1217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676925109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1676925109
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_err.3125380786
Short name T136
Test name
Test status
Simulation time 28135783 ps
CPU time 1.04 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 215072 kb
Host smart-5c4d1b68-2e71-4512-b401-73fb8f5a6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125380786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3125380786
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3792694690
Short name T284
Test name
Test status
Simulation time 36555444 ps
CPU time 0.98 seconds
Started Sep 27 01:01:59 PM PDT 23
Finished Sep 27 01:02:00 PM PDT 23
Peak memory 205448 kb
Host smart-94c0d98c-1824-4f0a-88dc-41b34d5194fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792694690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3792694690
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.4126238155
Short name T582
Test name
Test status
Simulation time 20695105 ps
CPU time 1.15 seconds
Started Sep 27 01:02:33 PM PDT 23
Finished Sep 27 01:02:35 PM PDT 23
Peak memory 221832 kb
Host smart-1a72201b-78d2-4e7b-9f61-5136ddd3f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126238155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4126238155
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3549434655
Short name T516
Test name
Test status
Simulation time 16641523 ps
CPU time 0.81 seconds
Started Sep 27 01:03:52 PM PDT 23
Finished Sep 27 01:03:53 PM PDT 23
Peak memory 204960 kb
Host smart-54375982-8bd2-4884-ada9-f09725ad9ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549434655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3549434655
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4018273914
Short name T479
Test name
Test status
Simulation time 324678573 ps
CPU time 2.31 seconds
Started Sep 27 01:03:14 PM PDT 23
Finished Sep 27 01:03:17 PM PDT 23
Peak memory 206328 kb
Host smart-589e3c37-85f0-4d1c-b661-d31bf1ad1c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018273914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4018273914
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.2512636153
Short name T17
Test name
Test status
Simulation time 20381878 ps
CPU time 0.95 seconds
Started Sep 27 01:02:54 PM PDT 23
Finished Sep 27 01:02:56 PM PDT 23
Peak memory 205536 kb
Host smart-9eb9188a-7df3-4b47-a266-d009ce41931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512636153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2512636153
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4202641369
Short name T92
Test name
Test status
Simulation time 20741563 ps
CPU time 0.79 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:04 PM PDT 23
Peak memory 204464 kb
Host smart-0ec36204-a34e-4cdf-b4cf-6d83f1eefdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202641369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4202641369
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1074950246
Short name T105
Test name
Test status
Simulation time 38459562 ps
CPU time 0.8 seconds
Started Sep 27 01:04:29 PM PDT 23
Finished Sep 27 01:04:30 PM PDT 23
Peak memory 214784 kb
Host smart-1443acd4-bc86-4fac-a4cb-e91bdd79a68f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074950246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1074950246
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.3028477364
Short name T589
Test name
Test status
Simulation time 42807340 ps
CPU time 0.97 seconds
Started Sep 27 01:03:45 PM PDT 23
Finished Sep 27 01:03:46 PM PDT 23
Peak memory 217248 kb
Host smart-16bceef2-c202-4dad-96aa-8b1a747e7125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028477364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3028477364
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3618939183
Short name T649
Test name
Test status
Simulation time 48422356 ps
CPU time 0.97 seconds
Started Sep 27 01:03:02 PM PDT 23
Finished Sep 27 01:03:04 PM PDT 23
Peak memory 205548 kb
Host smart-ecc6841c-9508-4ea8-83e8-b1ada535fa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618939183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3618939183
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1766562547
Short name T687
Test name
Test status
Simulation time 19414247 ps
CPU time 1 seconds
Started Sep 27 01:02:40 PM PDT 23
Finished Sep 27 01:02:41 PM PDT 23
Peak memory 214956 kb
Host smart-ad447ad9-acfd-419b-9924-7fbe21d31529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766562547 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1766562547
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4096334679
Short name T481
Test name
Test status
Simulation time 13096044 ps
CPU time 0.83 seconds
Started Sep 27 01:02:42 PM PDT 23
Finished Sep 27 01:02:43 PM PDT 23
Peak memory 205160 kb
Host smart-8ca4b4f6-811d-479b-8c76-adc959f1d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096334679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4096334679
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.39101124
Short name T87
Test name
Test status
Simulation time 356368054 ps
CPU time 3.87 seconds
Started Sep 27 01:01:15 PM PDT 23
Finished Sep 27 01:01:19 PM PDT 23
Peak memory 206544 kb
Host smart-d54feed0-453a-4932-81f9-fa3e8a6fd054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.39101124
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.990832117
Short name T563
Test name
Test status
Simulation time 47475237689 ps
CPU time 520.98 seconds
Started Sep 27 01:02:02 PM PDT 23
Finished Sep 27 01:10:45 PM PDT 23
Peak memory 216548 kb
Host smart-b3f917fd-16b9-4f86-9e54-9f67dd15cfc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990832117 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.990832117
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3106129766
Short name T302
Test name
Test status
Simulation time 44409076 ps
CPU time 0.87 seconds
Started Sep 27 01:03:15 PM PDT 23
Finished Sep 27 01:03:16 PM PDT 23
Peak memory 206396 kb
Host smart-8e18cb8c-ddc1-4985-ba03-d3c5951950e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106129766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3106129766
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2659697952
Short name T502
Test name
Test status
Simulation time 43263511 ps
CPU time 0.83 seconds
Started Sep 27 01:04:05 PM PDT 23
Finished Sep 27 01:04:06 PM PDT 23
Peak memory 204864 kb
Host smart-70d8f40a-2aa1-42ce-866a-3b97ff1c5cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659697952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2659697952
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.1167120848
Short name T144
Test name
Test status
Simulation time 65521874 ps
CPU time 1.01 seconds
Started Sep 27 01:04:36 PM PDT 23
Finished Sep 27 01:04:38 PM PDT 23
Peak memory 214932 kb
Host smart-8266721a-b37d-47e9-8a13-39d0aa042b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167120848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1167120848
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.923998190
Short name T2
Test name
Test status
Simulation time 60883522 ps
CPU time 0.86 seconds
Started Sep 27 01:02:57 PM PDT 23
Finished Sep 27 01:02:58 PM PDT 23
Peak memory 205300 kb
Host smart-ddd00357-21ce-45da-b362-3e43f48017b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923998190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.923998190
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3121731182
Short name T498
Test name
Test status
Simulation time 32639283 ps
CPU time 0.84 seconds
Started Sep 27 01:01:39 PM PDT 23
Finished Sep 27 01:01:40 PM PDT 23
Peak memory 214876 kb
Host smart-a059d058-65b4-41f9-bad4-62168f871c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121731182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3121731182
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1739000984
Short name T506
Test name
Test status
Simulation time 36031426 ps
CPU time 0.81 seconds
Started Sep 27 01:02:34 PM PDT 23
Finished Sep 27 01:02:35 PM PDT 23
Peak memory 205092 kb
Host smart-5c15cb91-d70c-4917-b56f-16e065cf9b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739000984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1739000984
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4148748980
Short name T508
Test name
Test status
Simulation time 611199269 ps
CPU time 2.02 seconds
Started Sep 27 01:02:46 PM PDT 23
Finished Sep 27 01:02:48 PM PDT 23
Peak memory 206152 kb
Host smart-3870dbc9-5309-401b-8acf-9cc3395348d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148748980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4148748980
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.2114189850
Short name T505
Test name
Test status
Simulation time 80071711 ps
CPU time 0.87 seconds
Started Sep 27 01:03:34 PM PDT 23
Finished Sep 27 01:03:35 PM PDT 23
Peak memory 205456 kb
Host smart-f34f6c33-a46b-4992-b59f-073e0f921727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114189850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2114189850
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.61548806
Short name T445
Test name
Test status
Simulation time 39810918 ps
CPU time 0.99 seconds
Started Sep 27 01:02:12 PM PDT 23
Finished Sep 27 01:02:13 PM PDT 23
Peak memory 205020 kb
Host smart-39fb1352-4b4c-456c-9fe3-9eb50f241a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61548806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.61548806
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.555939107
Short name T71
Test name
Test status
Simulation time 30853468 ps
CPU time 0.79 seconds
Started Sep 27 01:02:11 PM PDT 23
Finished Sep 27 01:02:12 PM PDT 23
Peak memory 214852 kb
Host smart-2678735c-4130-4dd0-a269-3a8e30ded316
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555939107 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.555939107
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.716628634
Short name T143
Test name
Test status
Simulation time 80836716 ps
CPU time 1.02 seconds
Started Sep 27 01:02:11 PM PDT 23
Finished Sep 27 01:02:12 PM PDT 23
Peak memory 215016 kb
Host smart-dca7e606-df6d-474f-8958-87d1f512d2d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716628634 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.716628634
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3723374718
Short name T660
Test name
Test status
Simulation time 32295940 ps
CPU time 0.84 seconds
Started Sep 27 01:04:13 PM PDT 23
Finished Sep 27 01:04:14 PM PDT 23
Peak memory 216036 kb
Host smart-2859e870-2e2c-4041-bb0f-e53cfcff1dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723374718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3723374718
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1320483548
Short name T86
Test name
Test status
Simulation time 152915445 ps
CPU time 0.96 seconds
Started Sep 27 01:04:16 PM PDT 23
Finished Sep 27 01:04:17 PM PDT 23
Peak memory 205448 kb
Host smart-d05764fa-1caf-4885-9836-5e1edc8cc312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320483548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1320483548
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.379677370
Short name T63
Test name
Test status
Simulation time 34760585 ps
CPU time 0.87 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:46 PM PDT 23
Peak memory 205200 kb
Host smart-d73ec2ce-97e5-4926-9fc5-3ebacc934933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379677370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.379677370
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2045899010
Short name T633
Test name
Test status
Simulation time 250866729 ps
CPU time 1.05 seconds
Started Sep 27 01:04:41 PM PDT 23
Finished Sep 27 01:04:42 PM PDT 23
Peak memory 205884 kb
Host smart-eaf2c2ff-749b-4c57-8f92-ab32ac915b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045899010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2045899010
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3318294238
Short name T497
Test name
Test status
Simulation time 37925209858 ps
CPU time 851.83 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:16:27 PM PDT 23
Peak memory 215412 kb
Host smart-0af8732b-a13d-46fd-b144-d8c33aac404d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318294238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3318294238
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2718454985
Short name T18
Test name
Test status
Simulation time 76922699 ps
CPU time 0.92 seconds
Started Sep 27 01:02:33 PM PDT 23
Finished Sep 27 01:02:34 PM PDT 23
Peak memory 206380 kb
Host smart-a7887249-1fc6-4d28-9a19-945a32b73fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718454985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2718454985
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3283344826
Short name T673
Test name
Test status
Simulation time 26858131 ps
CPU time 0.88 seconds
Started Sep 27 01:03:27 PM PDT 23
Finished Sep 27 01:03:28 PM PDT 23
Peak memory 204976 kb
Host smart-83cf1e73-98f2-47cc-a4a1-18bed0ee12c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283344826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3283344826
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_err.1590273560
Short name T126
Test name
Test status
Simulation time 32866773 ps
CPU time 1.07 seconds
Started Sep 27 01:02:03 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 216392 kb
Host smart-b3c07979-8ce9-418f-bdd9-7cad977c1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590273560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1590273560
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3660284863
Short name T69
Test name
Test status
Simulation time 52352992 ps
CPU time 0.87 seconds
Started Sep 27 01:01:18 PM PDT 23
Finished Sep 27 01:01:19 PM PDT 23
Peak memory 205220 kb
Host smart-6bb8e730-18db-4408-8146-8226b70f970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660284863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3660284863
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2909015270
Short name T558
Test name
Test status
Simulation time 19758803 ps
CPU time 0.93 seconds
Started Sep 27 01:02:31 PM PDT 23
Finished Sep 27 01:02:32 PM PDT 23
Peak memory 214836 kb
Host smart-e9c78441-dbf7-4371-8f18-e3c264ea64c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909015270 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2909015270
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4175905755
Short name T562
Test name
Test status
Simulation time 83780356 ps
CPU time 0.84 seconds
Started Sep 27 01:02:25 PM PDT 23
Finished Sep 27 01:02:26 PM PDT 23
Peak memory 205272 kb
Host smart-860e72f3-aec5-43f6-a1a7-a1b4ce8af5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175905755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4175905755
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2209725358
Short name T586
Test name
Test status
Simulation time 321814741 ps
CPU time 2.62 seconds
Started Sep 27 01:03:04 PM PDT 23
Finished Sep 27 01:03:07 PM PDT 23
Peak memory 205752 kb
Host smart-9f2d0597-400b-46e4-b684-f149e43190e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209725358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2209725358
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.44858301
Short name T541
Test name
Test status
Simulation time 14410856118 ps
CPU time 84.89 seconds
Started Sep 27 01:03:35 PM PDT 23
Finished Sep 27 01:05:00 PM PDT 23
Peak memory 216016 kb
Host smart-324cf263-5262-4fcb-b996-c8ce18ee5f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44858301 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.44858301
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2272807346
Short name T74
Test name
Test status
Simulation time 19921665 ps
CPU time 0.98 seconds
Started Sep 27 01:02:19 PM PDT 23
Finished Sep 27 01:02:21 PM PDT 23
Peak memory 206396 kb
Host smart-97ff87b4-e07d-44b5-92cc-717bf06843c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272807346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2272807346
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3263959779
Short name T651
Test name
Test status
Simulation time 67219216 ps
CPU time 0.95 seconds
Started Sep 27 01:01:14 PM PDT 23
Finished Sep 27 01:01:15 PM PDT 23
Peak memory 205072 kb
Host smart-42cb79f6-9859-4c40-bbfa-7b721930811b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263959779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3263959779
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3048452726
Short name T597
Test name
Test status
Simulation time 59358304 ps
CPU time 0.91 seconds
Started Sep 27 01:04:29 PM PDT 23
Finished Sep 27 01:04:30 PM PDT 23
Peak memory 214976 kb
Host smart-01ce2b87-c8fe-4861-a778-d00b2f92f0c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048452726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3048452726
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2265075155
Short name T679
Test name
Test status
Simulation time 23872143 ps
CPU time 0.91 seconds
Started Sep 27 01:02:17 PM PDT 23
Finished Sep 27 01:02:18 PM PDT 23
Peak memory 215888 kb
Host smart-541751fe-8b68-4b64-aad9-a4959325b0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265075155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2265075155
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3534621391
Short name T583
Test name
Test status
Simulation time 43436491 ps
CPU time 1.03 seconds
Started Sep 27 01:04:16 PM PDT 23
Finished Sep 27 01:04:18 PM PDT 23
Peak memory 205620 kb
Host smart-c6987110-e0d2-4f27-822b-d14b53569f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534621391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3534621391
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3189749679
Short name T670
Test name
Test status
Simulation time 37306500 ps
CPU time 0.95 seconds
Started Sep 27 01:03:16 PM PDT 23
Finished Sep 27 01:03:17 PM PDT 23
Peak memory 221832 kb
Host smart-225ded25-c8e2-4c5a-9148-c9738698746e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189749679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3189749679
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1147997089
Short name T474
Test name
Test status
Simulation time 40311018 ps
CPU time 0.82 seconds
Started Sep 27 01:03:34 PM PDT 23
Finished Sep 27 01:03:35 PM PDT 23
Peak memory 205096 kb
Host smart-8d716f1c-a262-4e62-aca1-3a46287446de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147997089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1147997089
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1817645818
Short name T514
Test name
Test status
Simulation time 551335847 ps
CPU time 1.74 seconds
Started Sep 27 01:02:56 PM PDT 23
Finished Sep 27 01:02:57 PM PDT 23
Peak memory 206328 kb
Host smart-0ff5b384-22c0-437e-a88a-fc2a21388b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817645818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1817645818
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3965693636
Short name T482
Test name
Test status
Simulation time 266114892584 ps
CPU time 1466.78 seconds
Started Sep 27 01:02:14 PM PDT 23
Finished Sep 27 01:26:41 PM PDT 23
Peak memory 219444 kb
Host smart-ce93e819-2d07-493f-99b0-fbfa5f229b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965693636 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3965693636
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.278405548
Short name T656
Test name
Test status
Simulation time 31997329 ps
CPU time 0.96 seconds
Started Sep 27 01:02:56 PM PDT 23
Finished Sep 27 01:02:58 PM PDT 23
Peak memory 206460 kb
Host smart-aaed7d78-b2af-4c7f-9cfb-4a07a2224df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278405548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.278405548
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3773347733
Short name T182
Test name
Test status
Simulation time 47158289 ps
CPU time 0.9 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 205864 kb
Host smart-9da89c40-53fa-4c86-8d61-8dad969bb3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773347733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3773347733
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1767715297
Short name T627
Test name
Test status
Simulation time 40939503 ps
CPU time 0.8 seconds
Started Sep 27 01:04:48 PM PDT 23
Finished Sep 27 01:04:49 PM PDT 23
Peak memory 214756 kb
Host smart-4a213ab7-19c5-4c53-aed0-51253573ca3c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767715297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1767715297
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2512913360
Short name T48
Test name
Test status
Simulation time 25280857 ps
CPU time 1.08 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:29 PM PDT 23
Peak memory 228912 kb
Host smart-d865575c-63e0-4166-9c6a-bc2e28e970eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512913360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2512913360
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3959675977
Short name T191
Test name
Test status
Simulation time 20155727 ps
CPU time 1.01 seconds
Started Sep 27 01:02:02 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 205288 kb
Host smart-01af4346-f9d0-4cbe-a04c-8f6edae9b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959675977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3959675977
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3415191432
Short name T629
Test name
Test status
Simulation time 19409094 ps
CPU time 1.11 seconds
Started Sep 27 01:03:57 PM PDT 23
Finished Sep 27 01:03:58 PM PDT 23
Peak memory 225888 kb
Host smart-2e103233-a1e7-4d84-af4a-15f7b6fd40ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415191432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3415191432
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1281521898
Short name T308
Test name
Test status
Simulation time 70914994 ps
CPU time 0.84 seconds
Started Sep 27 01:02:31 PM PDT 23
Finished Sep 27 01:02:32 PM PDT 23
Peak memory 205128 kb
Host smart-852c956a-5c40-4b6e-b2c3-4baf2daf53d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281521898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1281521898
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1293357822
Short name T599
Test name
Test status
Simulation time 536544706 ps
CPU time 3.37 seconds
Started Sep 27 01:02:56 PM PDT 23
Finished Sep 27 01:02:59 PM PDT 23
Peak memory 206596 kb
Host smart-a13498bd-ad3a-4f49-b536-116ad3ff66a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293357822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1293357822
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2108889163
Short name T650
Test name
Test status
Simulation time 225508184767 ps
CPU time 316.33 seconds
Started Sep 27 01:03:46 PM PDT 23
Finished Sep 27 01:09:03 PM PDT 23
Peak memory 214308 kb
Host smart-13f3410a-ea0b-425d-9e40-44c7db0ec428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108889163 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2108889163
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3987566670
Short name T190
Test name
Test status
Simulation time 39139356 ps
CPU time 0.96 seconds
Started Sep 27 01:02:39 PM PDT 23
Finished Sep 27 01:02:40 PM PDT 23
Peak memory 206496 kb
Host smart-0b5e6e29-9cfb-465b-afd5-ca48845cfb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987566670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3987566670
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3231461127
Short name T320
Test name
Test status
Simulation time 28509275 ps
CPU time 0.83 seconds
Started Sep 27 01:04:32 PM PDT 23
Finished Sep 27 01:04:33 PM PDT 23
Peak memory 205816 kb
Host smart-25f82f55-3420-41b7-9fa1-5cd050a7fd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231461127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3231461127
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4132791463
Short name T159
Test name
Test status
Simulation time 33230765 ps
CPU time 0.82 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:29 PM PDT 23
Peak memory 214836 kb
Host smart-854e256f-9f9a-4ca9-987f-16cf71f76503
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132791463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4132791463
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.4271397756
Short name T4
Test name
Test status
Simulation time 64064753 ps
CPU time 0.81 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:29 PM PDT 23
Peak memory 214888 kb
Host smart-cce62005-c028-465c-ba95-c0cfde2ea528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271397756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4271397756
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1324481904
Short name T530
Test name
Test status
Simulation time 333994865 ps
CPU time 1.06 seconds
Started Sep 27 01:02:23 PM PDT 23
Finished Sep 27 01:02:25 PM PDT 23
Peak memory 205576 kb
Host smart-6b5a2abf-d7c5-4e86-860e-3eac5b6dd603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324481904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1324481904
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2417052487
Short name T32
Test name
Test status
Simulation time 44337291 ps
CPU time 0.81 seconds
Started Sep 27 01:02:01 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 214980 kb
Host smart-b5b0d6d4-c0b3-4c76-97cd-b11f257c28fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417052487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2417052487
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2780706093
Short name T611
Test name
Test status
Simulation time 14807710 ps
CPU time 0.86 seconds
Started Sep 27 01:02:18 PM PDT 23
Finished Sep 27 01:02:19 PM PDT 23
Peak memory 205316 kb
Host smart-360d1f1a-fb2b-437e-a341-abec5f9eaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780706093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2780706093
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2528322355
Short name T571
Test name
Test status
Simulation time 131264111 ps
CPU time 2.84 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:31 PM PDT 23
Peak memory 205968 kb
Host smart-2afc5ca3-1cad-4555-b9dc-6a75ffe13364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528322355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2528322355
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2185263388
Short name T456
Test name
Test status
Simulation time 70990642541 ps
CPU time 739.23 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:14:35 PM PDT 23
Peak memory 214996 kb
Host smart-cb6170a8-2dec-4ee4-a6ee-7fc35c9b6490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185263388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2185263388
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4108837777
Short name T301
Test name
Test status
Simulation time 19942964 ps
CPU time 0.98 seconds
Started Sep 27 01:04:10 PM PDT 23
Finished Sep 27 01:04:11 PM PDT 23
Peak memory 205332 kb
Host smart-9da40fd4-9ee6-4202-8f13-ee26a5bb50e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108837777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4108837777
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1050155525
Short name T539
Test name
Test status
Simulation time 17750354 ps
CPU time 0.92 seconds
Started Sep 27 01:02:56 PM PDT 23
Finished Sep 27 01:02:58 PM PDT 23
Peak memory 205552 kb
Host smart-1be96413-ae26-4234-ada0-8aef698a804b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050155525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1050155525
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.503310661
Short name T80
Test name
Test status
Simulation time 30862123 ps
CPU time 0.84 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 214836 kb
Host smart-f490e70f-c794-4f8b-89a0-1776787a60e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503310661 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.503310661
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3003520255
Short name T160
Test name
Test status
Simulation time 32877263 ps
CPU time 0.79 seconds
Started Sep 27 01:03:15 PM PDT 23
Finished Sep 27 01:03:16 PM PDT 23
Peak memory 215676 kb
Host smart-5d3fa588-416c-4a38-974f-56a5641bb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003520255 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3003520255
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_intr.3938163511
Short name T681
Test name
Test status
Simulation time 21934284 ps
CPU time 0.99 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:30 PM PDT 23
Peak memory 215048 kb
Host smart-ca10e19d-28c1-4e07-b347-2a0f2b4417c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938163511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3938163511
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2435353241
Short name T315
Test name
Test status
Simulation time 15377228 ps
CPU time 0.9 seconds
Started Sep 27 01:02:10 PM PDT 23
Finished Sep 27 01:02:11 PM PDT 23
Peak memory 205224 kb
Host smart-8dca46af-7ec5-4af8-aee9-e3a320210b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435353241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2435353241
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.603908024
Short name T668
Test name
Test status
Simulation time 134744186 ps
CPU time 3.34 seconds
Started Sep 27 01:02:50 PM PDT 23
Finished Sep 27 01:02:53 PM PDT 23
Peak memory 206256 kb
Host smart-8d365a66-b265-4e66-8da9-5209265b6e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603908024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.603908024
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1067394655
Short name T682
Test name
Test status
Simulation time 72489299329 ps
CPU time 758.21 seconds
Started Sep 27 01:04:26 PM PDT 23
Finished Sep 27 01:17:06 PM PDT 23
Peak memory 215780 kb
Host smart-3c79f548-a3bb-4b94-929c-390f999ed3cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067394655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1067394655
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1880709876
Short name T295
Test name
Test status
Simulation time 71837728 ps
CPU time 0.88 seconds
Started Sep 27 01:08:52 PM PDT 23
Finished Sep 27 01:08:54 PM PDT 23
Peak memory 206516 kb
Host smart-0a04cbfa-05a4-4ea4-9b51-456d4087b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880709876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1880709876
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3924541519
Short name T572
Test name
Test status
Simulation time 49251334 ps
CPU time 0.87 seconds
Started Sep 27 01:01:48 PM PDT 23
Finished Sep 27 01:01:49 PM PDT 23
Peak memory 204964 kb
Host smart-cdf74b43-8f27-4b29-afc6-548a327ce6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924541519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3924541519
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2636790995
Short name T620
Test name
Test status
Simulation time 22022214 ps
CPU time 0.83 seconds
Started Sep 27 01:00:25 PM PDT 23
Finished Sep 27 01:00:26 PM PDT 23
Peak memory 214904 kb
Host smart-901747ef-d072-4739-afaa-42f001133171
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636790995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2636790995
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1163630575
Short name T249
Test name
Test status
Simulation time 42361241 ps
CPU time 1.13 seconds
Started Sep 27 01:15:13 PM PDT 23
Finished Sep 27 01:15:15 PM PDT 23
Peak memory 222252 kb
Host smart-688549f1-db78-4909-9287-735f05185cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163630575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1163630575
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_intr.3535164422
Short name T114
Test name
Test status
Simulation time 22967604 ps
CPU time 0.83 seconds
Started Sep 27 01:13:56 PM PDT 23
Finished Sep 27 01:13:57 PM PDT 23
Peak memory 215016 kb
Host smart-ba1632c1-fbc2-458b-b8b9-b0f746af3f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535164422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3535164422
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.205631274
Short name T578
Test name
Test status
Simulation time 14641850 ps
CPU time 0.87 seconds
Started Sep 27 01:10:31 PM PDT 23
Finished Sep 27 01:10:33 PM PDT 23
Peak memory 205228 kb
Host smart-3f591a7c-6110-4431-825b-e7cb5f6e8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205631274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.205631274
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1547413220
Short name T24
Test name
Test status
Simulation time 1250430080 ps
CPU time 3.04 seconds
Started Sep 27 01:00:27 PM PDT 23
Finished Sep 27 01:00:31 PM PDT 23
Peak memory 232300 kb
Host smart-3c6513bd-a536-46ae-a773-66dd229b5e79
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547413220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1547413220
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2875931465
Short name T193
Test name
Test status
Simulation time 54522565 ps
CPU time 0.92 seconds
Started Sep 27 01:07:12 PM PDT 23
Finished Sep 27 01:07:13 PM PDT 23
Peak memory 205284 kb
Host smart-0d8c4b0a-548d-4436-ae04-44b64994303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875931465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2875931465
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4294714072
Short name T461
Test name
Test status
Simulation time 135575475 ps
CPU time 3.09 seconds
Started Sep 27 01:03:48 PM PDT 23
Finished Sep 27 01:03:52 PM PDT 23
Peak memory 206308 kb
Host smart-f369753b-d724-47bb-b9e3-e8b3f0150ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294714072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4294714072
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2775594397
Short name T454
Test name
Test status
Simulation time 281225775532 ps
CPU time 1455.31 seconds
Started Sep 27 01:08:42 PM PDT 23
Finished Sep 27 01:32:58 PM PDT 23
Peak memory 218924 kb
Host smart-518d6322-8b60-4b21-9fcd-ea6cabfad299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775594397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2775594397
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.3370720380
Short name T466
Test name
Test status
Simulation time 65223062 ps
CPU time 1.01 seconds
Started Sep 27 01:03:00 PM PDT 23
Finished Sep 27 01:03:01 PM PDT 23
Peak memory 204960 kb
Host smart-12a60e25-5a81-49ae-b5d0-29f3791227f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370720380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3370720380
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_err.2101625614
Short name T35
Test name
Test status
Simulation time 24081444 ps
CPU time 0.88 seconds
Started Sep 27 01:02:10 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 215988 kb
Host smart-c456d015-8ea9-4fc8-813f-1b328c7172b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101625614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2101625614
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.1394382208
Short name T603
Test name
Test status
Simulation time 47458279 ps
CPU time 0.86 seconds
Started Sep 27 01:02:57 PM PDT 23
Finished Sep 27 01:02:58 PM PDT 23
Peak memory 214868 kb
Host smart-de2c7405-d3c2-4d61-8ddc-150fda07080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394382208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1394382208
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3281906425
Short name T519
Test name
Test status
Simulation time 71674458 ps
CPU time 0.81 seconds
Started Sep 27 01:04:20 PM PDT 23
Finished Sep 27 01:04:24 PM PDT 23
Peak memory 204844 kb
Host smart-b8c31a1e-5cc5-4f7f-9d9b-6af5eb1c29f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281906425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3281906425
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4157948863
Short name T312
Test name
Test status
Simulation time 147364021 ps
CPU time 3.4 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:32 PM PDT 23
Peak memory 206636 kb
Host smart-830ca8e2-8df4-4ff9-8f4f-4200af5789dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157948863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4157948863
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2114608866
Short name T443
Test name
Test status
Simulation time 135671996406 ps
CPU time 755.48 seconds
Started Sep 27 01:04:04 PM PDT 23
Finished Sep 27 01:16:40 PM PDT 23
Peak memory 215644 kb
Host smart-e65d4bd4-671a-411a-ba65-394607342de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114608866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2114608866
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.628543361
Short name T254
Test name
Test status
Simulation time 117764301 ps
CPU time 1 seconds
Started Sep 27 01:02:04 PM PDT 23
Finished Sep 27 01:02:05 PM PDT 23
Peak memory 205556 kb
Host smart-2b78ae58-584d-4a32-8074-5cfc90e6069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628543361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.628543361
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2549254930
Short name T509
Test name
Test status
Simulation time 16202935 ps
CPU time 0.89 seconds
Started Sep 27 01:04:09 PM PDT 23
Finished Sep 27 01:04:10 PM PDT 23
Peak memory 204936 kb
Host smart-f21403ae-7e96-4f3c-87d8-252822cc2898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549254930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2549254930
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3568729841
Short name T29
Test name
Test status
Simulation time 20110626 ps
CPU time 0.81 seconds
Started Sep 27 01:02:55 PM PDT 23
Finished Sep 27 01:02:56 PM PDT 23
Peak memory 214900 kb
Host smart-8dbd87eb-0204-4ca3-83d1-bc197c82c705
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568729841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3568729841
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.3516445221
Short name T648
Test name
Test status
Simulation time 28700383 ps
CPU time 1.13 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:29 PM PDT 23
Peak memory 217156 kb
Host smart-3ebcd538-25b9-42c0-a3b8-97c01590b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516445221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3516445221
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.127858072
Short name T38
Test name
Test status
Simulation time 19384243 ps
CPU time 1.18 seconds
Started Sep 27 01:03:57 PM PDT 23
Finished Sep 27 01:03:59 PM PDT 23
Peak memory 205872 kb
Host smart-92ac5361-6121-42e4-94f7-225eff5ce312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127858072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.127858072
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2928369933
Short name T503
Test name
Test status
Simulation time 29908233 ps
CPU time 0.93 seconds
Started Sep 27 01:04:53 PM PDT 23
Finished Sep 27 01:04:54 PM PDT 23
Peak memory 221720 kb
Host smart-3e3c273a-a8d8-4c51-93ec-bec90b2d897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928369933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2928369933
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4051408410
Short name T111
Test name
Test status
Simulation time 12934110 ps
CPU time 0.88 seconds
Started Sep 27 01:02:00 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 205072 kb
Host smart-cc3ab217-d8c1-4311-9af1-931ab0f44229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051408410 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4051408410
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2127108631
Short name T671
Test name
Test status
Simulation time 365596590 ps
CPU time 2.55 seconds
Started Sep 27 01:02:53 PM PDT 23
Finished Sep 27 01:02:55 PM PDT 23
Peak memory 206300 kb
Host smart-33df3410-fc40-42fd-b39a-65ee493a852c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127108631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2127108631
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.232535419
Short name T507
Test name
Test status
Simulation time 61709731374 ps
CPU time 376.1 seconds
Started Sep 27 01:01:58 PM PDT 23
Finished Sep 27 01:08:14 PM PDT 23
Peak memory 215852 kb
Host smart-ee5189f8-9e3c-4bad-9552-cdc68e56625d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232535419 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.232535419
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1511421871
Short name T557
Test name
Test status
Simulation time 55679276 ps
CPU time 0.89 seconds
Started Sep 27 01:03:12 PM PDT 23
Finished Sep 27 01:03:14 PM PDT 23
Peak memory 206544 kb
Host smart-25c202e1-5b93-4b7e-890b-1a10851973b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511421871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1511421871
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2495689715
Short name T536
Test name
Test status
Simulation time 21196220 ps
CPU time 0.79 seconds
Started Sep 27 01:03:26 PM PDT 23
Finished Sep 27 01:03:27 PM PDT 23
Peak memory 205540 kb
Host smart-7665c2a7-1f67-49c4-8514-ede08e489385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495689715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2495689715
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1872402488
Short name T84
Test name
Test status
Simulation time 19761353 ps
CPU time 0.89 seconds
Started Sep 27 01:02:22 PM PDT 23
Finished Sep 27 01:02:23 PM PDT 23
Peak memory 214776 kb
Host smart-db7a181b-29b4-41ab-863c-b6de46aff43f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872402488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1872402488
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2339082952
Short name T281
Test name
Test status
Simulation time 283001837 ps
CPU time 1 seconds
Started Sep 27 01:01:32 PM PDT 23
Finished Sep 27 01:01:33 PM PDT 23
Peak memory 215136 kb
Host smart-f39702a8-d702-4782-9399-5850fa38329f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339082952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2339082952
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3668955906
Short name T21
Test name
Test status
Simulation time 70176643 ps
CPU time 1.01 seconds
Started Sep 27 01:02:31 PM PDT 23
Finished Sep 27 01:02:33 PM PDT 23
Peak memory 217468 kb
Host smart-69199236-be14-4a07-a22c-dbcc5f751f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668955906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3668955906
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.490714576
Short name T43
Test name
Test status
Simulation time 46072494 ps
CPU time 1.19 seconds
Started Sep 27 01:02:08 PM PDT 23
Finished Sep 27 01:02:10 PM PDT 23
Peak memory 205692 kb
Host smart-1e8b5454-a179-4d7c-9dac-a82af1ad88be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490714576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.490714576
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1379194127
Short name T657
Test name
Test status
Simulation time 17814698 ps
CPU time 0.97 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:29 PM PDT 23
Peak memory 215040 kb
Host smart-ce46ad4a-d485-48d0-9b80-bbacbf7abf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379194127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1379194127
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1859060311
Short name T554
Test name
Test status
Simulation time 61294880 ps
CPU time 0.85 seconds
Started Sep 27 01:01:32 PM PDT 23
Finished Sep 27 01:01:33 PM PDT 23
Peak memory 205264 kb
Host smart-ee77ebec-e528-4f6e-b189-f31af1a3f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859060311 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1859060311
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.968494276
Short name T457
Test name
Test status
Simulation time 68075772 ps
CPU time 1.74 seconds
Started Sep 27 01:04:09 PM PDT 23
Finished Sep 27 01:04:11 PM PDT 23
Peak memory 205928 kb
Host smart-1f30f906-75a7-4393-84ec-e5d3e2119df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968494276 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.968494276
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.111214893
Short name T280
Test name
Test status
Simulation time 58211101043 ps
CPU time 1131.87 seconds
Started Sep 27 01:03:28 PM PDT 23
Finished Sep 27 01:22:20 PM PDT 23
Peak memory 217008 kb
Host smart-eaa4348c-b33a-4935-bd3d-3239fde8d1c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111214893 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.111214893
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3461198360
Short name T475
Test name
Test status
Simulation time 37044619 ps
CPU time 0.99 seconds
Started Sep 27 01:01:27 PM PDT 23
Finished Sep 27 01:01:28 PM PDT 23
Peak memory 205432 kb
Host smart-33e392ff-c0ce-43af-a44d-e4feec8201ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461198360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3461198360
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2304258481
Short name T470
Test name
Test status
Simulation time 21410165 ps
CPU time 0.98 seconds
Started Sep 27 01:02:35 PM PDT 23
Finished Sep 27 01:02:36 PM PDT 23
Peak memory 205000 kb
Host smart-a6fec4fc-b75d-412c-aee7-9b5aa58113b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304258481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2304258481
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1443953917
Short name T170
Test name
Test status
Simulation time 37407489 ps
CPU time 0.77 seconds
Started Sep 27 01:03:00 PM PDT 23
Finished Sep 27 01:03:01 PM PDT 23
Peak memory 214876 kb
Host smart-b45126e7-6a5b-41f6-b861-5ab69af16daf
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443953917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1443953917
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_intr.148280246
Short name T98
Test name
Test status
Simulation time 35397296 ps
CPU time 0.87 seconds
Started Sep 27 01:03:16 PM PDT 23
Finished Sep 27 01:03:18 PM PDT 23
Peak memory 214812 kb
Host smart-e2113fa6-c58f-4072-a3ea-ab0d28241c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148280246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.148280246
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3780887578
Short name T64
Test name
Test status
Simulation time 27278226 ps
CPU time 0.92 seconds
Started Sep 27 01:04:08 PM PDT 23
Finished Sep 27 01:04:10 PM PDT 23
Peak memory 204136 kb
Host smart-abec3849-f45d-4f84-9bb3-8a90b51a18d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780887578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3780887578
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2887602345
Short name T658
Test name
Test status
Simulation time 89666884 ps
CPU time 2.25 seconds
Started Sep 27 01:02:40 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 206464 kb
Host smart-2172e8b1-a6f9-43f4-9247-6db80f09fa27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887602345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2887602345
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1737563332
Short name T606
Test name
Test status
Simulation time 72251982918 ps
CPU time 1115 seconds
Started Sep 27 01:02:57 PM PDT 23
Finished Sep 27 01:21:37 PM PDT 23
Peak memory 216248 kb
Host smart-990420e2-f1e2-44fb-b2ce-5dccd56c005c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737563332 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1737563332
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.509798201
Short name T624
Test name
Test status
Simulation time 28380858 ps
CPU time 0.96 seconds
Started Sep 27 01:01:29 PM PDT 23
Finished Sep 27 01:01:30 PM PDT 23
Peak memory 205516 kb
Host smart-17ecb125-05aa-49c2-9958-b94e3e781f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509798201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.509798201
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2602606936
Short name T316
Test name
Test status
Simulation time 16636492 ps
CPU time 0.85 seconds
Started Sep 27 01:04:41 PM PDT 23
Finished Sep 27 01:04:42 PM PDT 23
Peak memory 205564 kb
Host smart-92816d39-fa97-4293-a84d-ac17f2f8a434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602606936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2602606936
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_err.1025988383
Short name T135
Test name
Test status
Simulation time 19575348 ps
CPU time 1.06 seconds
Started Sep 27 01:02:06 PM PDT 23
Finished Sep 27 01:02:07 PM PDT 23
Peak memory 215008 kb
Host smart-a102c12e-5810-4c44-a36b-02a8f4aed4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025988383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1025988383
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3514592590
Short name T12
Test name
Test status
Simulation time 30502425 ps
CPU time 0.97 seconds
Started Sep 27 01:02:55 PM PDT 23
Finished Sep 27 01:02:56 PM PDT 23
Peak memory 205504 kb
Host smart-cc181ce9-3bcc-4019-bb23-4d11031aea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514592590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3514592590
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.957771603
Short name T115
Test name
Test status
Simulation time 19928184 ps
CPU time 0.94 seconds
Started Sep 27 01:03:18 PM PDT 23
Finished Sep 27 01:03:19 PM PDT 23
Peak memory 215096 kb
Host smart-4188feef-ec2d-4433-bac3-d66391ad82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957771603 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.957771603
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.20256129
Short name T608
Test name
Test status
Simulation time 33178537 ps
CPU time 0.85 seconds
Started Sep 27 01:01:28 PM PDT 23
Finished Sep 27 01:01:29 PM PDT 23
Peak memory 205020 kb
Host smart-763a3113-e7d4-40cc-bb7d-07cbf0d8c5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20256129 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.20256129
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.65166602
Short name T37
Test name
Test status
Simulation time 133935728 ps
CPU time 3.08 seconds
Started Sep 27 01:01:30 PM PDT 23
Finished Sep 27 01:01:33 PM PDT 23
Peak memory 206372 kb
Host smart-71437934-95ef-4b98-a109-cd9dbe7889c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65166602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.65166602
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2382368688
Short name T446
Test name
Test status
Simulation time 22007949105 ps
CPU time 542.85 seconds
Started Sep 27 01:02:08 PM PDT 23
Finished Sep 27 01:11:11 PM PDT 23
Peak memory 215692 kb
Host smart-e420e8a0-894b-4336-9b80-0464a9447123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382368688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2382368688
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.4197790743
Short name T200
Test name
Test status
Simulation time 61610166 ps
CPU time 0.93 seconds
Started Sep 27 01:01:58 PM PDT 23
Finished Sep 27 01:01:59 PM PDT 23
Peak memory 206452 kb
Host smart-4625aed2-c1ae-4926-a245-dbd9015153d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197790743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4197790743
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1141406431
Short name T538
Test name
Test status
Simulation time 15375896 ps
CPU time 0.83 seconds
Started Sep 27 01:05:27 PM PDT 23
Finished Sep 27 01:05:28 PM PDT 23
Peak memory 204964 kb
Host smart-118e6e57-3061-42d1-a9cb-1358227328b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141406431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1141406431
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2257921763
Short name T564
Test name
Test status
Simulation time 16613346 ps
CPU time 0.81 seconds
Started Sep 27 01:07:17 PM PDT 23
Finished Sep 27 01:07:18 PM PDT 23
Peak memory 214792 kb
Host smart-f46d9657-e056-446d-95e8-c97744153903
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257921763 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2257921763
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1943327928
Short name T142
Test name
Test status
Simulation time 40640356 ps
CPU time 1.21 seconds
Started Sep 27 01:01:32 PM PDT 23
Finished Sep 27 01:01:34 PM PDT 23
Peak memory 230616 kb
Host smart-fdaa0290-95b8-4cbd-b918-58f709a15797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943327928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1943327928
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3263286627
Short name T203
Test name
Test status
Simulation time 114017955 ps
CPU time 0.89 seconds
Started Sep 27 01:02:15 PM PDT 23
Finished Sep 27 01:02:17 PM PDT 23
Peak memory 205160 kb
Host smart-c782b692-bcc0-4081-9602-1705f7648632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263286627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3263286627
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3715354165
Short name T622
Test name
Test status
Simulation time 21024572 ps
CPU time 1.03 seconds
Started Sep 27 01:04:48 PM PDT 23
Finished Sep 27 01:04:49 PM PDT 23
Peak memory 214996 kb
Host smart-2ddc167b-f8a0-4717-b6d5-068ac3fbda29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715354165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3715354165
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1706561260
Short name T655
Test name
Test status
Simulation time 43159563 ps
CPU time 0.86 seconds
Started Sep 27 01:02:32 PM PDT 23
Finished Sep 27 01:02:33 PM PDT 23
Peak memory 205224 kb
Host smart-7dec8c97-2368-4177-9427-bb5287e07779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706561260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1706561260
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.741120321
Short name T535
Test name
Test status
Simulation time 353923970 ps
CPU time 2.13 seconds
Started Sep 27 01:01:39 PM PDT 23
Finished Sep 27 01:01:41 PM PDT 23
Peak memory 206036 kb
Host smart-946c4ff1-4924-480b-b23a-918cf965ccf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741120321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.741120321
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1554179769
Short name T260
Test name
Test status
Simulation time 41396926453 ps
CPU time 1001.94 seconds
Started Sep 27 01:13:58 PM PDT 23
Finished Sep 27 01:30:41 PM PDT 23
Peak memory 215040 kb
Host smart-0e458fef-cb90-4de0-9638-9df8e0d4dfa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554179769 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1554179769
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1214306524
Short name T531
Test name
Test status
Simulation time 66249787 ps
CPU time 1 seconds
Started Sep 27 01:04:21 PM PDT 23
Finished Sep 27 01:04:23 PM PDT 23
Peak memory 204592 kb
Host smart-2659fc3c-e8ca-4e8a-99d3-b5abec58d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214306524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1214306524
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.958910277
Short name T455
Test name
Test status
Simulation time 122161842 ps
CPU time 0.93 seconds
Started Sep 27 01:02:39 PM PDT 23
Finished Sep 27 01:02:40 PM PDT 23
Peak memory 205824 kb
Host smart-188afae0-5700-4191-88d4-30d24603afcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958910277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.958910277
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2160452441
Short name T630
Test name
Test status
Simulation time 12691098 ps
CPU time 0.86 seconds
Started Sep 27 01:03:58 PM PDT 23
Finished Sep 27 01:03:59 PM PDT 23
Peak memory 214932 kb
Host smart-3b5a7bad-9989-4f50-8424-c234b9af051d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160452441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2160452441
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.3418939234
Short name T129
Test name
Test status
Simulation time 25567634 ps
CPU time 1.3 seconds
Started Sep 27 01:04:44 PM PDT 23
Finished Sep 27 01:04:46 PM PDT 23
Peak memory 215020 kb
Host smart-571df6bd-0fcf-4cbd-bf3e-b43b41907a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418939234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3418939234
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_intr.3059319435
Short name T52
Test name
Test status
Simulation time 24001998 ps
CPU time 1.05 seconds
Started Sep 27 01:04:59 PM PDT 23
Finished Sep 27 01:05:00 PM PDT 23
Peak memory 214804 kb
Host smart-456c4092-58e0-4e46-87b6-51f5d3656875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059319435 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3059319435
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1956374874
Short name T654
Test name
Test status
Simulation time 13071029 ps
CPU time 0.84 seconds
Started Sep 27 01:08:26 PM PDT 23
Finished Sep 27 01:08:27 PM PDT 23
Peak memory 205148 kb
Host smart-1e733bbc-fc32-4497-8594-c26924376902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956374874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1956374874
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.956436004
Short name T625
Test name
Test status
Simulation time 116636271 ps
CPU time 2.74 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:31 PM PDT 23
Peak memory 206188 kb
Host smart-8f4db354-da2e-410b-903e-e608fb368417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956436004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.956436004
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1574346926
Short name T560
Test name
Test status
Simulation time 54556078465 ps
CPU time 312.46 seconds
Started Sep 27 01:03:51 PM PDT 23
Finished Sep 27 01:09:03 PM PDT 23
Peak memory 215888 kb
Host smart-c0a66223-c645-4ee9-80ac-be435264b193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574346926 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1574346926
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2672379542
Short name T542
Test name
Test status
Simulation time 177568641 ps
CPU time 0.98 seconds
Started Sep 27 01:03:32 PM PDT 23
Finished Sep 27 01:03:33 PM PDT 23
Peak memory 205648 kb
Host smart-437c63f9-82a7-45e6-b741-4b65b1ed05c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672379542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2672379542
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3136828221
Short name T85
Test name
Test status
Simulation time 18638359 ps
CPU time 0.91 seconds
Started Sep 27 01:03:25 PM PDT 23
Finished Sep 27 01:03:26 PM PDT 23
Peak memory 205512 kb
Host smart-4d8b02b1-5bbf-446a-bb5a-d532b718894a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136828221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3136828221
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_err.943671207
Short name T145
Test name
Test status
Simulation time 33710228 ps
CPU time 1 seconds
Started Sep 27 01:04:13 PM PDT 23
Finished Sep 27 01:04:14 PM PDT 23
Peak memory 214924 kb
Host smart-5a1ac3f4-28fe-403d-b7ef-d17eb1f2a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943671207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.943671207
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2454099215
Short name T518
Test name
Test status
Simulation time 27704023 ps
CPU time 0.91 seconds
Started Sep 27 01:03:38 PM PDT 23
Finished Sep 27 01:03:39 PM PDT 23
Peak memory 205412 kb
Host smart-04890a1c-3c8c-471f-85ae-a96811d878c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454099215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2454099215
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1915411828
Short name T117
Test name
Test status
Simulation time 57069789 ps
CPU time 0.92 seconds
Started Sep 27 01:02:18 PM PDT 23
Finished Sep 27 01:02:19 PM PDT 23
Peak memory 225128 kb
Host smart-cccd00f2-8580-4746-aabf-90f5a61cb003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915411828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1915411828
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1897097508
Short name T637
Test name
Test status
Simulation time 16949590 ps
CPU time 0.78 seconds
Started Sep 27 01:04:34 PM PDT 23
Finished Sep 27 01:04:35 PM PDT 23
Peak memory 205096 kb
Host smart-cd230562-b3d5-4f31-b25d-accbfe062738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897097508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1897097508
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1476830389
Short name T570
Test name
Test status
Simulation time 310245166 ps
CPU time 1.95 seconds
Started Sep 27 01:04:32 PM PDT 23
Finished Sep 27 01:04:34 PM PDT 23
Peak memory 205668 kb
Host smart-dd96262b-0691-46be-a2f1-1515f73a352e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476830389 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1476830389
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3854031350
Short name T450
Test name
Test status
Simulation time 125917308171 ps
CPU time 860.18 seconds
Started Sep 27 01:04:54 PM PDT 23
Finished Sep 27 01:19:15 PM PDT 23
Peak memory 217232 kb
Host smart-cd7f8367-b72e-46e9-839d-6c47eeaf5c75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854031350 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3854031350
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3696667024
Short name T124
Test name
Test status
Simulation time 31615953 ps
CPU time 0.94 seconds
Started Sep 27 01:01:26 PM PDT 23
Finished Sep 27 01:01:27 PM PDT 23
Peak memory 205576 kb
Host smart-d3145269-1b3d-479a-b473-d8bd685955fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696667024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3696667024
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2963427252
Short name T322
Test name
Test status
Simulation time 66052019 ps
CPU time 0.91 seconds
Started Sep 27 01:04:09 PM PDT 23
Finished Sep 27 01:04:10 PM PDT 23
Peak memory 205752 kb
Host smart-b824d7a0-2a36-498d-ac57-fced24a3dd8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963427252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2963427252
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_err.2390940250
Short name T157
Test name
Test status
Simulation time 37949683 ps
CPU time 0.78 seconds
Started Sep 27 01:03:55 PM PDT 23
Finished Sep 27 01:03:56 PM PDT 23
Peak memory 215484 kb
Host smart-4423519e-aaf1-4700-9893-1697cd7e219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390940250 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2390940250
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3039501591
Short name T476
Test name
Test status
Simulation time 56191582 ps
CPU time 0.9 seconds
Started Sep 27 01:04:43 PM PDT 23
Finished Sep 27 01:04:44 PM PDT 23
Peak memory 205280 kb
Host smart-64ee7e30-df30-48a8-99cd-c52a2aea7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039501591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3039501591
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.185933622
Short name T107
Test name
Test status
Simulation time 21503249 ps
CPU time 0.93 seconds
Started Sep 27 01:01:57 PM PDT 23
Finished Sep 27 01:01:58 PM PDT 23
Peak memory 215180 kb
Host smart-1651196b-a7c6-4853-9757-aa04563c7a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185933622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.185933622
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.728887426
Short name T590
Test name
Test status
Simulation time 27228289 ps
CPU time 0.77 seconds
Started Sep 27 01:04:33 PM PDT 23
Finished Sep 27 01:04:34 PM PDT 23
Peak memory 205092 kb
Host smart-4c3e8c6c-38e4-4ac2-83c6-26ab34871aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728887426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.728887426
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1473786921
Short name T433
Test name
Test status
Simulation time 107492851 ps
CPU time 2.41 seconds
Started Sep 27 01:02:34 PM PDT 23
Finished Sep 27 01:02:36 PM PDT 23
Peak memory 206156 kb
Host smart-7ada21f3-ad24-43f7-b861-1c18b90f2881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473786921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1473786921
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3872910263
Short name T537
Test name
Test status
Simulation time 117456966356 ps
CPU time 701.62 seconds
Started Sep 27 01:03:37 PM PDT 23
Finished Sep 27 01:15:19 PM PDT 23
Peak memory 216236 kb
Host smart-683b6043-615f-41d6-a1f6-a448326b0822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872910263 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3872910263
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.946678005
Short name T628
Test name
Test status
Simulation time 18092781 ps
CPU time 0.91 seconds
Started Sep 27 01:01:31 PM PDT 23
Finished Sep 27 01:01:33 PM PDT 23
Peak memory 205564 kb
Host smart-37c9d67a-3ba7-416e-83c1-99a397e140ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946678005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.946678005
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3187138153
Short name T473
Test name
Test status
Simulation time 57736815 ps
CPU time 0.85 seconds
Started Sep 27 01:03:42 PM PDT 23
Finished Sep 27 01:03:43 PM PDT 23
Peak memory 204932 kb
Host smart-fbfa0909-6061-4f04-ad61-e9f2f070eb75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187138153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3187138153
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3517910264
Short name T156
Test name
Test status
Simulation time 17778429 ps
CPU time 0.9 seconds
Started Sep 27 01:03:55 PM PDT 23
Finished Sep 27 01:03:56 PM PDT 23
Peak memory 215032 kb
Host smart-eeecdeeb-1c33-4681-ba5b-5135e19638b5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517910264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3517910264
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.1569334152
Short name T154
Test name
Test status
Simulation time 20373151 ps
CPU time 0.87 seconds
Started Sep 27 01:03:01 PM PDT 23
Finished Sep 27 01:03:02 PM PDT 23
Peak memory 215920 kb
Host smart-2a365b97-cde6-426d-b12d-7dc59912a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569334152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1569334152
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4062758204
Short name T291
Test name
Test status
Simulation time 97336002 ps
CPU time 0.94 seconds
Started Sep 27 01:03:41 PM PDT 23
Finished Sep 27 01:03:42 PM PDT 23
Peak memory 205508 kb
Host smart-beeb1622-94ff-443f-8eeb-46ebacbc6d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062758204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4062758204
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2012626306
Short name T66
Test name
Test status
Simulation time 39265661 ps
CPU time 0.82 seconds
Started Sep 27 01:03:06 PM PDT 23
Finished Sep 27 01:03:08 PM PDT 23
Peak memory 214772 kb
Host smart-5ee6c47e-ab2e-4920-a0da-79e3c4c1cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012626306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2012626306
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2651065148
Short name T609
Test name
Test status
Simulation time 14920133 ps
CPU time 0.87 seconds
Started Sep 27 01:03:01 PM PDT 23
Finished Sep 27 01:03:04 PM PDT 23
Peak memory 205032 kb
Host smart-78bf899e-3d41-4798-a550-1114f5521763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651065148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2651065148
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.722104375
Short name T499
Test name
Test status
Simulation time 149289558 ps
CPU time 1.28 seconds
Started Sep 27 01:01:31 PM PDT 23
Finished Sep 27 01:01:32 PM PDT 23
Peak memory 205052 kb
Host smart-70948bce-b29d-453e-a088-853dd37a2dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722104375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.722104375
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2746916573
Short name T565
Test name
Test status
Simulation time 138480007366 ps
CPU time 1664.98 seconds
Started Sep 27 01:03:03 PM PDT 23
Finished Sep 27 01:30:49 PM PDT 23
Peak memory 218852 kb
Host smart-04ebb8d0-909f-4198-8462-c2ba7a15f5a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746916573 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2746916573
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.879467911
Short name T72
Test name
Test status
Simulation time 33977987 ps
CPU time 0.92 seconds
Started Sep 27 01:00:28 PM PDT 23
Finished Sep 27 01:00:30 PM PDT 23
Peak memory 205548 kb
Host smart-2de16b04-1eb0-4eac-9176-376cb8f4b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879467911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.879467911
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2544313303
Short name T559
Test name
Test status
Simulation time 49162362 ps
CPU time 0.82 seconds
Started Sep 27 01:01:01 PM PDT 23
Finished Sep 27 01:01:02 PM PDT 23
Peak memory 205004 kb
Host smart-3bfe09c5-8c1f-41ef-95f9-9251a1202226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544313303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2544313303
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1392287587
Short name T676
Test name
Test status
Simulation time 92464459 ps
CPU time 0.77 seconds
Started Sep 27 01:09:19 PM PDT 23
Finished Sep 27 01:09:20 PM PDT 23
Peak memory 214768 kb
Host smart-58fe6a20-27fa-4771-b701-92e6c558f502
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392287587 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1392287587
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.2364338593
Short name T311
Test name
Test status
Simulation time 26054806 ps
CPU time 0.91 seconds
Started Sep 27 01:01:49 PM PDT 23
Finished Sep 27 01:01:50 PM PDT 23
Peak memory 216192 kb
Host smart-d34d8d5c-c4da-4ed9-b480-44687b3c8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364338593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2364338593
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3970108823
Short name T102
Test name
Test status
Simulation time 21926451 ps
CPU time 0.99 seconds
Started Sep 27 01:03:03 PM PDT 23
Finished Sep 27 01:03:04 PM PDT 23
Peak memory 205708 kb
Host smart-08d1f6ca-e3b6-4b10-8d0c-5342659767f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970108823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3970108823
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.4182118417
Short name T293
Test name
Test status
Simulation time 152847357 ps
CPU time 0.76 seconds
Started Sep 27 01:14:07 PM PDT 23
Finished Sep 27 01:14:09 PM PDT 23
Peak memory 205036 kb
Host smart-d363b1a1-c5d7-4ab4-88dd-dddd913ece4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182118417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4182118417
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.604472993
Short name T462
Test name
Test status
Simulation time 25172972 ps
CPU time 0.85 seconds
Started Sep 27 01:00:30 PM PDT 23
Finished Sep 27 01:00:31 PM PDT 23
Peak memory 205220 kb
Host smart-d88408b4-cf3c-41f9-b774-18029b920171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604472993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.604472993
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.853243398
Short name T523
Test name
Test status
Simulation time 280430162 ps
CPU time 3.32 seconds
Started Sep 27 01:01:36 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 206276 kb
Host smart-3212f77f-73a3-41fd-867c-3c051855d543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853243398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.853243398
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2875704781
Short name T123
Test name
Test status
Simulation time 56545271202 ps
CPU time 1374.68 seconds
Started Sep 27 01:02:21 PM PDT 23
Finished Sep 27 01:25:16 PM PDT 23
Peak memory 217256 kb
Host smart-cdf5fbc4-f8ec-428d-8562-ffef01c8413f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875704781 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2875704781
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1870695172
Short name T449
Test name
Test status
Simulation time 19315907 ps
CPU time 1.19 seconds
Started Sep 27 01:01:33 PM PDT 23
Finished Sep 27 01:01:34 PM PDT 23
Peak memory 221896 kb
Host smart-bc2a6899-78c6-4d1f-b925-6a15d2adfcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870695172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1870695172
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.357296530
Short name T500
Test name
Test status
Simulation time 28549010 ps
CPU time 1.09 seconds
Started Sep 27 01:03:48 PM PDT 23
Finished Sep 27 01:03:50 PM PDT 23
Peak memory 217080 kb
Host smart-8e393621-19cf-423a-b3b1-474804d9c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357296530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.357296530
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.3337742195
Short name T112
Test name
Test status
Simulation time 31050816 ps
CPU time 1.19 seconds
Started Sep 27 01:01:33 PM PDT 23
Finished Sep 27 01:01:35 PM PDT 23
Peak memory 217232 kb
Host smart-f998a301-2c11-4dba-b1ef-a2e1f4677ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337742195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3337742195
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.4105686795
Short name T7
Test name
Test status
Simulation time 20102901 ps
CPU time 1.12 seconds
Started Sep 27 01:03:59 PM PDT 23
Finished Sep 27 01:04:00 PM PDT 23
Peak memory 228936 kb
Host smart-0f96b56e-d3c0-457a-8a36-affcc00ccd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105686795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4105686795
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.2647748847
Short name T57
Test name
Test status
Simulation time 144334359 ps
CPU time 0.95 seconds
Started Sep 27 01:03:17 PM PDT 23
Finished Sep 27 01:03:24 PM PDT 23
Peak memory 214936 kb
Host smart-0b087eb5-b127-4e5b-ae5a-e307f90ff7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647748847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2647748847
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.156957259
Short name T441
Test name
Test status
Simulation time 32636279 ps
CPU time 0.81 seconds
Started Sep 27 01:02:59 PM PDT 23
Finished Sep 27 01:03:00 PM PDT 23
Peak memory 216024 kb
Host smart-ae1240b3-2acd-4bf4-8f1b-7d963b71cd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156957259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.156957259
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.2234117833
Short name T50
Test name
Test status
Simulation time 24348813 ps
CPU time 0.82 seconds
Started Sep 27 01:02:22 PM PDT 23
Finished Sep 27 01:02:23 PM PDT 23
Peak memory 215976 kb
Host smart-9f5482e6-71ed-4de2-b4b9-eee41274fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234117833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2234117833
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.3099040748
Short name T5
Test name
Test status
Simulation time 24935035 ps
CPU time 0.95 seconds
Started Sep 27 01:01:38 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 215888 kb
Host smart-e95c28b5-e342-4bb2-a8c2-eb2cf16f20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099040748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3099040748
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.2169828821
Short name T453
Test name
Test status
Simulation time 18682814 ps
CPU time 1.2 seconds
Started Sep 27 01:01:34 PM PDT 23
Finished Sep 27 01:01:35 PM PDT 23
Peak memory 215028 kb
Host smart-bc1e981b-3487-473a-a2e6-940eb8d4f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169828821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2169828821
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.391289774
Short name T47
Test name
Test status
Simulation time 53956729 ps
CPU time 0.95 seconds
Started Sep 27 01:03:24 PM PDT 23
Finished Sep 27 01:03:25 PM PDT 23
Peak memory 221504 kb
Host smart-966d0235-9b1f-4a1a-9809-f34129b96066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391289774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.391289774
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.1350915958
Short name T253
Test name
Test status
Simulation time 18429173 ps
CPU time 0.96 seconds
Started Sep 27 01:02:21 PM PDT 23
Finished Sep 27 01:02:22 PM PDT 23
Peak memory 205552 kb
Host smart-c29241f8-4304-44d2-baff-d0821146ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350915958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1350915958
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3235236198
Short name T192
Test name
Test status
Simulation time 15440016 ps
CPU time 0.92 seconds
Started Sep 27 01:02:01 PM PDT 23
Finished Sep 27 01:02:03 PM PDT 23
Peak memory 204980 kb
Host smart-0ce2ee07-6f9c-493e-901a-cae94a4b0cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235236198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3235236198
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.48952922
Short name T76
Test name
Test status
Simulation time 18645166 ps
CPU time 0.84 seconds
Started Sep 27 01:02:41 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 214828 kb
Host smart-3053560a-446b-4f4e-b5d2-14c7c2bd549e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48952922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.48952922
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.1371301762
Short name T15
Test name
Test status
Simulation time 32480461 ps
CPU time 0.92 seconds
Started Sep 27 01:05:12 PM PDT 23
Finished Sep 27 01:05:13 PM PDT 23
Peak memory 221476 kb
Host smart-1c236273-aebb-4a75-928b-ba3fa530e8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371301762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1371301762
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1232301098
Short name T20
Test name
Test status
Simulation time 45047996 ps
CPU time 0.85 seconds
Started Sep 27 01:22:09 PM PDT 23
Finished Sep 27 01:22:10 PM PDT 23
Peak memory 205492 kb
Host smart-82ae4151-3d92-4af1-97a5-e74694f31b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232301098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1232301098
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1403930059
Short name T437
Test name
Test status
Simulation time 21362147 ps
CPU time 1 seconds
Started Sep 27 01:02:44 PM PDT 23
Finished Sep 27 01:02:45 PM PDT 23
Peak memory 214948 kb
Host smart-5bab7776-3c1b-40f1-bf24-c3c257c91cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403930059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1403930059
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1434190801
Short name T297
Test name
Test status
Simulation time 42830225 ps
CPU time 0.83 seconds
Started Sep 27 01:01:12 PM PDT 23
Finished Sep 27 01:01:13 PM PDT 23
Peak memory 205184 kb
Host smart-5e4c7074-c91f-47ff-8dc5-a43743b1de1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434190801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1434190801
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.49950764
Short name T201
Test name
Test status
Simulation time 56183941 ps
CPU time 0.87 seconds
Started Sep 27 01:02:28 PM PDT 23
Finished Sep 27 01:02:29 PM PDT 23
Peak memory 205096 kb
Host smart-362501d3-9f8d-45d3-ae36-873859aabffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49950764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.49950764
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1108121321
Short name T511
Test name
Test status
Simulation time 388416052 ps
CPU time 2.57 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:48 PM PDT 23
Peak memory 206320 kb
Host smart-ca6890f0-489d-4974-8453-65f81a8a5ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108121321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1108121321
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_err.3500440867
Short name T527
Test name
Test status
Simulation time 28757404 ps
CPU time 0.79 seconds
Started Sep 27 01:02:07 PM PDT 23
Finished Sep 27 01:02:08 PM PDT 23
Peak memory 215808 kb
Host smart-4f205896-6f05-4dba-919b-1daac173018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500440867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3500440867
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.1020301317
Short name T434
Test name
Test status
Simulation time 21885301 ps
CPU time 0.92 seconds
Started Sep 27 01:01:38 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 216000 kb
Host smart-da4cb7c2-332b-4db1-8360-4b09accb65d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020301317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1020301317
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.1020375773
Short name T134
Test name
Test status
Simulation time 46204606 ps
CPU time 0.93 seconds
Started Sep 27 01:03:20 PM PDT 23
Finished Sep 27 01:03:21 PM PDT 23
Peak memory 216204 kb
Host smart-2393726b-a22f-4d36-bbae-fbfb36550f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020375773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1020375773
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.3857232807
Short name T9
Test name
Test status
Simulation time 23398194 ps
CPU time 1.17 seconds
Started Sep 27 01:02:55 PM PDT 23
Finished Sep 27 01:02:56 PM PDT 23
Peak memory 228884 kb
Host smart-0d5ff826-a18f-4233-9047-84d784880802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857232807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3857232807
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.1896076239
Short name T137
Test name
Test status
Simulation time 63648564 ps
CPU time 1.08 seconds
Started Sep 27 01:04:39 PM PDT 23
Finished Sep 27 01:04:41 PM PDT 23
Peak memory 220312 kb
Host smart-50a82b6c-eb0a-4d49-a388-9975fdb815bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896076239 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1896076239
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.862746503
Short name T321
Test name
Test status
Simulation time 21737027 ps
CPU time 1.09 seconds
Started Sep 27 01:01:40 PM PDT 23
Finished Sep 27 01:01:41 PM PDT 23
Peak memory 215028 kb
Host smart-8acb1991-62c7-4f21-88db-881bd455c9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862746503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.862746503
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.2659073836
Short name T540
Test name
Test status
Simulation time 29365803 ps
CPU time 1 seconds
Started Sep 27 01:04:28 PM PDT 23
Finished Sep 27 01:04:29 PM PDT 23
Peak memory 216160 kb
Host smart-691a4b11-e830-493e-be84-e00e4ae1580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659073836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2659073836
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.3659739189
Short name T468
Test name
Test status
Simulation time 44237316 ps
CPU time 1.19 seconds
Started Sep 27 01:01:39 PM PDT 23
Finished Sep 27 01:01:41 PM PDT 23
Peak memory 222396 kb
Host smart-9e8a6b76-e054-45bd-8c1f-d5cf00784e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659739189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3659739189
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.2908964245
Short name T153
Test name
Test status
Simulation time 22951258 ps
CPU time 0.91 seconds
Started Sep 27 01:03:41 PM PDT 23
Finished Sep 27 01:03:42 PM PDT 23
Peak memory 216200 kb
Host smart-6ef3b68c-25de-4954-b6e3-08a3617245d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908964245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2908964245
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.809159348
Short name T645
Test name
Test status
Simulation time 31380707 ps
CPU time 0.84 seconds
Started Sep 27 01:04:55 PM PDT 23
Finished Sep 27 01:04:58 PM PDT 23
Peak memory 215820 kb
Host smart-54fa8998-b898-4500-ba50-9ef202126a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809159348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.809159348
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.3443491710
Short name T493
Test name
Test status
Simulation time 19223870 ps
CPU time 1.02 seconds
Started Sep 27 01:00:32 PM PDT 23
Finished Sep 27 01:00:34 PM PDT 23
Peak memory 206536 kb
Host smart-3a6001f8-dac6-4f58-a623-a1f8fa8749da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443491710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3443491710
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1678452944
Short name T484
Test name
Test status
Simulation time 18923767 ps
CPU time 0.97 seconds
Started Sep 27 01:01:36 PM PDT 23
Finished Sep 27 01:01:37 PM PDT 23
Peak memory 205080 kb
Host smart-b0000c4a-b603-4e97-9208-1f44bc0db651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678452944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1678452944
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.173583406
Short name T165
Test name
Test status
Simulation time 13710470 ps
CPU time 0.92 seconds
Started Sep 27 01:15:37 PM PDT 23
Finished Sep 27 01:15:38 PM PDT 23
Peak memory 215024 kb
Host smart-abcc7f45-fc76-41bf-a24a-f6a99f2057d4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173583406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.173583406
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.2126437842
Short name T604
Test name
Test status
Simulation time 73337484 ps
CPU time 1.18 seconds
Started Sep 27 01:02:42 PM PDT 23
Finished Sep 27 01:02:43 PM PDT 23
Peak memory 222352 kb
Host smart-f93c094e-d36d-48ef-8ba1-321f23bab4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126437842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2126437842
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1074649283
Short name T286
Test name
Test status
Simulation time 32229853 ps
CPU time 0.97 seconds
Started Sep 27 01:02:33 PM PDT 23
Finished Sep 27 01:02:34 PM PDT 23
Peak memory 205820 kb
Host smart-82a7a875-8a08-429c-95da-988c5c459720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074649283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1074649283
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3658282651
Short name T113
Test name
Test status
Simulation time 25902335 ps
CPU time 1 seconds
Started Sep 27 01:02:05 PM PDT 23
Finished Sep 27 01:02:11 PM PDT 23
Peak memory 226008 kb
Host smart-739af01f-f757-449a-b5f7-577779f4a9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658282651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3658282651
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.3863046590
Short name T545
Test name
Test status
Simulation time 53372396 ps
CPU time 0.96 seconds
Started Sep 27 01:02:01 PM PDT 23
Finished Sep 27 01:02:02 PM PDT 23
Peak memory 205344 kb
Host smart-8e381960-9fd4-4926-a1ad-ad4450f32969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863046590 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3863046590
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.688338451
Short name T489
Test name
Test status
Simulation time 602702177 ps
CPU time 3.43 seconds
Started Sep 27 01:09:12 PM PDT 23
Finished Sep 27 01:09:16 PM PDT 23
Peak memory 206352 kb
Host smart-24deb599-d236-413c-84e9-a96d4f3ca8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688338451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.688338451
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2514012837
Short name T631
Test name
Test status
Simulation time 47703909674 ps
CPU time 1035.66 seconds
Started Sep 27 01:02:32 PM PDT 23
Finished Sep 27 01:19:48 PM PDT 23
Peak memory 215168 kb
Host smart-7ee8b819-7ab2-4492-b8ee-956f15c8d3ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514012837 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2514012837
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3666165960
Short name T155
Test name
Test status
Simulation time 31704807 ps
CPU time 0.82 seconds
Started Sep 27 01:03:44 PM PDT 23
Finished Sep 27 01:03:45 PM PDT 23
Peak memory 215728 kb
Host smart-e84ff276-7b12-4361-a7f7-7cf4fa84adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666165960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3666165960
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.770437696
Short name T258
Test name
Test status
Simulation time 25608104 ps
CPU time 1.33 seconds
Started Sep 27 01:03:22 PM PDT 23
Finished Sep 27 01:03:24 PM PDT 23
Peak memory 228064 kb
Host smart-e6b62165-814f-4942-bf5a-464655bedb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770437696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.770437696
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.4187736482
Short name T442
Test name
Test status
Simulation time 23073956 ps
CPU time 0.87 seconds
Started Sep 27 01:01:40 PM PDT 23
Finished Sep 27 01:01:41 PM PDT 23
Peak memory 216008 kb
Host smart-2da577ed-3000-439b-993a-5414657a3fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187736482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4187736482
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.1910478142
Short name T460
Test name
Test status
Simulation time 63377919 ps
CPU time 1.05 seconds
Started Sep 27 01:04:52 PM PDT 23
Finished Sep 27 01:04:53 PM PDT 23
Peak memory 228996 kb
Host smart-d8883c70-9f71-4d3b-8a95-9aa295b19fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910478142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1910478142
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.3498148842
Short name T686
Test name
Test status
Simulation time 25014257 ps
CPU time 0.89 seconds
Started Sep 27 01:03:00 PM PDT 23
Finished Sep 27 01:03:01 PM PDT 23
Peak memory 221708 kb
Host smart-e0d35bde-b6b7-45c5-b6f8-3d82d7a74b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498148842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3498148842
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.3160009515
Short name T177
Test name
Test status
Simulation time 25763827 ps
CPU time 1 seconds
Started Sep 27 01:04:55 PM PDT 23
Finished Sep 27 01:04:57 PM PDT 23
Peak memory 228748 kb
Host smart-0565c8f1-3f44-478f-b8f7-7fb63488bfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160009515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3160009515
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.4107740102
Short name T525
Test name
Test status
Simulation time 22283583 ps
CPU time 0.81 seconds
Started Sep 27 01:04:37 PM PDT 23
Finished Sep 27 01:04:38 PM PDT 23
Peak memory 214864 kb
Host smart-33d8c4b1-dad7-4a18-8808-e384a8281daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107740102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4107740102
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.649709853
Short name T116
Test name
Test status
Simulation time 32350215 ps
CPU time 0.92 seconds
Started Sep 27 01:04:18 PM PDT 23
Finished Sep 27 01:04:19 PM PDT 23
Peak memory 214832 kb
Host smart-b0f91edd-5697-4170-b5af-14412fdc0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649709853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.649709853
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.1914900586
Short name T310
Test name
Test status
Simulation time 18294625 ps
CPU time 1.3 seconds
Started Sep 27 01:01:37 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 216400 kb
Host smart-818d4114-4088-4e5e-936c-94b960b593c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914900586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1914900586
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.2530515957
Short name T512
Test name
Test status
Simulation time 119649113 ps
CPU time 0.99 seconds
Started Sep 27 01:00:25 PM PDT 23
Finished Sep 27 01:00:26 PM PDT 23
Peak memory 206476 kb
Host smart-d81ef44c-5710-47d6-8215-81ef047cacd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530515957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2530515957
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.523217071
Short name T486
Test name
Test status
Simulation time 53771050 ps
CPU time 0.85 seconds
Started Sep 27 01:02:27 PM PDT 23
Finished Sep 27 01:02:28 PM PDT 23
Peak memory 205852 kb
Host smart-09da1997-e8bb-48ef-b294-4fe800088714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523217071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.523217071
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3040498693
Short name T78
Test name
Test status
Simulation time 48356182 ps
CPU time 0.82 seconds
Started Sep 27 01:01:07 PM PDT 23
Finished Sep 27 01:01:09 PM PDT 23
Peak memory 214804 kb
Host smart-13bee57e-956b-4f01-a4b3-9ddca5e0936f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040498693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3040498693
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.3952060875
Short name T138
Test name
Test status
Simulation time 37656167 ps
CPU time 1.37 seconds
Started Sep 27 01:00:28 PM PDT 23
Finished Sep 27 01:00:30 PM PDT 23
Peak memory 228132 kb
Host smart-6bb365de-3683-40cd-987d-7c825e7044d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952060875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3952060875
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.546580958
Short name T70
Test name
Test status
Simulation time 62053238 ps
CPU time 1.16 seconds
Started Sep 27 01:03:15 PM PDT 23
Finished Sep 27 01:03:16 PM PDT 23
Peak memory 205520 kb
Host smart-99c5ea55-107c-41d2-b3ee-54324d473c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546580958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.546580958
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4120692224
Short name T644
Test name
Test status
Simulation time 29150620 ps
CPU time 0.83 seconds
Started Sep 27 01:02:45 PM PDT 23
Finished Sep 27 01:02:46 PM PDT 23
Peak memory 214892 kb
Host smart-f84abdeb-689b-40ed-a858-e6b386cd42cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120692224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4120692224
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2238482890
Short name T257
Test name
Test status
Simulation time 20476594 ps
CPU time 0.88 seconds
Started Sep 27 01:02:40 PM PDT 23
Finished Sep 27 01:02:42 PM PDT 23
Peak memory 205312 kb
Host smart-c8ce6898-1b5f-4cd7-bd44-ec1405d1de56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238482890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2238482890
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1727131487
Short name T480
Test name
Test status
Simulation time 13025219 ps
CPU time 0.91 seconds
Started Sep 27 01:02:38 PM PDT 23
Finished Sep 27 01:02:40 PM PDT 23
Peak memory 205136 kb
Host smart-d2f91757-b6c2-4601-b9ca-f31a5ac2fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727131487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1727131487
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3727721279
Short name T472
Test name
Test status
Simulation time 350410922 ps
CPU time 2.24 seconds
Started Sep 27 01:02:26 PM PDT 23
Finished Sep 27 01:02:29 PM PDT 23
Peak memory 206124 kb
Host smart-a1ce2544-e959-488c-b097-06303b87fc1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727721279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3727721279
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1974283597
Short name T614
Test name
Test status
Simulation time 48494181099 ps
CPU time 1228.26 seconds
Started Sep 27 01:01:17 PM PDT 23
Finished Sep 27 01:21:45 PM PDT 23
Peak memory 216328 kb
Host smart-10e2699e-544a-4219-a53b-c2c320bd54a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974283597 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1974283597
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3532291500
Short name T685
Test name
Test status
Simulation time 51000528 ps
CPU time 0.94 seconds
Started Sep 27 01:03:19 PM PDT 23
Finished Sep 27 01:03:20 PM PDT 23
Peak memory 216244 kb
Host smart-601d12b4-7660-497c-a48d-948544b9a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532291500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3532291500
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.935239751
Short name T45
Test name
Test status
Simulation time 19248201 ps
CPU time 1.39 seconds
Started Sep 27 01:01:37 PM PDT 23
Finished Sep 27 01:01:39 PM PDT 23
Peak memory 222304 kb
Host smart-46bc81a6-c315-455c-8b2b-57522ae8ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935239751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.935239751
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.3392120776
Short name T158
Test name
Test status
Simulation time 22933912 ps
CPU time 0.88 seconds
Started Sep 27 01:01:40 PM PDT 23
Finished Sep 27 01:01:41 PM PDT 23
Peak memory 215948 kb
Host smart-ca0007a5-a59d-4f9a-9997-e8d13831c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392120776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3392120776
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.1882336073
Short name T36
Test name
Test status
Simulation time 45035841 ps
CPU time 0.84 seconds
Started Sep 27 01:03:57 PM PDT 23
Finished Sep 27 01:03:58 PM PDT 23
Peak memory 216380 kb
Host smart-59c639dc-c535-46a1-a1cb-9a30ae2852e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882336073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1882336073
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.372044816
Short name T162
Test name
Test status
Simulation time 85820303 ps
CPU time 0.77 seconds
Started Sep 27 01:04:18 PM PDT 23
Finished Sep 27 01:04:19 PM PDT 23
Peak memory 215748 kb
Host smart-d955116c-86cb-4cb0-b7dd-247681df2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372044816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.372044816
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.191034546
Short name T626
Test name
Test status
Simulation time 40827352 ps
CPU time 0.94 seconds
Started Sep 27 01:02:44 PM PDT 23
Finished Sep 27 01:02:45 PM PDT 23
Peak memory 221928 kb
Host smart-eb2b9a29-9573-43df-87ba-6dd01b7a8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191034546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.191034546
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.95410458
Short name T244
Test name
Test status
Simulation time 20731851 ps
CPU time 1.01 seconds
Started Sep 27 01:04:30 PM PDT 23
Finished Sep 27 01:04:31 PM PDT 23
Peak memory 216136 kb
Host smart-d095306c-fc64-46fc-9be8-b0a83d757afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95410458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.95410458
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.3354685157
Short name T463
Test name
Test status
Simulation time 215329453 ps
CPU time 1.02 seconds
Started Sep 27 01:03:25 PM PDT 23
Finished Sep 27 01:03:26 PM PDT 23
Peak memory 216172 kb
Host smart-e033efec-3e75-481e-afaf-f1f3e8e37de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354685157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3354685157
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.1070324621
Short name T664
Test name
Test status
Simulation time 20395126 ps
CPU time 0.99 seconds
Started Sep 27 01:03:12 PM PDT 23
Finished Sep 27 01:03:13 PM PDT 23
Peak memory 215236 kb
Host smart-289406a3-9079-4a4e-9d6e-c4122ba88c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070324621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1070324621
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.456685996
Short name T659
Test name
Test status
Simulation time 19399347 ps
CPU time 1.36 seconds
Started Sep 27 01:02:16 PM PDT 23
Finished Sep 27 01:02:18 PM PDT 23
Peak memory 214928 kb
Host smart-f585d8f0-449c-4ed5-8fc4-f0de752079d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456685996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.456685996
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1102714638
Short name T89
Test name
Test status
Simulation time 17151448 ps
CPU time 0.97 seconds
Started Sep 27 01:01:47 PM PDT 23
Finished Sep 27 01:01:48 PM PDT 23
Peak memory 206408 kb
Host smart-2887d4eb-2adb-41cb-9362-26cbca881798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102714638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1102714638
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1195082397
Short name T93
Test name
Test status
Simulation time 19453291 ps
CPU time 0.99 seconds
Started Sep 27 01:00:28 PM PDT 23
Finished Sep 27 01:00:29 PM PDT 23
Peak memory 205656 kb
Host smart-dfc064f5-4d25-4996-a28f-a938f376d138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195082397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1195082397
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4221905038
Short name T169
Test name
Test status
Simulation time 13862206 ps
CPU time 0.85 seconds
Started Sep 27 01:02:13 PM PDT 23
Finished Sep 27 01:02:14 PM PDT 23
Peak memory 215024 kb
Host smart-cfd7a49b-5d52-4865-bd3e-dec4fa33d195
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221905038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4221905038
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.2559726208
Short name T61
Test name
Test status
Simulation time 25136979 ps
CPU time 1.14 seconds
Started Sep 27 01:04:06 PM PDT 23
Finished Sep 27 01:04:07 PM PDT 23
Peak memory 214828 kb
Host smart-a1e95d07-0520-469c-a10b-d92e9dadb52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559726208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2559726208
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2510597543
Short name T60
Test name
Test status
Simulation time 75417849 ps
CPU time 0.84 seconds
Started Sep 27 01:07:09 PM PDT 23
Finished Sep 27 01:07:10 PM PDT 23
Peak memory 205436 kb
Host smart-71db8400-6bc6-4069-981b-3f472a38ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510597543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2510597543
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.103651594
Short name T120
Test name
Test status
Simulation time 39409303 ps
CPU time 0.84 seconds
Started Sep 27 01:07:18 PM PDT 23
Finished Sep 27 01:07:20 PM PDT 23
Peak memory 214980 kb
Host smart-54b8d64e-2021-48f0-853e-1ce3bc1c791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103651594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.103651594
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.3650159274
Short name T553
Test name
Test status
Simulation time 12310664 ps
CPU time 0.85 seconds
Started Sep 27 01:15:40 PM PDT 23
Finished Sep 27 01:15:41 PM PDT 23
Peak memory 205232 kb
Host smart-f91f0931-04bc-407b-ad96-9982d1335d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650159274 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3650159274
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1038598896
Short name T576
Test name
Test status
Simulation time 417094473 ps
CPU time 1.69 seconds
Started Sep 27 01:02:49 PM PDT 23
Finished Sep 27 01:02:51 PM PDT 23
Peak memory 206092 kb
Host smart-cf1f4e8b-b515-48a5-a1cb-1dd7393e7248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038598896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1038598896
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1696037947
Short name T640
Test name
Test status
Simulation time 119115974033 ps
CPU time 611.26 seconds
Started Sep 27 01:05:52 PM PDT 23
Finished Sep 27 01:16:04 PM PDT 23
Peak memory 215312 kb
Host smart-126b577f-b211-4d78-9545-057d44cfa0de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696037947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1696037947
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2002865594
Short name T141
Test name
Test status
Simulation time 52725267 ps
CPU time 1.01 seconds
Started Sep 27 01:04:07 PM PDT 23
Finished Sep 27 01:04:08 PM PDT 23
Peak memory 216024 kb
Host smart-a7ad1876-d720-49c4-be4b-2421c90ec5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002865594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2002865594
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.409871890
Short name T430
Test name
Test status
Simulation time 24395664 ps
CPU time 0.9 seconds
Started Sep 27 01:04:04 PM PDT 23
Finished Sep 27 01:04:05 PM PDT 23
Peak memory 214780 kb
Host smart-d5648462-2b93-4639-bb21-3c3aaaa92318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409871890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.409871890
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.2889276174
Short name T146
Test name
Test status
Simulation time 18628482 ps
CPU time 0.93 seconds
Started Sep 27 01:04:30 PM PDT 23
Finished Sep 27 01:04:31 PM PDT 23
Peak memory 216068 kb
Host smart-0da8b55a-abe8-43f2-987e-218dcff4d7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889276174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2889276174
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.2125726262
Short name T543
Test name
Test status
Simulation time 128318850 ps
CPU time 0.98 seconds
Started Sep 27 01:04:05 PM PDT 23
Finished Sep 27 01:04:06 PM PDT 23
Peak memory 216248 kb
Host smart-39aeff62-2238-4b58-baba-4482b5f9986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125726262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2125726262
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.3629485665
Short name T163
Test name
Test status
Simulation time 68360524 ps
CPU time 0.79 seconds
Started Sep 27 01:01:39 PM PDT 23
Finished Sep 27 01:01:40 PM PDT 23
Peak memory 215956 kb
Host smart-9737f6fa-00be-49e7-bd5f-c303b1826123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629485665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3629485665
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.1928950209
Short name T593
Test name
Test status
Simulation time 66881806 ps
CPU time 0.8 seconds
Started Sep 27 01:03:47 PM PDT 23
Finished Sep 27 01:03:48 PM PDT 23
Peak memory 215988 kb
Host smart-fdb522d5-3e6a-4854-b959-0d12ef689442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928950209 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1928950209
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.1492136848
Short name T292
Test name
Test status
Simulation time 27523992 ps
CPU time 1.15 seconds
Started Sep 27 01:03:38 PM PDT 23
Finished Sep 27 01:03:39 PM PDT 23
Peak memory 214780 kb
Host smart-62409763-3409-42b2-a7ba-95a598a3aa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492136848 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1492136848
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.4224901500
Short name T139
Test name
Test status
Simulation time 50054686 ps
CPU time 0.92 seconds
Started Sep 27 01:08:19 PM PDT 23
Finished Sep 27 01:08:20 PM PDT 23
Peak memory 214816 kb
Host smart-530deea4-0518-465f-a0d3-77d09999b9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224901500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4224901500
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.510690280
Short name T556
Test name
Test status
Simulation time 18517455 ps
CPU time 1.22 seconds
Started Sep 27 01:04:18 PM PDT 23
Finished Sep 27 01:04:19 PM PDT 23
Peak memory 216060 kb
Host smart-b0f8e8d6-d1a1-42fc-b9c1-e20dc83d713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510690280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.510690280
Directory /workspace/99.edn_err/latest
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