Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.89 99.02 92.39 96.84 93.42 98.62 99.77 98.14


Total test records in report: 729
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T549 /workspace/coverage/default/1.edn_stress_all.2865778492 Oct 01 12:41:04 PM PDT 23 Oct 01 12:41:09 PM PDT 23 1027801232 ps
T159 /workspace/coverage/default/34.edn_disable.1800255628 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:39 PM PDT 23 12048123 ps
T550 /workspace/coverage/default/42.edn_smoke.2811496369 Oct 01 12:42:43 PM PDT 23 Oct 01 12:42:45 PM PDT 23 14802563 ps
T551 /workspace/coverage/default/4.edn_disable_auto_req_mode.532257847 Oct 01 12:41:24 PM PDT 23 Oct 01 12:41:26 PM PDT 23 26669001 ps
T552 /workspace/coverage/default/39.edn_disable.1839620305 Oct 01 12:42:07 PM PDT 23 Oct 01 12:42:08 PM PDT 23 40051519 ps
T553 /workspace/coverage/default/70.edn_err.1523798972 Oct 01 12:42:28 PM PDT 23 Oct 01 12:42:30 PM PDT 23 29242991 ps
T554 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1796012096 Oct 01 12:42:18 PM PDT 23 Oct 01 12:47:43 PM PDT 23 29532992920 ps
T131 /workspace/coverage/default/8.edn_err.3015589126 Oct 01 12:41:30 PM PDT 23 Oct 01 12:41:31 PM PDT 23 27236349 ps
T555 /workspace/coverage/default/41.edn_stress_all.14154922 Oct 01 12:42:45 PM PDT 23 Oct 01 12:42:47 PM PDT 23 119029398 ps
T257 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3653838160 Oct 01 12:41:34 PM PDT 23 Oct 01 12:47:29 PM PDT 23 35076704139 ps
T556 /workspace/coverage/default/10.edn_intr.3853117029 Oct 01 12:41:48 PM PDT 23 Oct 01 12:41:50 PM PDT 23 23422388 ps
T557 /workspace/coverage/default/89.edn_err.3063161558 Oct 01 12:42:52 PM PDT 23 Oct 01 12:42:53 PM PDT 23 18358529 ps
T169 /workspace/coverage/default/4.edn_disable.3558618447 Oct 01 12:41:14 PM PDT 23 Oct 01 12:41:15 PM PDT 23 86749198 ps
T157 /workspace/coverage/default/62.edn_err.1774044153 Oct 01 12:42:46 PM PDT 23 Oct 01 12:42:47 PM PDT 23 30553120 ps
T558 /workspace/coverage/default/40.edn_genbits.2420477748 Oct 01 12:42:21 PM PDT 23 Oct 01 12:42:22 PM PDT 23 21773916 ps
T559 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1709470165 Oct 01 12:42:22 PM PDT 23 Oct 01 12:45:48 PM PDT 23 17220220233 ps
T282 /workspace/coverage/default/15.edn_alert.1637520387 Oct 01 12:41:59 PM PDT 23 Oct 01 12:42:00 PM PDT 23 65358580 ps
T560 /workspace/coverage/default/34.edn_alert_test.1906774546 Oct 01 12:42:11 PM PDT 23 Oct 01 12:42:13 PM PDT 23 15907133 ps
T561 /workspace/coverage/default/30.edn_intr.754110679 Oct 01 12:42:14 PM PDT 23 Oct 01 12:42:15 PM PDT 23 26520575 ps
T162 /workspace/coverage/default/86.edn_err.3098722523 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:38 PM PDT 23 18515906 ps
T562 /workspace/coverage/default/9.edn_intr.3032343969 Oct 01 12:41:15 PM PDT 23 Oct 01 12:41:16 PM PDT 23 26258293 ps
T167 /workspace/coverage/default/23.edn_disable.3489693849 Oct 01 12:42:02 PM PDT 23 Oct 01 12:42:03 PM PDT 23 38462241 ps
T563 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2494454969 Oct 01 12:42:40 PM PDT 23 Oct 01 12:57:38 PM PDT 23 237913339296 ps
T564 /workspace/coverage/default/29.edn_stress_all.4258007032 Oct 01 12:41:58 PM PDT 23 Oct 01 12:42:00 PM PDT 23 39502038 ps
T565 /workspace/coverage/default/53.edn_err.1542479843 Oct 01 12:42:35 PM PDT 23 Oct 01 12:42:37 PM PDT 23 38703867 ps
T566 /workspace/coverage/default/9.edn_smoke.679278673 Oct 01 12:41:16 PM PDT 23 Oct 01 12:41:17 PM PDT 23 18043509 ps
T132 /workspace/coverage/default/75.edn_err.2897513577 Oct 01 12:43:26 PM PDT 23 Oct 01 12:43:27 PM PDT 23 33523079 ps
T158 /workspace/coverage/default/18.edn_err.4191503937 Oct 01 12:41:58 PM PDT 23 Oct 01 12:41:59 PM PDT 23 20453968 ps
T160 /workspace/coverage/default/19.edn_disable.4063198185 Oct 01 12:41:55 PM PDT 23 Oct 01 12:41:57 PM PDT 23 86522832 ps
T567 /workspace/coverage/default/24.edn_smoke.2804247002 Oct 01 12:41:59 PM PDT 23 Oct 01 12:42:01 PM PDT 23 81006234 ps
T568 /workspace/coverage/default/49.edn_disable_auto_req_mode.1797762688 Oct 01 12:42:38 PM PDT 23 Oct 01 12:42:39 PM PDT 23 28372530 ps
T100 /workspace/coverage/default/23.edn_genbits.965819966 Oct 01 12:42:31 PM PDT 23 Oct 01 12:42:32 PM PDT 23 65884913 ps
T266 /workspace/coverage/default/12.edn_genbits.711581363 Oct 01 12:41:36 PM PDT 23 Oct 01 12:41:37 PM PDT 23 18428780 ps
T569 /workspace/coverage/default/29.edn_disable.2039283709 Oct 01 12:42:24 PM PDT 23 Oct 01 12:42:25 PM PDT 23 12019905 ps
T229 /workspace/coverage/default/48.edn_disable_auto_req_mode.1522257729 Oct 01 12:42:46 PM PDT 23 Oct 01 12:42:47 PM PDT 23 60207346 ps
T570 /workspace/coverage/default/4.edn_genbits.973515766 Oct 01 12:41:14 PM PDT 23 Oct 01 12:41:15 PM PDT 23 119782689 ps
T571 /workspace/coverage/default/3.edn_genbits.3852229396 Oct 01 12:41:29 PM PDT 23 Oct 01 12:41:31 PM PDT 23 28221694 ps
T145 /workspace/coverage/default/31.edn_disable_auto_req_mode.2330993675 Oct 01 12:42:04 PM PDT 23 Oct 01 12:42:05 PM PDT 23 134699512 ps
T106 /workspace/coverage/default/7.edn_intr.917197503 Oct 01 12:41:23 PM PDT 23 Oct 01 12:41:24 PM PDT 23 29169467 ps
T572 /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4176096762 Oct 01 12:41:27 PM PDT 23 Oct 01 12:47:37 PM PDT 23 18117024919 ps
T573 /workspace/coverage/default/15.edn_alert_test.744035044 Oct 01 12:41:56 PM PDT 23 Oct 01 12:41:57 PM PDT 23 14656671 ps
T574 /workspace/coverage/default/6.edn_smoke.829707477 Oct 01 12:41:36 PM PDT 23 Oct 01 12:41:38 PM PDT 23 39648778 ps
T575 /workspace/coverage/default/29.edn_alert_test.1180429976 Oct 01 12:42:23 PM PDT 23 Oct 01 12:42:24 PM PDT 23 30201977 ps
T576 /workspace/coverage/default/39.edn_smoke.681528363 Oct 01 12:42:21 PM PDT 23 Oct 01 12:42:22 PM PDT 23 111223135 ps
T168 /workspace/coverage/default/24.edn_disable.1731596680 Oct 01 12:42:40 PM PDT 23 Oct 01 12:42:41 PM PDT 23 40500221 ps
T577 /workspace/coverage/default/35.edn_genbits.659694373 Oct 01 12:42:31 PM PDT 23 Oct 01 12:42:33 PM PDT 23 18927390 ps
T578 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1609219681 Oct 01 12:41:59 PM PDT 23 Oct 01 12:56:41 PM PDT 23 122849115477 ps
T579 /workspace/coverage/default/36.edn_stress_all.1677473048 Oct 01 12:42:17 PM PDT 23 Oct 01 12:42:19 PM PDT 23 81561461 ps
T125 /workspace/coverage/default/49.edn_disable.180527380 Oct 01 12:42:45 PM PDT 23 Oct 01 12:42:46 PM PDT 23 21494170 ps
T150 /workspace/coverage/default/91.edn_err.2012295441 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:38 PM PDT 23 24800060 ps
T580 /workspace/coverage/default/43.edn_disable_auto_req_mode.156534873 Oct 01 12:42:17 PM PDT 23 Oct 01 12:42:19 PM PDT 23 49774739 ps
T581 /workspace/coverage/default/11.edn_err.448799123 Oct 01 12:41:54 PM PDT 23 Oct 01 12:41:55 PM PDT 23 127221482 ps
T582 /workspace/coverage/default/9.edn_alert_test.1952894087 Oct 01 12:41:35 PM PDT 23 Oct 01 12:41:36 PM PDT 23 44033591 ps
T583 /workspace/coverage/default/46.edn_intr.2755248790 Oct 01 12:42:39 PM PDT 23 Oct 01 12:42:40 PM PDT 23 29942082 ps
T584 /workspace/coverage/default/84.edn_err.2243571212 Oct 01 12:43:21 PM PDT 23 Oct 01 12:43:22 PM PDT 23 44212684 ps
T585 /workspace/coverage/default/20.edn_disable_auto_req_mode.464913511 Oct 01 12:42:17 PM PDT 23 Oct 01 12:42:19 PM PDT 23 103197058 ps
T107 /workspace/coverage/default/6.edn_intr.24125961 Oct 01 12:41:43 PM PDT 23 Oct 01 12:41:44 PM PDT 23 23798524 ps
T586 /workspace/coverage/default/19.edn_intr.3251759282 Oct 01 12:41:58 PM PDT 23 Oct 01 12:41:59 PM PDT 23 81085649 ps
T587 /workspace/coverage/default/47.edn_disable_auto_req_mode.2818064330 Oct 01 12:42:50 PM PDT 23 Oct 01 12:42:51 PM PDT 23 403546916 ps
T588 /workspace/coverage/default/16.edn_stress_all.3565423563 Oct 01 12:42:13 PM PDT 23 Oct 01 12:42:16 PM PDT 23 364313040 ps
T589 /workspace/coverage/default/37.edn_err.3634873640 Oct 01 12:42:24 PM PDT 23 Oct 01 12:42:25 PM PDT 23 64024311 ps
T147 /workspace/coverage/default/92.edn_err.3722423817 Oct 01 12:42:35 PM PDT 23 Oct 01 12:42:36 PM PDT 23 35015496 ps
T590 /workspace/coverage/default/43.edn_disable.175849362 Oct 01 12:42:45 PM PDT 23 Oct 01 12:42:46 PM PDT 23 31126288 ps
T591 /workspace/coverage/default/8.edn_smoke.2329396704 Oct 01 12:41:17 PM PDT 23 Oct 01 12:41:18 PM PDT 23 22098233 ps
T592 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.484848467 Oct 01 12:42:11 PM PDT 23 Oct 01 12:50:04 PM PDT 23 100196947898 ps
T593 /workspace/coverage/default/36.edn_smoke.848654419 Oct 01 12:42:46 PM PDT 23 Oct 01 12:42:47 PM PDT 23 14708793 ps
T594 /workspace/coverage/default/36.edn_genbits.2144690693 Oct 01 12:42:32 PM PDT 23 Oct 01 12:42:33 PM PDT 23 37787547 ps
T595 /workspace/coverage/default/35.edn_disable.1771671188 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:38 PM PDT 23 28947433 ps
T596 /workspace/coverage/default/33.edn_stress_all.2127796908 Oct 01 12:42:18 PM PDT 23 Oct 01 12:42:20 PM PDT 23 96162480 ps
T597 /workspace/coverage/default/48.edn_smoke.3121420447 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:38 PM PDT 23 20890662 ps
T598 /workspace/coverage/default/27.edn_alert_test.3215784600 Oct 01 12:42:33 PM PDT 23 Oct 01 12:42:34 PM PDT 23 22405215 ps
T599 /workspace/coverage/default/0.edn_intr.796532623 Oct 01 12:41:23 PM PDT 23 Oct 01 12:41:24 PM PDT 23 21400707 ps
T600 /workspace/coverage/default/18.edn_alert_test.2601453971 Oct 01 12:41:54 PM PDT 23 Oct 01 12:41:55 PM PDT 23 32998231 ps
T140 /workspace/coverage/default/72.edn_err.2476886872 Oct 01 12:42:22 PM PDT 23 Oct 01 12:42:24 PM PDT 23 44184095 ps
T601 /workspace/coverage/default/36.edn_disable.3248054361 Oct 01 12:42:40 PM PDT 23 Oct 01 12:42:41 PM PDT 23 17359309 ps
T602 /workspace/coverage/default/43.edn_smoke.2413430841 Oct 01 12:42:22 PM PDT 23 Oct 01 12:42:23 PM PDT 23 27152066 ps
T603 /workspace/coverage/default/15.edn_disable.1812244812 Oct 01 12:42:03 PM PDT 23 Oct 01 12:42:04 PM PDT 23 14347788 ps
T604 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.47611541 Oct 01 12:42:16 PM PDT 23 Oct 01 12:51:26 PM PDT 23 190883860875 ps
T605 /workspace/coverage/default/29.edn_disable_auto_req_mode.1423276850 Oct 01 12:42:25 PM PDT 23 Oct 01 12:42:26 PM PDT 23 68016577 ps
T606 /workspace/coverage/default/49.edn_alert_test.4216441066 Oct 01 12:42:38 PM PDT 23 Oct 01 12:42:40 PM PDT 23 155318695 ps
T607 /workspace/coverage/default/1.edn_smoke.2481048275 Oct 01 12:41:25 PM PDT 23 Oct 01 12:41:31 PM PDT 23 48672476 ps
T608 /workspace/coverage/default/2.edn_alert_test.3448709034 Oct 01 12:41:33 PM PDT 23 Oct 01 12:41:34 PM PDT 23 15250404 ps
T283 /workspace/coverage/default/14.edn_alert.1686528525 Oct 01 12:42:04 PM PDT 23 Oct 01 12:42:06 PM PDT 23 63732374 ps
T609 /workspace/coverage/default/5.edn_smoke.1080817177 Oct 01 12:41:24 PM PDT 23 Oct 01 12:41:25 PM PDT 23 17818422 ps
T232 /workspace/coverage/default/58.edn_err.3772147755 Oct 01 12:43:02 PM PDT 23 Oct 01 12:43:04 PM PDT 23 92570264 ps
T610 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1159633600 Oct 01 12:42:05 PM PDT 23 Oct 01 12:52:49 PM PDT 23 119407539786 ps
T611 /workspace/coverage/default/32.edn_smoke.3962102484 Oct 01 12:42:18 PM PDT 23 Oct 01 12:42:20 PM PDT 23 17449446 ps
T612 /workspace/coverage/default/11.edn_smoke.4198810456 Oct 01 12:41:56 PM PDT 23 Oct 01 12:41:57 PM PDT 23 23233201 ps
T613 /workspace/coverage/default/44.edn_err.1663788121 Oct 01 12:42:26 PM PDT 23 Oct 01 12:42:27 PM PDT 23 31986773 ps
T173 /workspace/coverage/default/34.edn_err.2687765583 Oct 01 12:42:22 PM PDT 23 Oct 01 12:42:23 PM PDT 23 22403474 ps
T614 /workspace/coverage/default/41.edn_intr.1218067434 Oct 01 12:42:48 PM PDT 23 Oct 01 12:42:49 PM PDT 23 22949445 ps
T122 /workspace/coverage/default/32.edn_disable.1091790909 Oct 01 12:42:20 PM PDT 23 Oct 01 12:42:21 PM PDT 23 10579794 ps
T292 /workspace/coverage/default/7.edn_alert.2922923401 Oct 01 12:41:09 PM PDT 23 Oct 01 12:41:11 PM PDT 23 76429933 ps
T284 /workspace/coverage/default/5.edn_regwen.2549222426 Oct 01 12:41:17 PM PDT 23 Oct 01 12:41:18 PM PDT 23 78368499 ps
T615 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.933667489 Oct 01 12:42:13 PM PDT 23 Oct 01 01:11:36 PM PDT 23 271813388794 ps
T273 /workspace/coverage/default/25.edn_disable_auto_req_mode.335089014 Oct 01 12:42:18 PM PDT 23 Oct 01 12:42:19 PM PDT 23 45121177 ps
T616 /workspace/coverage/default/9.edn_stress_all.566033229 Oct 01 12:41:29 PM PDT 23 Oct 01 12:41:31 PM PDT 23 40004245 ps
T617 /workspace/coverage/default/47.edn_disable.246599165 Oct 01 12:42:36 PM PDT 23 Oct 01 12:42:37 PM PDT 23 16234680 ps
T258 /workspace/coverage/default/2.edn_genbits.1487280017 Oct 01 12:41:27 PM PDT 23 Oct 01 12:41:28 PM PDT 23 27156747 ps
T618 /workspace/coverage/default/6.edn_err.3643690761 Oct 01 12:41:26 PM PDT 23 Oct 01 12:41:27 PM PDT 23 32832572 ps
T619 /workspace/coverage/default/26.edn_stress_all.1208247061 Oct 01 12:42:09 PM PDT 23 Oct 01 12:42:10 PM PDT 23 47782658 ps
T233 /workspace/coverage/default/26.edn_disable.2567187098 Oct 01 12:42:05 PM PDT 23 Oct 01 12:42:06 PM PDT 23 34455226 ps
T163 /workspace/coverage/default/94.edn_err.2479814950 Oct 01 12:43:02 PM PDT 23 Oct 01 12:43:04 PM PDT 23 20135663 ps
T174 /workspace/coverage/default/4.edn_err.1517371057 Oct 01 12:41:27 PM PDT 23 Oct 01 12:41:28 PM PDT 23 47366368 ps
T620 /workspace/coverage/default/0.edn_disable_auto_req_mode.2640298770 Oct 01 12:41:34 PM PDT 23 Oct 01 12:41:35 PM PDT 23 30473615 ps
T621 /workspace/coverage/default/33.edn_disable.2546175938 Oct 01 12:42:19 PM PDT 23 Oct 01 12:42:20 PM PDT 23 39488118 ps
T622 /workspace/coverage/default/59.edn_err.4105043734 Oct 01 12:42:21 PM PDT 23 Oct 01 12:42:22 PM PDT 23 22419292 ps
T153 /workspace/coverage/default/24.edn_disable_auto_req_mode.3724412999 Oct 01 12:42:15 PM PDT 23 Oct 01 12:42:16 PM PDT 23 211507310 ps
T623 /workspace/coverage/default/20.edn_intr.2325508050 Oct 01 12:42:04 PM PDT 23 Oct 01 12:42:05 PM PDT 23 63722091 ps
T624 /workspace/coverage/default/17.edn_smoke.4088255642 Oct 01 12:42:15 PM PDT 23 Oct 01 12:42:16 PM PDT 23 32665181 ps
T625 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.817096721 Oct 01 12:42:02 PM PDT 23 Oct 01 01:06:25 PM PDT 23 59551375735 ps
T626 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2926253473 Oct 01 12:42:42 PM PDT 23 Oct 01 12:56:09 PM PDT 23 33762757503 ps
T627 /workspace/coverage/default/31.edn_alert.4181590257 Oct 01 12:42:25 PM PDT 23 Oct 01 12:42:26 PM PDT 23 56456893 ps
T628 /workspace/coverage/default/13.edn_disable.1141054606 Oct 01 12:41:52 PM PDT 23 Oct 01 12:41:53 PM PDT 23 19555439 ps
T629 /workspace/coverage/default/27.edn_smoke.1747049760 Oct 01 12:42:23 PM PDT 23 Oct 01 12:42:25 PM PDT 23 15919547 ps
T630 /workspace/coverage/default/26.edn_alert_test.577308027 Oct 01 12:42:30 PM PDT 23 Oct 01 12:42:36 PM PDT 23 124755407 ps
T143 /workspace/coverage/default/79.edn_err.3449268555 Oct 01 12:43:14 PM PDT 23 Oct 01 12:43:15 PM PDT 23 119279311 ps
T631 /workspace/coverage/default/8.edn_stress_all.1442140304 Oct 01 12:41:14 PM PDT 23 Oct 01 12:41:18 PM PDT 23 1144361720 ps
T632 /workspace/coverage/default/0.edn_stress_all.2405805686 Oct 01 12:41:31 PM PDT 23 Oct 01 12:41:33 PM PDT 23 73432989 ps
T633 /workspace/coverage/default/97.edn_err.2552112248 Oct 01 12:42:50 PM PDT 23 Oct 01 12:42:51 PM PDT 23 19151964 ps
T634 /workspace/coverage/default/47.edn_smoke.2113140217 Oct 01 12:43:00 PM PDT 23 Oct 01 12:43:01 PM PDT 23 35400669 ps
T635 /workspace/coverage/default/13.edn_err.1892673078 Oct 01 12:41:43 PM PDT 23 Oct 01 12:41:44 PM PDT 23 25058806 ps
T636 /workspace/coverage/default/57.edn_err.558421538 Oct 01 12:42:28 PM PDT 23 Oct 01 12:42:30 PM PDT 23 24929991 ps
T234 /workspace/coverage/default/9.edn_disable.3153179487 Oct 01 12:41:25 PM PDT 23 Oct 01 12:41:26 PM PDT 23 13463031 ps
T637 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2304293598 Oct 01 12:42:19 PM PDT 23 Oct 01 01:06:50 PM PDT 23 623238766126 ps
T126 /workspace/coverage/default/0.edn_disable.1417731464 Oct 01 12:41:22 PM PDT 23 Oct 01 12:41:28 PM PDT 23 55263713 ps
T638 /workspace/coverage/default/44.edn_genbits.3203065318 Oct 01 12:42:40 PM PDT 23 Oct 01 12:42:41 PM PDT 23 53464702 ps
T285 /workspace/coverage/default/29.edn_alert.3129092751 Oct 01 12:42:43 PM PDT 23 Oct 01 12:42:45 PM PDT 23 20399602 ps
T639 /workspace/coverage/default/7.edn_disable_auto_req_mode.73302529 Oct 01 12:41:18 PM PDT 23 Oct 01 12:41:19 PM PDT 23 29917151 ps
T640 /workspace/coverage/default/6.edn_stress_all.2030195013 Oct 01 12:41:33 PM PDT 23 Oct 01 12:41:34 PM PDT 23 135492300 ps
T641 /workspace/coverage/default/13.edn_intr.3366341141 Oct 01 12:41:25 PM PDT 23 Oct 01 12:41:26 PM PDT 23 44594984 ps
T642 /workspace/coverage/default/26.edn_smoke.79676416 Oct 01 12:42:10 PM PDT 23 Oct 01 12:42:11 PM PDT 23 30375482 ps
T172 /workspace/coverage/default/31.edn_disable.3182890720 Oct 01 12:42:19 PM PDT 23 Oct 01 12:42:20 PM PDT 23 10300983 ps
T643 /workspace/coverage/default/9.edn_disable_auto_req_mode.1026311022 Oct 01 12:41:58 PM PDT 23 Oct 01 12:41:59 PM PDT 23 24576401 ps
T644 /workspace/coverage/default/21.edn_alert_test.2978633523 Oct 01 12:42:28 PM PDT 23 Oct 01 12:42:29 PM PDT 23 38434931 ps
T645 /workspace/coverage/default/28.edn_intr.2189215688 Oct 01 12:42:19 PM PDT 23 Oct 01 12:42:20 PM PDT 23 19687607 ps
T646 /workspace/coverage/default/22.edn_smoke.2681304993 Oct 01 12:42:27 PM PDT 23 Oct 01 12:42:28 PM PDT 23 14299991 ps
T647 /workspace/coverage/default/43.edn_intr.3438888434 Oct 01 12:42:16 PM PDT 23 Oct 01 12:42:17 PM PDT 23 41866964 ps
T123 /workspace/coverage/default/18.edn_disable.1152783792 Oct 01 12:42:00 PM PDT 23 Oct 01 12:42:01 PM PDT 23 10624658 ps
T648 /workspace/coverage/default/47.edn_alert.2336297114 Oct 01 12:42:43 PM PDT 23 Oct 01 12:42:44 PM PDT 23 17054647 ps
T649 /workspace/coverage/default/44.edn_alert_test.12881245 Oct 01 12:42:42 PM PDT 23 Oct 01 12:42:43 PM PDT 23 101598405 ps
T128 /workspace/coverage/default/41.edn_disable.2348814143 Oct 01 12:42:20 PM PDT 23 Oct 01 12:42:22 PM PDT 23 13819434 ps
T650 /workspace/coverage/default/40.edn_stress_all.2560099767 Oct 01 12:42:05 PM PDT 23 Oct 01 12:42:08 PM PDT 23 117473625 ps
T651 /workspace/coverage/default/48.edn_alert_test.4033417510 Oct 01 12:42:24 PM PDT 23 Oct 01 12:42:25 PM PDT 23 14040341 ps
T652 /workspace/coverage/default/26.edn_disable_auto_req_mode.3762421133 Oct 01 12:42:33 PM PDT 23 Oct 01 12:42:34 PM PDT 23 97301030 ps
T653 /workspace/coverage/default/41.edn_alert_test.2294847694 Oct 01 12:42:43 PM PDT 23 Oct 01 12:42:44 PM PDT 23 75910696 ps
T654 /workspace/coverage/default/17.edn_alert.1711909876 Oct 01 12:42:04 PM PDT 23 Oct 01 12:42:05 PM PDT 23 19805927 ps
T655 /workspace/coverage/default/7.edn_regwen.4282921224 Oct 01 12:41:26 PM PDT 23 Oct 01 12:41:27 PM PDT 23 15546100 ps
T656 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3067344300 Oct 01 12:41:55 PM PDT 23 Oct 01 01:05:45 PM PDT 23 691581376611 ps
T657 /workspace/coverage/default/49.edn_smoke.1521792286 Oct 01 12:42:36 PM PDT 23 Oct 01 12:42:37 PM PDT 23 124300179 ps
T658 /workspace/coverage/default/33.edn_alert_test.2843334102 Oct 01 12:42:33 PM PDT 23 Oct 01 12:42:36 PM PDT 23 25351909 ps
T659 /workspace/coverage/default/47.edn_stress_all.1385762020 Oct 01 12:42:50 PM PDT 23 Oct 01 12:42:52 PM PDT 23 89530309 ps
T660 /workspace/coverage/default/96.edn_err.1248860335 Oct 01 12:43:29 PM PDT 23 Oct 01 12:43:30 PM PDT 23 20166566 ps
T661 /workspace/coverage/default/0.edn_smoke.1408455874 Oct 01 12:41:24 PM PDT 23 Oct 01 12:41:25 PM PDT 23 38060432 ps
T662 /workspace/coverage/default/18.edn_alert.132217293 Oct 01 12:41:38 PM PDT 23 Oct 01 12:41:39 PM PDT 23 173335549 ps
T663 /workspace/coverage/default/41.edn_genbits.1013946923 Oct 01 12:42:45 PM PDT 23 Oct 01 12:42:47 PM PDT 23 47678740 ps
T664 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3163022277 Oct 01 12:42:01 PM PDT 23 Oct 01 01:01:22 PM PDT 23 218823918918 ps
T665 /workspace/coverage/default/27.edn_alert.1663628791 Oct 01 12:42:28 PM PDT 23 Oct 01 12:42:30 PM PDT 23 15687397 ps
T666 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3964831679 Oct 01 12:42:18 PM PDT 23 Oct 01 01:18:18 PM PDT 23 98515734998 ps
T667 /workspace/coverage/default/11.edn_disable_auto_req_mode.3429990667 Oct 01 12:41:54 PM PDT 23 Oct 01 12:41:55 PM PDT 23 35450109 ps
T668 /workspace/coverage/default/30.edn_alert_test.3933124254 Oct 01 12:42:21 PM PDT 23 Oct 01 12:42:23 PM PDT 23 20696344 ps
T669 /workspace/coverage/default/17.edn_stress_all.1994629473 Oct 01 12:42:12 PM PDT 23 Oct 01 12:42:13 PM PDT 23 61535180 ps
T670 /workspace/coverage/default/39.edn_genbits.447181899 Oct 01 12:42:15 PM PDT 23 Oct 01 12:42:17 PM PDT 23 68658170 ps
T44 /workspace/coverage/default/2.edn_sec_cm.3115093519 Oct 01 12:41:32 PM PDT 23 Oct 01 12:41:38 PM PDT 23 1332031565 ps
T671 /workspace/coverage/default/11.edn_intr.2626870720 Oct 01 12:41:49 PM PDT 23 Oct 01 12:41:50 PM PDT 23 36889602 ps
T672 /workspace/coverage/default/6.edn_disable.3028025534 Oct 01 12:41:49 PM PDT 23 Oct 01 12:41:50 PM PDT 23 17982020 ps
T267 /workspace/coverage/default/22.edn_genbits.4136612342 Oct 01 12:42:40 PM PDT 23 Oct 01 12:42:41 PM PDT 23 14388154 ps
T673 /workspace/coverage/default/17.edn_disable_auto_req_mode.3133088416 Oct 01 12:41:52 PM PDT 23 Oct 01 12:41:53 PM PDT 23 15939946 ps
T674 /workspace/coverage/default/31.edn_stress_all.34848351 Oct 01 12:42:22 PM PDT 23 Oct 01 12:42:26 PM PDT 23 360192771 ps
T675 /workspace/coverage/default/13.edn_disable_auto_req_mode.2206836814 Oct 01 12:41:54 PM PDT 23 Oct 01 12:41:55 PM PDT 23 20890233 ps
T676 /workspace/coverage/default/21.edn_disable_auto_req_mode.378299709 Oct 01 12:42:16 PM PDT 23 Oct 01 12:42:17 PM PDT 23 66098118 ps
T677 /workspace/coverage/default/23.edn_err.3640698372 Oct 01 12:42:18 PM PDT 23 Oct 01 12:42:20 PM PDT 23 29794482 ps
T175 /workspace/coverage/default/17.edn_err.418246542 Oct 01 12:41:49 PM PDT 23 Oct 01 12:41:50 PM PDT 23 27795811 ps
T124 /workspace/coverage/default/2.edn_disable.1342122010 Oct 01 12:41:12 PM PDT 23 Oct 01 12:41:13 PM PDT 23 15689394 ps
T678 /workspace/coverage/default/15.edn_intr.2756101671 Oct 01 12:42:06 PM PDT 23 Oct 01 12:42:07 PM PDT 23 27988760 ps
T679 /workspace/coverage/default/78.edn_err.2048721623 Oct 01 12:43:19 PM PDT 23 Oct 01 12:43:21 PM PDT 23 32510597 ps
T680 /workspace/coverage/default/19.edn_stress_all.836566508 Oct 01 12:41:52 PM PDT 23 Oct 01 12:41:55 PM PDT 23 175977224 ps
T681 /workspace/coverage/default/2.edn_smoke.222990681 Oct 01 12:41:20 PM PDT 23 Oct 01 12:41:21 PM PDT 23 14037359 ps
T682 /workspace/coverage/default/10.edn_smoke.378130937 Oct 01 12:41:36 PM PDT 23 Oct 01 12:41:37 PM PDT 23 47294284 ps
T683 /workspace/coverage/default/45.edn_alert_test.2169768309 Oct 01 12:42:41 PM PDT 23 Oct 01 12:42:42 PM PDT 23 56743798 ps
T684 /workspace/coverage/default/10.edn_alert_test.3458961991 Oct 01 12:41:41 PM PDT 23 Oct 01 12:41:42 PM PDT 23 242294425 ps
T685 /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1345973226 Oct 01 12:42:41 PM PDT 23 Oct 01 12:49:33 PM PDT 23 34362748020 ps
T686 /workspace/coverage/default/14.edn_alert_test.511180993 Oct 01 12:41:44 PM PDT 23 Oct 01 12:41:46 PM PDT 23 17258169 ps
T687 /workspace/coverage/default/24.edn_alert_test.4049010380 Oct 01 12:41:54 PM PDT 23 Oct 01 12:41:55 PM PDT 23 19735656 ps
T688 /workspace/coverage/default/22.edn_alert.3545826980 Oct 01 12:42:20 PM PDT 23 Oct 01 12:42:22 PM PDT 23 221141976 ps
T689 /workspace/coverage/default/49.edn_alert.1081311644 Oct 01 12:42:39 PM PDT 23 Oct 01 12:42:40 PM PDT 23 100915671 ps
T690 /workspace/coverage/default/43.edn_stress_all.263084193 Oct 01 12:42:41 PM PDT 23 Oct 01 12:42:45 PM PDT 23 767819922 ps
T691 /workspace/coverage/default/93.edn_err.1473861160 Oct 01 12:43:20 PM PDT 23 Oct 01 12:43:21 PM PDT 23 32699607 ps
T692 /workspace/coverage/default/68.edn_err.27380808 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:39 PM PDT 23 18015051 ps
T693 /workspace/coverage/default/8.edn_disable_auto_req_mode.3680211768 Oct 01 12:41:52 PM PDT 23 Oct 01 12:41:53 PM PDT 23 13664599 ps
T141 /workspace/coverage/default/65.edn_err.3803186926 Oct 01 12:42:17 PM PDT 23 Oct 01 12:42:18 PM PDT 23 24113405 ps
T694 /workspace/coverage/default/30.edn_disable_auto_req_mode.881742476 Oct 01 12:42:16 PM PDT 23 Oct 01 12:42:17 PM PDT 23 17127912 ps
T695 /workspace/coverage/default/10.edn_alert.3076154868 Oct 01 12:41:34 PM PDT 23 Oct 01 12:41:36 PM PDT 23 24452999 ps
T696 /workspace/coverage/default/37.edn_intr.3218207051 Oct 01 12:42:36 PM PDT 23 Oct 01 12:42:37 PM PDT 23 23768455 ps
T697 /workspace/coverage/default/4.edn_stress_all.1132786720 Oct 01 12:41:26 PM PDT 23 Oct 01 12:41:29 PM PDT 23 150184366 ps
T698 /workspace/coverage/default/37.edn_disable.694619889 Oct 01 12:42:08 PM PDT 23 Oct 01 12:42:09 PM PDT 23 13329681 ps
T699 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3834537240 Oct 01 12:42:26 PM PDT 23 Oct 01 12:54:28 PM PDT 23 217361300535 ps
T45 /workspace/coverage/default/4.edn_sec_cm.560145171 Oct 01 12:41:13 PM PDT 23 Oct 01 12:41:19 PM PDT 23 1287701377 ps
T700 /workspace/coverage/default/25.edn_smoke.1354485692 Oct 01 12:42:01 PM PDT 23 Oct 01 12:42:02 PM PDT 23 13602307 ps
T701 /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3279314479 Oct 01 12:41:17 PM PDT 23 Oct 01 12:49:09 PM PDT 23 98024029726 ps
T702 /workspace/coverage/default/3.edn_alert.1931658854 Oct 01 12:41:36 PM PDT 23 Oct 01 12:41:37 PM PDT 23 64414296 ps
T703 /workspace/coverage/default/37.edn_smoke.257801292 Oct 01 12:42:20 PM PDT 23 Oct 01 12:42:22 PM PDT 23 19025341 ps
T704 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1940619822 Oct 01 12:42:18 PM PDT 23 Oct 01 01:11:43 PM PDT 23 606932382243 ps
T705 /workspace/coverage/default/48.edn_stress_all.818051593 Oct 01 12:42:36 PM PDT 23 Oct 01 12:42:40 PM PDT 23 198135135 ps
T706 /workspace/coverage/default/3.edn_err.968705259 Oct 01 12:41:13 PM PDT 23 Oct 01 12:41:14 PM PDT 23 24394443 ps
T707 /workspace/coverage/default/15.edn_smoke.2400236263 Oct 01 12:41:33 PM PDT 23 Oct 01 12:41:34 PM PDT 23 35115484 ps
T708 /workspace/coverage/default/61.edn_err.927321449 Oct 01 12:42:23 PM PDT 23 Oct 01 12:42:24 PM PDT 23 58074191 ps
T151 /workspace/coverage/default/31.edn_err.234650028 Oct 01 12:42:23 PM PDT 23 Oct 01 12:42:24 PM PDT 23 62932290 ps
T709 /workspace/coverage/default/27.edn_err.4082781963 Oct 01 12:42:24 PM PDT 23 Oct 01 12:42:25 PM PDT 23 26109894 ps
T710 /workspace/coverage/default/5.edn_alert_test.3658994408 Oct 01 12:41:51 PM PDT 23 Oct 01 12:41:52 PM PDT 23 19117011 ps
T711 /workspace/coverage/default/11.edn_stress_all.2952185836 Oct 01 12:41:52 PM PDT 23 Oct 01 12:41:54 PM PDT 23 61162496 ps
T712 /workspace/coverage/default/17.edn_genbits.1769777065 Oct 01 12:42:16 PM PDT 23 Oct 01 12:42:18 PM PDT 23 185410591 ps
T713 /workspace/coverage/default/35.edn_smoke.3573972874 Oct 01 12:42:09 PM PDT 23 Oct 01 12:42:10 PM PDT 23 23424573 ps
T714 /workspace/coverage/default/21.edn_smoke.2572671121 Oct 01 12:42:12 PM PDT 23 Oct 01 12:42:13 PM PDT 23 42044536 ps
T715 /workspace/coverage/default/18.edn_genbits.3176624942 Oct 01 12:41:39 PM PDT 23 Oct 01 12:41:41 PM PDT 23 39589817 ps
T716 /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4235336427 Oct 01 12:41:59 PM PDT 23 Oct 01 01:06:17 PM PDT 23 141415315759 ps
T717 /workspace/coverage/default/28.edn_disable.23347599 Oct 01 12:42:17 PM PDT 23 Oct 01 12:42:24 PM PDT 23 14561148 ps
T718 /workspace/coverage/default/24.edn_intr.3808339459 Oct 01 12:42:10 PM PDT 23 Oct 01 12:42:11 PM PDT 23 21511116 ps
T719 /workspace/coverage/default/13.edn_smoke.3664998568 Oct 01 12:41:26 PM PDT 23 Oct 01 12:41:27 PM PDT 23 16075266 ps
T720 /workspace/coverage/default/46.edn_stress_all.594807962 Oct 01 12:42:37 PM PDT 23 Oct 01 12:42:38 PM PDT 23 22631465 ps
T721 /workspace/coverage/default/30.edn_alert.1902854067 Oct 01 12:42:23 PM PDT 23 Oct 01 12:42:25 PM PDT 23 16344785 ps
T722 /workspace/coverage/default/3.edn_smoke.2391812986 Oct 01 12:41:16 PM PDT 23 Oct 01 12:41:17 PM PDT 23 18373039 ps
T723 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1844794121 Oct 01 12:42:31 PM PDT 23 Oct 01 12:46:37 PM PDT 23 20999375769 ps
T724 /workspace/coverage/default/0.edn_genbits.2375503766 Oct 01 12:41:28 PM PDT 23 Oct 01 12:41:29 PM PDT 23 111657872 ps
T725 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1393125409 Oct 01 12:42:26 PM PDT 23 Oct 01 12:55:42 PM PDT 23 146358015133 ps
T726 /workspace/coverage/default/33.edn_genbits.4276759069 Oct 01 12:42:24 PM PDT 23 Oct 01 12:42:25 PM PDT 23 33044672 ps
T727 /workspace/coverage/default/9.edn_regwen.3421553975 Oct 01 12:41:32 PM PDT 23 Oct 01 12:41:33 PM PDT 23 19564063 ps
T728 /workspace/coverage/default/16.edn_err.1115901324 Oct 01 12:41:56 PM PDT 23 Oct 01 12:41:57 PM PDT 23 72580244 ps
T729 /workspace/coverage/default/32.edn_alert.52384502 Oct 01 12:42:11 PM PDT 23 Oct 01 12:42:12 PM PDT 23 39116871 ps

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.587824604
Short name T15
Test name
Test status
Simulation time 133726324996 ps
CPU time 771.04 seconds
Started Oct 01 12:41:35 PM PDT 23
Finished Oct 01 12:54:27 PM PDT 23
Peak memory 215352 kb
Host smart-b500adb6-8121-4591-a1cc-3f7493c1ad15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587824604 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.587824604
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_genbits.531566107
Short name T25
Test name
Test status
Simulation time 23004547 ps
CPU time 1.4 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 205480 kb
Host smart-77c5f43f-f61a-4d0f-84db-bd58e9153b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531566107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.531566107
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2134649264
Short name T1
Test name
Test status
Simulation time 2611832866 ps
CPU time 3.53 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:30 PM PDT 23
Peak memory 233276 kb
Host smart-fc17099b-2491-4e67-a28d-44b2d3ed1852
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134649264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2134649264
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3853431428
Short name T26
Test name
Test status
Simulation time 86649954 ps
CPU time 0.95 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214604 kb
Host smart-319fade8-89d6-41e6-b5eb-14024e490cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853431428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3853431428
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2030979189
Short name T4
Test name
Test status
Simulation time 48739816 ps
CPU time 1.04 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 228900 kb
Host smart-1ad5cab8-96b7-4cdd-8737-d4cbe5677a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030979189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2030979189
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/48.edn_alert.2843450500
Short name T9
Test name
Test status
Simulation time 32787923 ps
CPU time 0.95 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 206160 kb
Host smart-915ff4d2-87cd-4354-8ce4-1fa0da040122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843450500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2843450500
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.3801709782
Short name T61
Test name
Test status
Simulation time 14509431 ps
CPU time 0.9 seconds
Started Oct 01 12:41:15 PM PDT 23
Finished Oct 01 12:41:17 PM PDT 23
Peak memory 204896 kb
Host smart-93e57cf3-abd1-4cf2-8d42-b08b2599466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801709782 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3801709782
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/39.edn_intr.1338417183
Short name T13
Test name
Test status
Simulation time 20254885 ps
CPU time 1.03 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 214760 kb
Host smart-f34fad6a-f667-41d9-b6b3-18788b7deed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338417183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1338417183
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3617837478
Short name T21
Test name
Test status
Simulation time 680409146628 ps
CPU time 1593.03 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 01:08:52 PM PDT 23
Peak memory 222852 kb
Host smart-7c33282b-a3c7-45ba-a4de-93918561b6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617837478 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3617837478
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2029345950
Short name T28
Test name
Test status
Simulation time 17404355 ps
CPU time 0.91 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214740 kb
Host smart-594290f0-243e-4be0-8e6c-4dc917f15a76
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029345950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2029345950
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3724412999
Short name T153
Test name
Test status
Simulation time 211507310 ps
CPU time 1.05 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 214664 kb
Host smart-6fbd8d94-a94a-47e6-95da-c5a316cbfb83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724412999 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3724412999
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3338629108
Short name T262
Test name
Test status
Simulation time 76480801 ps
CPU time 1.48 seconds
Started Oct 01 12:42:53 PM PDT 23
Finished Oct 01 12:42:55 PM PDT 23
Peak memory 205892 kb
Host smart-61fab12b-1bbf-4fca-8500-44e38a16c056
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338629108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3338629108
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4288780255
Short name T32
Test name
Test status
Simulation time 35601490 ps
CPU time 1.3 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 214416 kb
Host smart-f2761a50-aaef-4f0e-99ed-e87e19637a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288780255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4288780255
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.1030774871
Short name T91
Test name
Test status
Simulation time 11725761 ps
CPU time 0.86 seconds
Started Oct 01 12:41:42 PM PDT 23
Finished Oct 01 12:41:48 PM PDT 23
Peak memory 214332 kb
Host smart-75acf6f0-1b92-467b-9fd7-9780e58ec0b5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030774871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1030774871
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3870091961
Short name T138
Test name
Test status
Simulation time 85050321 ps
CPU time 1.09 seconds
Started Oct 01 12:42:55 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 214540 kb
Host smart-dbbce9fe-0f1b-4114-b297-0e253cfaeda8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870091961 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3870091961
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_disable.180527380
Short name T125
Test name
Test status
Simulation time 21494170 ps
CPU time 0.83 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:46 PM PDT 23
Peak memory 214472 kb
Host smart-7a94650c-ae80-446d-b429-fd5f492ac5ee
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180527380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.180527380
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.2989794903
Short name T85
Test name
Test status
Simulation time 12417144 ps
CPU time 0.88 seconds
Started Oct 01 12:41:55 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 214536 kb
Host smart-8ec1d64a-8426-437e-a15f-b6ca0e8580f1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989794903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2989794903
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1171870181
Short name T201
Test name
Test status
Simulation time 19263309 ps
CPU time 0.84 seconds
Started Oct 01 12:44:09 PM PDT 23
Finished Oct 01 12:44:11 PM PDT 23
Peak memory 205716 kb
Host smart-d1563cd9-49f3-4fdc-9789-58d70cd4b145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171870181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1171870181
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/default/3.edn_disable.1949506205
Short name T82
Test name
Test status
Simulation time 63340778 ps
CPU time 0.84 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 214484 kb
Host smart-4a93ffdf-8335-4a66-bd84-345c114d012b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949506205 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1949506205
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3409024721
Short name T239
Test name
Test status
Simulation time 100052284745 ps
CPU time 1002.29 seconds
Started Oct 01 12:42:06 PM PDT 23
Finished Oct 01 12:58:49 PM PDT 23
Peak memory 216408 kb
Host smart-2d5283be-2ed5-45de-ac5e-ead21dd2d48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409024721 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3409024721
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_intr.1521634651
Short name T104
Test name
Test status
Simulation time 23399280 ps
CPU time 0.89 seconds
Started Oct 01 12:41:37 PM PDT 23
Finished Oct 01 12:41:38 PM PDT 23
Peak memory 214696 kb
Host smart-611b5267-af36-46c8-a630-75887847d4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521634651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1521634651
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2086356260
Short name T84
Test name
Test status
Simulation time 29937569 ps
CPU time 0.9 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 214644 kb
Host smart-20961045-93d9-44e3-bedf-13ed82d5b597
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086356260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2086356260
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/54.edn_err.2776533671
Short name T41
Test name
Test status
Simulation time 19565238 ps
CPU time 1.37 seconds
Started Oct 01 12:42:34 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 222200 kb
Host smart-11da67a2-4097-4c51-9c64-0cd2ac91e61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776533671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2776533671
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/6.edn_regwen.1739046338
Short name T287
Test name
Test status
Simulation time 25180785 ps
CPU time 0.86 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 12:41:25 PM PDT 23
Peak memory 204752 kb
Host smart-b071de22-a7a9-4e2f-844e-fd44c40a939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739046338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1739046338
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_genbits.4000333865
Short name T254
Test name
Test status
Simulation time 54719048 ps
CPU time 0.92 seconds
Started Oct 01 12:41:33 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 205472 kb
Host smart-401df81d-0325-4e0d-84d4-99c74b34f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000333865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4000333865
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.4207410768
Short name T23
Test name
Test status
Simulation time 45895914 ps
CPU time 0.8 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:26 PM PDT 23
Peak memory 214488 kb
Host smart-b1fc37fc-5249-43f0-9320-100b03559eec
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207410768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4207410768
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.3182890720
Short name T172
Test name
Test status
Simulation time 10300983 ps
CPU time 0.82 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214424 kb
Host smart-71cfecd8-fecd-45e5-998a-bff43ecdae66
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182890720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3182890720
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1934520284
Short name T154
Test name
Test status
Simulation time 38568605 ps
CPU time 1 seconds
Started Oct 01 12:41:40 PM PDT 23
Finished Oct 01 12:41:42 PM PDT 23
Peak memory 214656 kb
Host smart-8b35a68d-3e0d-4019-a733-517912ec960c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934520284 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1934520284
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.1141054606
Short name T628
Test name
Test status
Simulation time 19555439 ps
CPU time 0.83 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:53 PM PDT 23
Peak memory 214412 kb
Host smart-047dc437-cff9-4b55-ad9f-58c66dcea7f1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141054606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1141054606
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.4063198185
Short name T160
Test name
Test status
Simulation time 86522832 ps
CPU time 0.82 seconds
Started Oct 01 12:41:55 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 214472 kb
Host smart-519a6196-0342-4505-9d20-2d1fa9b1202f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063198185 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.4063198185
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.3489693849
Short name T167
Test name
Test status
Simulation time 38462241 ps
CPU time 0.82 seconds
Started Oct 01 12:42:02 PM PDT 23
Finished Oct 01 12:42:03 PM PDT 23
Peak memory 214404 kb
Host smart-e114a60c-629b-45fd-af9d-40db3db61dfe
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489693849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3489693849
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.2567187098
Short name T233
Test name
Test status
Simulation time 34455226 ps
CPU time 0.83 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 214476 kb
Host smart-8bb3f254-f40d-48c6-be50-d51f3e0aea6e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567187098 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2567187098
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/14.edn_alert.1686528525
Short name T283
Test name
Test status
Simulation time 63732374 ps
CPU time 0.93 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 205112 kb
Host smart-e00f2fa6-e8c2-4c03-b89c-b67bb7170466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686528525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1686528525
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert.1658961944
Short name T86
Test name
Test status
Simulation time 19342614 ps
CPU time 0.93 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:11 PM PDT 23
Peak memory 205120 kb
Host smart-39fb4d6b-6d77-4022-87cf-dde36ad68f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658961944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1658961944
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.3641702004
Short name T279
Test name
Test status
Simulation time 108338808 ps
CPU time 0.93 seconds
Started Oct 01 12:41:49 PM PDT 23
Finished Oct 01 12:41:50 PM PDT 23
Peak memory 205172 kb
Host smart-1c4dfaea-1398-404f-9b01-10bd36ae2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641702004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3641702004
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/14.edn_genbits.3118530821
Short name T24
Test name
Test status
Simulation time 20214361 ps
CPU time 0.83 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 204840 kb
Host smart-4de6a3de-a3cc-4978-b704-bb8859b3efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118530821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3118530821
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all.2034477053
Short name T113
Test name
Test status
Simulation time 129109105 ps
CPU time 2.02 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 205340 kb
Host smart-dd3fe5cd-03ce-4a97-b38d-d9e3bebb73ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034477053 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2034477053
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_alert_test.3533405547
Short name T69
Test name
Test status
Simulation time 115140588 ps
CPU time 0.86 seconds
Started Oct 01 12:41:48 PM PDT 23
Finished Oct 01 12:41:49 PM PDT 23
Peak memory 205352 kb
Host smart-ad61daa4-3d72-4cab-a785-eee0728c07ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533405547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3533405547
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_genbits.3268961051
Short name T78
Test name
Test status
Simulation time 84211508 ps
CPU time 1.44 seconds
Started Oct 01 12:41:35 PM PDT 23
Finished Oct 01 12:41:37 PM PDT 23
Peak memory 214412 kb
Host smart-01835fe5-7a65-4e83-898e-9a398d1ab49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268961051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3268961051
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_err.567982336
Short name T101
Test name
Test status
Simulation time 67357906 ps
CPU time 1.02 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 215864 kb
Host smart-679a0705-96b3-4f3d-8146-a406918f84a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567982336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.567982336
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3653838160
Short name T257
Test name
Test status
Simulation time 35076704139 ps
CPU time 354.74 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:47:29 PM PDT 23
Peak memory 214624 kb
Host smart-60a9dcff-04d0-4471-b603-95e0cc645eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653838160 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3653838160
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_genbits.3108589244
Short name T52
Test name
Test status
Simulation time 116106420 ps
CPU time 0.93 seconds
Started Oct 01 12:41:45 PM PDT 23
Finished Oct 01 12:41:46 PM PDT 23
Peak memory 205032 kb
Host smart-e01cff3f-1f9a-4e09-92a3-cb9fa90fef06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108589244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3108589244
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_regwen.2549222426
Short name T284
Test name
Test status
Simulation time 78368499 ps
CPU time 0.81 seconds
Started Oct 01 12:41:17 PM PDT 23
Finished Oct 01 12:41:18 PM PDT 23
Peak memory 205072 kb
Host smart-55e8519e-fdcb-410d-a220-d17e9e188ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549222426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2549222426
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/34.edn_stress_all.3485517329
Short name T200
Test name
Test status
Simulation time 365218875 ps
CPU time 2.38 seconds
Started Oct 01 12:42:00 PM PDT 23
Finished Oct 01 12:42:02 PM PDT 23
Peak memory 205600 kb
Host smart-109d6d72-36a1-49ec-b392-61a1dbc87c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485517329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3485517329
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_genbits.560617369
Short name T53
Test name
Test status
Simulation time 144986554 ps
CPU time 1.54 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214368 kb
Host smart-f44a92b2-b360-4ff9-be3e-f33051eca322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560617369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.560617369
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3819025254
Short name T250
Test name
Test status
Simulation time 49474859 ps
CPU time 1.49 seconds
Started Oct 01 12:42:54 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 205760 kb
Host smart-aabd10c8-6243-4cf4-8862-45863f2aa88e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819025254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3819025254
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_alert.1570377884
Short name T248
Test name
Test status
Simulation time 117224435 ps
CPU time 0.97 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:53 PM PDT 23
Peak memory 205244 kb
Host smart-dce3a30d-1dbd-4c61-8069-f1f4f9bb437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570377884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1570377884
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert.1711909876
Short name T654
Test name
Test status
Simulation time 19805927 ps
CPU time 0.99 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 206008 kb
Host smart-3f79980d-1355-4f35-95ad-79b37cb84620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711909876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1711909876
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/2.edn_genbits.1487280017
Short name T258
Test name
Test status
Simulation time 27156747 ps
CPU time 0.96 seconds
Started Oct 01 12:41:27 PM PDT 23
Finished Oct 01 12:41:28 PM PDT 23
Peak memory 205556 kb
Host smart-65a0b7bb-8515-45de-a40b-919aaf8c450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487280017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1487280017
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.335089014
Short name T273
Test name
Test status
Simulation time 45121177 ps
CPU time 1.04 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214744 kb
Host smart-9a4ac5de-8c59-40be-836c-382858d673a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335089014 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.335089014
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_genbits.1990320933
Short name T8
Test name
Test status
Simulation time 25740397 ps
CPU time 1.34 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 214312 kb
Host smart-391cff3a-a0ed-4140-b935-32dac906326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990320933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1990320933
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_genbits.1637796444
Short name T190
Test name
Test status
Simulation time 51648380 ps
CPU time 0.89 seconds
Started Oct 01 12:42:29 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 205104 kb
Host smart-3f863814-11b7-45ac-9d51-1ed02f4775ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637796444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1637796444
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_genbits.2255301776
Short name T62
Test name
Test status
Simulation time 21984411 ps
CPU time 0.99 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 214408 kb
Host smart-8c68043f-fddf-4b2a-873b-fb061b0a2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255301776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2255301776
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_genbits.3647297133
Short name T256
Test name
Test status
Simulation time 21317786 ps
CPU time 1.26 seconds
Started Oct 01 12:41:28 PM PDT 23
Finished Oct 01 12:41:29 PM PDT 23
Peak memory 205608 kb
Host smart-82abade0-ecf2-44b5-92e0-ca99ad71c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647297133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3647297133
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.567801109
Short name T111
Test name
Test status
Simulation time 93500741 ps
CPU time 1.18 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 214592 kb
Host smart-212b96a2-88b1-434e-bb7d-13153e31968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567801109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.567801109
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.118587565
Short name T105
Test name
Test status
Simulation time 17763062 ps
CPU time 1.06 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:54 PM PDT 23
Peak memory 225636 kb
Host smart-211ae4b6-f3dd-4daf-b93c-9788d1f93a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118587565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.118587565
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/23.edn_intr.4112536224
Short name T108
Test name
Test status
Simulation time 33396586 ps
CPU time 0.81 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 214628 kb
Host smart-9350ff2c-17f6-474c-a025-91c4ddc527d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112536224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4112536224
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.2573577771
Short name T127
Test name
Test status
Simulation time 11391611 ps
CPU time 0.81 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 214440 kb
Host smart-85d91bbe-a9d7-49b5-8e2f-12d8a662d917
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573577771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2573577771
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3304554833
Short name T117
Test name
Test status
Simulation time 69310880 ps
CPU time 1.16 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 214668 kb
Host smart-48e4b6dd-3fd3-4cbb-8924-17f8f0177bd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304554833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3304554833
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.1342122010
Short name T124
Test name
Test status
Simulation time 15689394 ps
CPU time 0.79 seconds
Started Oct 01 12:41:12 PM PDT 23
Finished Oct 01 12:41:13 PM PDT 23
Peak memory 206156 kb
Host smart-f12178da-1df9-4813-ae6a-136964dab06a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342122010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1342122010
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable.1854530825
Short name T34
Test name
Test status
Simulation time 13313544 ps
CPU time 0.87 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214488 kb
Host smart-229c7eac-88eb-47e4-8032-54d14823b1e7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854530825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1854530825
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2372111747
Short name T446
Test name
Test status
Simulation time 25534812 ps
CPU time 1.11 seconds
Started Oct 01 12:18:26 PM PDT 23
Finished Oct 01 12:18:27 PM PDT 23
Peak memory 205496 kb
Host smart-6a20b876-daec-42e4-af30-5458932f6b81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372111747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2372111747
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2201942887
Short name T215
Test name
Test status
Simulation time 122850091 ps
CPU time 2 seconds
Started Oct 01 12:19:26 PM PDT 23
Finished Oct 01 12:19:28 PM PDT 23
Peak memory 204916 kb
Host smart-a651eead-2930-4056-b526-56e95b18833f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201942887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2201942887
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3638897611
Short name T378
Test name
Test status
Simulation time 19349870 ps
CPU time 0.88 seconds
Started Oct 01 12:15:50 PM PDT 23
Finished Oct 01 12:15:51 PM PDT 23
Peak memory 205528 kb
Host smart-3534ed61-5e85-4876-95b6-68451091966b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638897611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3638897611
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.659052708
Short name T376
Test name
Test status
Simulation time 22996756 ps
CPU time 0.98 seconds
Started Oct 01 12:15:32 PM PDT 23
Finished Oct 01 12:15:33 PM PDT 23
Peak memory 213972 kb
Host smart-83905f2b-e4df-4d56-a46b-da14ed8cbf5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659052708 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.659052708
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3102212526
Short name T202
Test name
Test status
Simulation time 29677848 ps
CPU time 0.83 seconds
Started Oct 01 12:15:37 PM PDT 23
Finished Oct 01 12:15:38 PM PDT 23
Peak memory 205860 kb
Host smart-06e53859-5b87-4ad0-852b-bf5e047971fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102212526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3102212526
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.569314573
Short name T223
Test name
Test status
Simulation time 17039661 ps
CPU time 0.73 seconds
Started Oct 01 12:21:32 PM PDT 23
Finished Oct 01 12:21:32 PM PDT 23
Peak memory 205416 kb
Host smart-fb328ac5-ef8a-48c9-bdf1-d1e2df87382a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569314573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.569314573
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3834939143
Short name T187
Test name
Test status
Simulation time 117934069 ps
CPU time 1.19 seconds
Started Oct 01 12:19:46 PM PDT 23
Finished Oct 01 12:19:48 PM PDT 23
Peak memory 205416 kb
Host smart-1fe2e2b0-9758-4a70-ae62-ae24aeb37c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834939143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3834939143
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2032815019
Short name T418
Test name
Test status
Simulation time 401294349 ps
CPU time 3.22 seconds
Started Oct 01 12:20:58 PM PDT 23
Finished Oct 01 12:21:01 PM PDT 23
Peak memory 213828 kb
Host smart-aa9d35be-6c8f-4cb4-8be4-87f656b8f2b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032815019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2032815019
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3915771546
Short name T377
Test name
Test status
Simulation time 92927458 ps
CPU time 1.5 seconds
Started Oct 01 12:19:39 PM PDT 23
Finished Oct 01 12:19:41 PM PDT 23
Peak memory 204272 kb
Host smart-7e04a946-5a4f-4f39-8bbc-88b49a35ca6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915771546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3915771546
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2446810977
Short name T213
Test name
Test status
Simulation time 35595479 ps
CPU time 1.39 seconds
Started Oct 01 12:43:20 PM PDT 23
Finished Oct 01 12:43:22 PM PDT 23
Peak memory 205872 kb
Host smart-33b49b62-2499-48b7-9ff6-7c4dcfad65be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446810977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2446810977
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2491124760
Short name T428
Test name
Test status
Simulation time 350509679 ps
CPU time 5.06 seconds
Started Oct 01 12:43:55 PM PDT 23
Finished Oct 01 12:44:00 PM PDT 23
Peak memory 205796 kb
Host smart-d9921e5c-5a11-4522-bab6-356943e19c05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491124760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2491124760
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2291110013
Short name T449
Test name
Test status
Simulation time 14529066 ps
CPU time 0.85 seconds
Started Oct 01 12:43:32 PM PDT 23
Finished Oct 01 12:43:33 PM PDT 23
Peak memory 205836 kb
Host smart-2b51cb4c-262b-43a8-9a1a-81a2d54e0f43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291110013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2291110013
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2828529125
Short name T394
Test name
Test status
Simulation time 324732086 ps
CPU time 1.38 seconds
Started Oct 01 12:43:16 PM PDT 23
Finished Oct 01 12:43:17 PM PDT 23
Peak memory 214032 kb
Host smart-bc0be233-9969-4559-8184-92cf9cc9b24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828529125 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2828529125
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2124273535
Short name T382
Test name
Test status
Simulation time 55970131 ps
CPU time 0.86 seconds
Started Oct 01 12:43:00 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 205816 kb
Host smart-9a395fd7-13f1-4f3a-be4d-9d9586366940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124273535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2124273535
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3438999522
Short name T414
Test name
Test status
Simulation time 42737192 ps
CPU time 0.79 seconds
Started Oct 01 12:43:08 PM PDT 23
Finished Oct 01 12:43:11 PM PDT 23
Peak memory 205548 kb
Host smart-6aabd3ea-e8c6-4b40-a6da-ecdd056f34ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438999522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3438999522
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2963781433
Short name T188
Test name
Test status
Simulation time 352154783 ps
CPU time 1.31 seconds
Started Oct 01 12:43:49 PM PDT 23
Finished Oct 01 12:43:50 PM PDT 23
Peak memory 205780 kb
Host smart-42d96452-a532-4815-ade4-168cd0226aa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963781433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2963781433
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1155590874
Short name T401
Test name
Test status
Simulation time 106278780 ps
CPU time 1.76 seconds
Started Oct 01 12:18:33 PM PDT 23
Finished Oct 01 12:18:36 PM PDT 23
Peak memory 213856 kb
Host smart-1d542300-72c2-49cc-92c3-7493f419a09f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155590874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1155590874
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2309693013
Short name T355
Test name
Test status
Simulation time 23647211 ps
CPU time 1.63 seconds
Started Oct 01 12:43:23 PM PDT 23
Finished Oct 01 12:43:25 PM PDT 23
Peak memory 214084 kb
Host smart-90f09981-ca12-4005-bfba-ba4714b74cae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309693013 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2309693013
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2963370520
Short name T352
Test name
Test status
Simulation time 69548827 ps
CPU time 0.79 seconds
Started Oct 01 12:42:48 PM PDT 23
Finished Oct 01 12:42:49 PM PDT 23
Peak memory 205740 kb
Host smart-c4511e5a-e068-4a39-9fba-7ca1a31a4b07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963370520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2963370520
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2221480198
Short name T221
Test name
Test status
Simulation time 15867880 ps
CPU time 0.89 seconds
Started Oct 01 12:42:54 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 205760 kb
Host smart-ebb3a990-10d0-4b96-9bf5-22fc7517e5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221480198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2221480198
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.704083171
Short name T389
Test name
Test status
Simulation time 42290576 ps
CPU time 0.89 seconds
Started Oct 01 12:43:26 PM PDT 23
Finished Oct 01 12:43:28 PM PDT 23
Peak memory 205732 kb
Host smart-c9de7360-c99c-4fcb-a1de-9394dd6c45a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704083171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.704083171
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2107855831
Short name T438
Test name
Test status
Simulation time 44517013 ps
CPU time 1.87 seconds
Started Oct 01 12:42:56 PM PDT 23
Finished Oct 01 12:42:58 PM PDT 23
Peak memory 214040 kb
Host smart-b18b556e-b175-485e-b6bd-3daf2ad1fec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107855831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2107855831
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.794145590
Short name T397
Test name
Test status
Simulation time 49995526 ps
CPU time 1.01 seconds
Started Oct 01 12:43:03 PM PDT 23
Finished Oct 01 12:43:05 PM PDT 23
Peak memory 214000 kb
Host smart-2671fee1-68a7-48ff-84c7-51838190f136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794145590 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.794145590
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4165861954
Short name T209
Test name
Test status
Simulation time 46365325 ps
CPU time 0.8 seconds
Started Oct 01 12:42:59 PM PDT 23
Finished Oct 01 12:43:00 PM PDT 23
Peak memory 205736 kb
Host smart-d0ad37d3-c49b-48fc-a798-1c5adb0769ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165861954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4165861954
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4251381270
Short name T399
Test name
Test status
Simulation time 13880616 ps
CPU time 0.82 seconds
Started Oct 01 12:43:01 PM PDT 23
Finished Oct 01 12:43:02 PM PDT 23
Peak memory 205692 kb
Host smart-2d89b279-79fc-47e0-a29c-ba90cd98ce34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251381270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4251381270
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4210168476
Short name T425
Test name
Test status
Simulation time 82466596 ps
CPU time 0.89 seconds
Started Oct 01 12:43:46 PM PDT 23
Finished Oct 01 12:43:47 PM PDT 23
Peak memory 205880 kb
Host smart-9b84457f-8882-49c6-8844-61afefcbcc12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210168476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4210168476
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3814855139
Short name T361
Test name
Test status
Simulation time 70080640 ps
CPU time 1.43 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:46 PM PDT 23
Peak memory 213936 kb
Host smart-873d765d-5dd9-4c1c-aa63-4c461a40b175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814855139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3814855139
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2502104638
Short name T406
Test name
Test status
Simulation time 63842900 ps
CPU time 1.66 seconds
Started Oct 01 12:42:58 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 205896 kb
Host smart-c4bfd699-57cb-4f72-bf51-c2c702043e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502104638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2502104638
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2680864452
Short name T405
Test name
Test status
Simulation time 25749561 ps
CPU time 1.2 seconds
Started Oct 01 12:42:59 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 214016 kb
Host smart-3ef1f4cf-ff3b-4ac3-b6a2-0719d57881a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680864452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2680864452
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4253529738
Short name T400
Test name
Test status
Simulation time 25307260 ps
CPU time 0.79 seconds
Started Oct 01 12:43:14 PM PDT 23
Finished Oct 01 12:43:15 PM PDT 23
Peak memory 205616 kb
Host smart-0619e0db-07dd-4135-8041-3340959aaa28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253529738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4253529738
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.165388557
Short name T328
Test name
Test status
Simulation time 11779791 ps
CPU time 0.84 seconds
Started Oct 01 12:43:07 PM PDT 23
Finished Oct 01 12:43:10 PM PDT 23
Peak memory 205692 kb
Host smart-d55ad006-3ee7-4e98-815b-70dd28da02d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165388557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.165388557
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1215492627
Short name T203
Test name
Test status
Simulation time 25372320 ps
CPU time 0.94 seconds
Started Oct 01 12:43:06 PM PDT 23
Finished Oct 01 12:43:07 PM PDT 23
Peak memory 205724 kb
Host smart-690c0c3b-f423-4889-b943-8efc48753e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215492627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1215492627
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2453339875
Short name T391
Test name
Test status
Simulation time 66858052 ps
CPU time 1.43 seconds
Started Oct 01 12:43:15 PM PDT 23
Finished Oct 01 12:43:17 PM PDT 23
Peak memory 214036 kb
Host smart-24789bc2-c1a7-4678-99e7-22410d343c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453339875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2453339875
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4141239098
Short name T264
Test name
Test status
Simulation time 80979200 ps
CPU time 2.25 seconds
Started Oct 01 12:43:09 PM PDT 23
Finished Oct 01 12:43:12 PM PDT 23
Peak memory 205724 kb
Host smart-81e697fc-a1f7-44a5-97b7-ce2254bb22ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141239098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4141239098
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3489710205
Short name T396
Test name
Test status
Simulation time 21920558 ps
CPU time 0.88 seconds
Started Oct 01 12:43:16 PM PDT 23
Finished Oct 01 12:43:17 PM PDT 23
Peak memory 205816 kb
Host smart-0987b9d1-d2fe-4aac-9db6-c481546958a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489710205 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3489710205
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2169258317
Short name T211
Test name
Test status
Simulation time 24653497 ps
CPU time 0.86 seconds
Started Oct 01 12:43:07 PM PDT 23
Finished Oct 01 12:43:08 PM PDT 23
Peak memory 205708 kb
Host smart-0a0650f5-04e0-4956-9b99-6f01b7585e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169258317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2169258317
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2951932865
Short name T385
Test name
Test status
Simulation time 13148900 ps
CPU time 0.86 seconds
Started Oct 01 12:43:18 PM PDT 23
Finished Oct 01 12:43:19 PM PDT 23
Peak memory 205684 kb
Host smart-b7df2570-9138-4731-bc9c-82a0f98d8beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951932865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2951932865
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3716431466
Short name T338
Test name
Test status
Simulation time 31259229 ps
CPU time 1.27 seconds
Started Oct 01 12:43:16 PM PDT 23
Finished Oct 01 12:43:18 PM PDT 23
Peak memory 205752 kb
Host smart-05c3206f-f2fb-4f72-88a9-73499361c22c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716431466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3716431466
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1362491617
Short name T435
Test name
Test status
Simulation time 1201766717 ps
CPU time 3.49 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:54 PM PDT 23
Peak memory 213952 kb
Host smart-9449fe11-6fbc-4ef9-9ea8-d8e9f9aafc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362491617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1362491617
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.559327197
Short name T441
Test name
Test status
Simulation time 94523926 ps
CPU time 2.36 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:07 PM PDT 23
Peak memory 205780 kb
Host smart-d4e11cf6-6e17-46f8-bf40-a40f73346532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559327197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.559327197
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2987487650
Short name T344
Test name
Test status
Simulation time 21266657 ps
CPU time 0.92 seconds
Started Oct 01 12:43:48 PM PDT 23
Finished Oct 01 12:43:50 PM PDT 23
Peak memory 205780 kb
Host smart-b6d887b5-236d-4b8b-837a-7c43122a6071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987487650 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2987487650
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.275430718
Short name T195
Test name
Test status
Simulation time 23456853 ps
CPU time 0.82 seconds
Started Oct 01 12:44:09 PM PDT 23
Finished Oct 01 12:44:10 PM PDT 23
Peak memory 205816 kb
Host smart-578fd678-7479-4c38-a281-ca34021d0114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275430718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.275430718
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2959477597
Short name T403
Test name
Test status
Simulation time 11602836 ps
CPU time 0.86 seconds
Started Oct 01 12:43:44 PM PDT 23
Finished Oct 01 12:43:45 PM PDT 23
Peak memory 205696 kb
Host smart-04391b6b-4dad-4d18-a8e3-13e79476f41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959477597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2959477597
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3163331064
Short name T443
Test name
Test status
Simulation time 28426247 ps
CPU time 1.03 seconds
Started Oct 01 12:43:15 PM PDT 23
Finished Oct 01 12:43:17 PM PDT 23
Peak memory 205812 kb
Host smart-8e2043a5-24d7-45ff-a857-6f59ea4472ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163331064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3163331064
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2250981278
Short name T220
Test name
Test status
Simulation time 116077568 ps
CPU time 2.01 seconds
Started Oct 01 12:43:23 PM PDT 23
Finished Oct 01 12:43:25 PM PDT 23
Peak memory 214008 kb
Host smart-a7e66fee-a6b3-490b-b6af-43713e31d881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250981278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2250981278
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3409122244
Short name T362
Test name
Test status
Simulation time 99869281 ps
CPU time 2.51 seconds
Started Oct 01 12:43:57 PM PDT 23
Finished Oct 01 12:44:00 PM PDT 23
Peak memory 205896 kb
Host smart-1a19f99a-1266-4faf-95f7-eaa82c68bc33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409122244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3409122244
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.207491690
Short name T218
Test name
Test status
Simulation time 33186933 ps
CPU time 1.84 seconds
Started Oct 01 12:43:39 PM PDT 23
Finished Oct 01 12:43:41 PM PDT 23
Peak memory 214076 kb
Host smart-df0e3aa6-b9c6-4964-90b5-6e7a9da073f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207491690 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.207491690
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2019920343
Short name T217
Test name
Test status
Simulation time 15491686 ps
CPU time 0.92 seconds
Started Oct 01 12:43:43 PM PDT 23
Finished Oct 01 12:43:44 PM PDT 23
Peak memory 205828 kb
Host smart-a3265357-ede9-4358-9570-424cd19f2598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019920343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2019920343
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1261485847
Short name T374
Test name
Test status
Simulation time 23101125 ps
CPU time 0.83 seconds
Started Oct 01 12:43:50 PM PDT 23
Finished Oct 01 12:43:51 PM PDT 23
Peak memory 205708 kb
Host smart-eb4e5386-9180-403a-9669-a6781fd4cdda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261485847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1261485847
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.258137047
Short name T208
Test name
Test status
Simulation time 27438451 ps
CPU time 0.94 seconds
Started Oct 01 12:43:22 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 205884 kb
Host smart-3338004c-18cc-4278-8896-c9439621140b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258137047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.258137047
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2811188533
Short name T360
Test name
Test status
Simulation time 186692012 ps
CPU time 3.18 seconds
Started Oct 01 12:43:21 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 213964 kb
Host smart-b688e1b5-a44a-489e-a9d6-cde7e8362f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811188533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2811188533
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2985887957
Short name T379
Test name
Test status
Simulation time 324531201 ps
CPU time 1.3 seconds
Started Oct 01 12:43:21 PM PDT 23
Finished Oct 01 12:43:23 PM PDT 23
Peak memory 205828 kb
Host smart-efc092fa-3267-4a64-bc05-26fa8e9df700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985887957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2985887957
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3889619141
Short name T434
Test name
Test status
Simulation time 40571205 ps
CPU time 0.94 seconds
Started Oct 01 12:44:13 PM PDT 23
Finished Oct 01 12:44:14 PM PDT 23
Peak memory 205896 kb
Host smart-ad5b5e43-18ea-4c92-95ac-a7f98b8a4473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889619141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3889619141
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1341369590
Short name T433
Test name
Test status
Simulation time 51303308 ps
CPU time 0.89 seconds
Started Oct 01 12:44:04 PM PDT 23
Finished Oct 01 12:44:06 PM PDT 23
Peak memory 205848 kb
Host smart-7d2d439a-3ab0-4569-b772-774cd4076c98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341369590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1341369590
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.100185572
Short name T340
Test name
Test status
Simulation time 28126685 ps
CPU time 0.76 seconds
Started Oct 01 12:43:45 PM PDT 23
Finished Oct 01 12:43:46 PM PDT 23
Peak memory 205600 kb
Host smart-0c5b8439-1f23-4df0-9d57-f3251d137282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100185572 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.100185572
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3497421075
Short name T186
Test name
Test status
Simulation time 86471004 ps
CPU time 1.2 seconds
Started Oct 01 12:43:53 PM PDT 23
Finished Oct 01 12:43:54 PM PDT 23
Peak memory 205816 kb
Host smart-51f9b07f-d26a-409e-a30e-c5af2523ff73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497421075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3497421075
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1374154422
Short name T384
Test name
Test status
Simulation time 194842645 ps
CPU time 3.36 seconds
Started Oct 01 12:44:05 PM PDT 23
Finished Oct 01 12:44:09 PM PDT 23
Peak memory 214080 kb
Host smart-f006fb08-e6bf-4b4f-8389-a9671342f0aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374154422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1374154422
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.218007458
Short name T413
Test name
Test status
Simulation time 277556131 ps
CPU time 2.93 seconds
Started Oct 01 12:44:05 PM PDT 23
Finished Oct 01 12:44:08 PM PDT 23
Peak memory 205708 kb
Host smart-38411569-4420-4ee0-bbe4-1fa7d36d2075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218007458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.218007458
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4260142925
Short name T429
Test name
Test status
Simulation time 165588522 ps
CPU time 1.63 seconds
Started Oct 01 12:44:09 PM PDT 23
Finished Oct 01 12:44:11 PM PDT 23
Peak memory 214088 kb
Host smart-4f0b341f-16d2-4463-96b0-0b21f9957035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260142925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4260142925
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.321315045
Short name T439
Test name
Test status
Simulation time 21283105 ps
CPU time 0.86 seconds
Started Oct 01 12:43:55 PM PDT 23
Finished Oct 01 12:43:56 PM PDT 23
Peak memory 205708 kb
Host smart-a59eb806-3925-4857-81d9-b5eff35fb39a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321315045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.321315045
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3531325411
Short name T440
Test name
Test status
Simulation time 55289312 ps
CPU time 1.1 seconds
Started Oct 01 12:44:04 PM PDT 23
Finished Oct 01 12:44:06 PM PDT 23
Peak memory 205748 kb
Host smart-9f88bc1b-b64c-47e0-8a86-76eb3967072a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531325411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3531325411
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.922113980
Short name T393
Test name
Test status
Simulation time 681199503 ps
CPU time 2.57 seconds
Started Oct 01 12:44:07 PM PDT 23
Finished Oct 01 12:44:10 PM PDT 23
Peak memory 214136 kb
Host smart-930a59e1-28df-4aba-acbe-da6ad0fc1699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922113980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.922113980
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2744038392
Short name T404
Test name
Test status
Simulation time 149482796 ps
CPU time 2.06 seconds
Started Oct 01 12:44:15 PM PDT 23
Finished Oct 01 12:44:17 PM PDT 23
Peak memory 205772 kb
Host smart-4a8d7422-ad7b-4825-8dc6-d55313323f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744038392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2744038392
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.4023650105
Short name T189
Test name
Test status
Simulation time 44236361 ps
CPU time 1.27 seconds
Started Oct 01 12:43:09 PM PDT 23
Finished Oct 01 12:43:11 PM PDT 23
Peak memory 214036 kb
Host smart-32fc1d36-17e5-462c-ae0b-aa812813ac9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023650105 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.4023650105
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3734348704
Short name T214
Test name
Test status
Simulation time 18568164 ps
CPU time 0.84 seconds
Started Oct 01 12:44:24 PM PDT 23
Finished Oct 01 12:44:25 PM PDT 23
Peak memory 205772 kb
Host smart-2c82069e-746d-43ed-8f0c-a27c406ee2d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734348704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3734348704
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3993087393
Short name T388
Test name
Test status
Simulation time 16289158 ps
CPU time 0.91 seconds
Started Oct 01 12:45:12 PM PDT 23
Finished Oct 01 12:45:18 PM PDT 23
Peak memory 205724 kb
Host smart-ec848cbb-3011-477e-ae6d-aa258744fc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993087393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3993087393
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.492326023
Short name T415
Test name
Test status
Simulation time 32889032 ps
CPU time 1.39 seconds
Started Oct 01 12:43:29 PM PDT 23
Finished Oct 01 12:43:31 PM PDT 23
Peak memory 205788 kb
Host smart-cc9fad8d-5fe7-487c-a880-58ee555e48c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492326023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.492326023
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3455738414
Short name T448
Test name
Test status
Simulation time 100553164 ps
CPU time 2.11 seconds
Started Oct 01 12:45:22 PM PDT 23
Finished Oct 01 12:45:24 PM PDT 23
Peak memory 214084 kb
Host smart-6c0204b5-9c5b-41fc-8217-d6ff563d668f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455738414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3455738414
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1574940821
Short name T419
Test name
Test status
Simulation time 130493283 ps
CPU time 2.8 seconds
Started Oct 01 12:44:24 PM PDT 23
Finished Oct 01 12:44:27 PM PDT 23
Peak memory 205880 kb
Host smart-3e47bbf9-06c3-4947-8b29-d3e7afd42139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574940821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1574940821
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1873564512
Short name T423
Test name
Test status
Simulation time 35992215 ps
CPU time 1.07 seconds
Started Oct 01 12:43:47 PM PDT 23
Finished Oct 01 12:43:48 PM PDT 23
Peak memory 214168 kb
Host smart-92fa062f-2b29-4670-955c-e35effe4e897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873564512 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1873564512
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3616995166
Short name T386
Test name
Test status
Simulation time 120977106 ps
CPU time 0.83 seconds
Started Oct 01 12:43:47 PM PDT 23
Finished Oct 01 12:43:48 PM PDT 23
Peak memory 205800 kb
Host smart-ba2fb4d5-28d7-4373-bb0a-1c4716b3e7e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616995166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3616995166
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1204633389
Short name T334
Test name
Test status
Simulation time 12072627 ps
CPU time 0.76 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:06 PM PDT 23
Peak memory 205564 kb
Host smart-8e25146d-5f1c-4fcd-bb0d-7e24deb25992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204633389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1204633389
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2224980928
Short name T207
Test name
Test status
Simulation time 46734644 ps
CPU time 0.89 seconds
Started Oct 01 12:43:50 PM PDT 23
Finished Oct 01 12:43:51 PM PDT 23
Peak memory 205820 kb
Host smart-46116b1f-c512-4ec4-a524-fc9c255fa1fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224980928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2224980928
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.896262210
Short name T185
Test name
Test status
Simulation time 110069402 ps
CPU time 3.46 seconds
Started Oct 01 12:43:19 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 214092 kb
Host smart-133b9650-2e44-4723-a27c-c74d1a9bcea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896262210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.896262210
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3126847074
Short name T249
Test name
Test status
Simulation time 230582113 ps
CPU time 2.2 seconds
Started Oct 01 12:43:22 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 205828 kb
Host smart-858f97d3-fc21-4796-8e96-6e607a91df1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126847074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3126847074
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.524163512
Short name T210
Test name
Test status
Simulation time 27423548 ps
CPU time 1.06 seconds
Started Oct 01 12:43:55 PM PDT 23
Finished Oct 01 12:43:57 PM PDT 23
Peak memory 205836 kb
Host smart-8e6944a9-c554-4dba-821a-fb7f6265bb92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524163512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.524163512
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1950326962
Short name T348
Test name
Test status
Simulation time 697846827 ps
CPU time 5.05 seconds
Started Oct 01 12:44:44 PM PDT 23
Finished Oct 01 12:44:50 PM PDT 23
Peak memory 205752 kb
Host smart-d3bb0c8d-005a-425b-9ddd-9e756c00d19e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950326962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1950326962
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2818876270
Short name T416
Test name
Test status
Simulation time 28559758 ps
CPU time 0.94 seconds
Started Oct 01 12:43:43 PM PDT 23
Finished Oct 01 12:43:45 PM PDT 23
Peak memory 205768 kb
Host smart-25ad4454-0591-400a-a5a1-a92d096f6979
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818876270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2818876270
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3407112491
Short name T357
Test name
Test status
Simulation time 21556430 ps
CPU time 1.16 seconds
Started Oct 01 12:42:35 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 213988 kb
Host smart-345e7504-e847-47fa-8639-abe0d4fa6cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407112491 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3407112491
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.659623614
Short name T212
Test name
Test status
Simulation time 61537685 ps
CPU time 0.85 seconds
Started Oct 01 12:43:53 PM PDT 23
Finished Oct 01 12:43:54 PM PDT 23
Peak memory 205780 kb
Host smart-ca717f13-54c0-43c4-a73b-d04c26d3da2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659623614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.659623614
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3746685566
Short name T339
Test name
Test status
Simulation time 13857448 ps
CPU time 0.88 seconds
Started Oct 01 12:43:33 PM PDT 23
Finished Oct 01 12:43:34 PM PDT 23
Peak memory 205684 kb
Host smart-4e1c3c1d-2186-4e5c-9441-c1db217400b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746685566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3746685566
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.81055765
Short name T411
Test name
Test status
Simulation time 14099608 ps
CPU time 0.93 seconds
Started Oct 01 12:43:36 PM PDT 23
Finished Oct 01 12:43:37 PM PDT 23
Peak memory 205924 kb
Host smart-d47911f5-8d60-4b80-9f9d-ee74df4d2307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81055765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outs
tanding.81055765
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.35705359
Short name T445
Test name
Test status
Simulation time 44674111 ps
CPU time 3.07 seconds
Started Oct 01 12:43:54 PM PDT 23
Finished Oct 01 12:43:58 PM PDT 23
Peak memory 213944 kb
Host smart-f40ec5b7-306c-4c56-9ca1-8c10f37d6752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.35705359
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.251818250
Short name T261
Test name
Test status
Simulation time 459190782 ps
CPU time 2.03 seconds
Started Oct 01 12:44:08 PM PDT 23
Finished Oct 01 12:44:11 PM PDT 23
Peak memory 205836 kb
Host smart-8e314e03-4a01-4503-9e4a-492f2266a871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251818250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.251818250
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1253593109
Short name T347
Test name
Test status
Simulation time 60862400 ps
CPU time 0.76 seconds
Started Oct 01 12:43:49 PM PDT 23
Finished Oct 01 12:43:50 PM PDT 23
Peak memory 205544 kb
Host smart-ea0d36b3-1475-4849-aec5-66232801df77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253593109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1253593109
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4020438388
Short name T370
Test name
Test status
Simulation time 37742646 ps
CPU time 0.79 seconds
Started Oct 01 12:43:35 PM PDT 23
Finished Oct 01 12:43:37 PM PDT 23
Peak memory 205660 kb
Host smart-fdd5757c-559a-4f3f-855c-bce13980b389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020438388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4020438388
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1887201045
Short name T219
Test name
Test status
Simulation time 36793370 ps
CPU time 0.8 seconds
Started Oct 01 12:43:48 PM PDT 23
Finished Oct 01 12:43:49 PM PDT 23
Peak memory 205620 kb
Host smart-1a236b89-c179-4e2d-b2ea-843d4671dc5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887201045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1887201045
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1563224167
Short name T447
Test name
Test status
Simulation time 12002942 ps
CPU time 0.83 seconds
Started Oct 01 12:43:36 PM PDT 23
Finished Oct 01 12:43:37 PM PDT 23
Peak memory 205644 kb
Host smart-8caee41a-b052-467b-ae55-a1fce84a6a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563224167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1563224167
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1758485063
Short name T331
Test name
Test status
Simulation time 24065610 ps
CPU time 0.84 seconds
Started Oct 01 12:44:01 PM PDT 23
Finished Oct 01 12:44:02 PM PDT 23
Peak memory 205576 kb
Host smart-f7305cc6-ca2f-4637-803e-a7579e20a82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758485063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1758485063
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3301036893
Short name T398
Test name
Test status
Simulation time 15597018 ps
CPU time 0.77 seconds
Started Oct 01 12:44:21 PM PDT 23
Finished Oct 01 12:44:22 PM PDT 23
Peak memory 205632 kb
Host smart-688136c8-057a-4830-bdf8-7bdd9f273f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301036893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3301036893
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4043335551
Short name T205
Test name
Test status
Simulation time 58063548 ps
CPU time 0.86 seconds
Started Oct 01 12:44:19 PM PDT 23
Finished Oct 01 12:44:20 PM PDT 23
Peak memory 205756 kb
Host smart-57b05449-bbdf-4be6-aa03-a635b2d116a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043335551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4043335551
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2292915818
Short name T330
Test name
Test status
Simulation time 31652890 ps
CPU time 0.76 seconds
Started Oct 01 12:44:06 PM PDT 23
Finished Oct 01 12:44:07 PM PDT 23
Peak memory 205628 kb
Host smart-dcffa6e8-b2fc-41d7-aeff-161055f17d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292915818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2292915818
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3771677092
Short name T332
Test name
Test status
Simulation time 22019426 ps
CPU time 0.81 seconds
Started Oct 01 12:43:52 PM PDT 23
Finished Oct 01 12:43:53 PM PDT 23
Peak memory 205692 kb
Host smart-ef7138a7-caff-4ab2-9c73-d0b3dfcac3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771677092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3771677092
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3592821074
Short name T387
Test name
Test status
Simulation time 49183618 ps
CPU time 0.88 seconds
Started Oct 01 12:44:07 PM PDT 23
Finished Oct 01 12:44:08 PM PDT 23
Peak memory 205692 kb
Host smart-43d769cf-0b55-41e7-aab5-cbd202e16902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592821074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3592821074
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3730767281
Short name T336
Test name
Test status
Simulation time 120081490 ps
CPU time 1.38 seconds
Started Oct 01 12:43:22 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 205816 kb
Host smart-0cd76e3f-e8e0-4322-9f95-c569263b976f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730767281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3730767281
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1576466166
Short name T444
Test name
Test status
Simulation time 256193631 ps
CPU time 6.14 seconds
Started Oct 01 12:43:20 PM PDT 23
Finished Oct 01 12:43:26 PM PDT 23
Peak memory 205920 kb
Host smart-e659ce41-79be-4c8a-b8cc-074ec9bafe8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576466166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1576466166
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3735525616
Short name T345
Test name
Test status
Simulation time 14595842 ps
CPU time 0.92 seconds
Started Oct 01 12:42:53 PM PDT 23
Finished Oct 01 12:42:54 PM PDT 23
Peak memory 205880 kb
Host smart-a28a6691-1e8d-488c-b063-da0a27283788
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735525616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3735525616
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3968634530
Short name T375
Test name
Test status
Simulation time 73795180 ps
CPU time 0.83 seconds
Started Oct 01 12:42:53 PM PDT 23
Finished Oct 01 12:42:54 PM PDT 23
Peak memory 205624 kb
Host smart-a77f5770-c9f5-4adb-b8f9-1e3d229ce712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968634530 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3968634530
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1730583739
Short name T335
Test name
Test status
Simulation time 22592368 ps
CPU time 0.79 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:06 PM PDT 23
Peak memory 205752 kb
Host smart-13b03c39-7a75-4e0c-85f4-e2a4d94ec06b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730583739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1730583739
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3644393376
Short name T206
Test name
Test status
Simulation time 45699872 ps
CPU time 0.89 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:05 PM PDT 23
Peak memory 205700 kb
Host smart-d93fb70c-5634-479a-bdc0-3527cb780aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644393376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3644393376
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2835732624
Short name T422
Test name
Test status
Simulation time 19424171 ps
CPU time 1.08 seconds
Started Oct 01 12:42:56 PM PDT 23
Finished Oct 01 12:42:57 PM PDT 23
Peak memory 205864 kb
Host smart-5d972aa1-630d-47d5-a3e8-2bf3959f7fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835732624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2835732624
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1628674392
Short name T372
Test name
Test status
Simulation time 431306160 ps
CPU time 4.08 seconds
Started Oct 01 12:42:53 PM PDT 23
Finished Oct 01 12:42:57 PM PDT 23
Peak memory 214080 kb
Host smart-7668d8c7-a735-4323-a6f0-43a63bd24032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628674392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1628674392
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2466016148
Short name T263
Test name
Test status
Simulation time 116969330 ps
CPU time 2.8 seconds
Started Oct 01 12:43:06 PM PDT 23
Finished Oct 01 12:43:10 PM PDT 23
Peak memory 205820 kb
Host smart-608f1ade-a8a8-4b1f-ab99-e7e0c44cf8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466016148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2466016148
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2899890375
Short name T204
Test name
Test status
Simulation time 54652744 ps
CPU time 0.74 seconds
Started Oct 01 12:44:09 PM PDT 23
Finished Oct 01 12:44:10 PM PDT 23
Peak memory 205648 kb
Host smart-23efc660-3638-4266-b70f-e4f7322430fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899890375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2899890375
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2380429930
Short name T353
Test name
Test status
Simulation time 27319612 ps
CPU time 0.87 seconds
Started Oct 01 12:44:23 PM PDT 23
Finished Oct 01 12:44:25 PM PDT 23
Peak memory 205532 kb
Host smart-51671615-2b87-4b88-8fd1-824e15232566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380429930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2380429930
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1055961965
Short name T390
Test name
Test status
Simulation time 15443491 ps
CPU time 0.89 seconds
Started Oct 01 12:43:52 PM PDT 23
Finished Oct 01 12:43:54 PM PDT 23
Peak memory 205612 kb
Host smart-65a881bb-3dd8-457f-897a-77ca6c040d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055961965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1055961965
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.801739852
Short name T356
Test name
Test status
Simulation time 35066116 ps
CPU time 0.77 seconds
Started Oct 01 12:44:16 PM PDT 23
Finished Oct 01 12:44:17 PM PDT 23
Peak memory 205580 kb
Host smart-50e1fe5b-66b0-40ab-b408-4c4144aff29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801739852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.801739852
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4224860154
Short name T409
Test name
Test status
Simulation time 54563439 ps
CPU time 0.85 seconds
Started Oct 01 12:44:24 PM PDT 23
Finished Oct 01 12:44:25 PM PDT 23
Peak memory 205756 kb
Host smart-bfa9079d-43da-44fe-b4ab-8894eda5132f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224860154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4224860154
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3687577883
Short name T351
Test name
Test status
Simulation time 48404075 ps
CPU time 0.75 seconds
Started Oct 01 12:44:15 PM PDT 23
Finished Oct 01 12:44:16 PM PDT 23
Peak memory 205664 kb
Host smart-46261729-fbcc-440f-8716-77087fc80b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687577883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3687577883
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2930341157
Short name T407
Test name
Test status
Simulation time 34055272 ps
CPU time 0.79 seconds
Started Oct 01 12:44:26 PM PDT 23
Finished Oct 01 12:44:28 PM PDT 23
Peak memory 205664 kb
Host smart-802dfe57-4367-49e5-885e-c887bd06713e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930341157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2930341157
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1845396138
Short name T442
Test name
Test status
Simulation time 14299030 ps
CPU time 0.81 seconds
Started Oct 01 12:44:23 PM PDT 23
Finished Oct 01 12:44:24 PM PDT 23
Peak memory 205704 kb
Host smart-b2dc3f32-226e-40d8-9596-1e25d8c7ce74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845396138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1845396138
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1735918563
Short name T412
Test name
Test status
Simulation time 79574651 ps
CPU time 0.75 seconds
Started Oct 01 12:44:21 PM PDT 23
Finished Oct 01 12:44:22 PM PDT 23
Peak memory 205648 kb
Host smart-b5c81cb0-33d9-4d8d-99c8-cd5c6412e312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735918563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1735918563
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1975907858
Short name T364
Test name
Test status
Simulation time 13788675 ps
CPU time 0.84 seconds
Started Oct 01 12:44:08 PM PDT 23
Finished Oct 01 12:44:09 PM PDT 23
Peak memory 205668 kb
Host smart-5b72412d-0125-4996-aca5-15f9f09eab9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975907858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1975907858
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1186058420
Short name T349
Test name
Test status
Simulation time 25095332 ps
CPU time 1.17 seconds
Started Oct 01 12:43:59 PM PDT 23
Finished Oct 01 12:44:00 PM PDT 23
Peak memory 205832 kb
Host smart-9b44de1b-da08-4754-863a-9c885f5bd79c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186058420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1186058420
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.194818473
Short name T196
Test name
Test status
Simulation time 487571604 ps
CPU time 3.19 seconds
Started Oct 01 12:43:19 PM PDT 23
Finished Oct 01 12:43:23 PM PDT 23
Peak memory 205820 kb
Host smart-cba12ef7-7757-425e-97a6-6974361d968d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194818473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.194818473
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2741637295
Short name T329
Test name
Test status
Simulation time 26261321 ps
CPU time 0.91 seconds
Started Oct 01 12:42:58 PM PDT 23
Finished Oct 01 12:43:00 PM PDT 23
Peak memory 205680 kb
Host smart-95db922f-a03e-40d4-ae3d-cb1b04b0f079
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741637295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2741637295
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1519099556
Short name T421
Test name
Test status
Simulation time 36642692 ps
CPU time 1.07 seconds
Started Oct 01 12:43:43 PM PDT 23
Finished Oct 01 12:43:44 PM PDT 23
Peak memory 206120 kb
Host smart-f6ffec61-60e9-49f1-8139-33dcb4bb841c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519099556 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1519099556
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3741888594
Short name T224
Test name
Test status
Simulation time 49343640 ps
CPU time 0.79 seconds
Started Oct 01 12:43:51 PM PDT 23
Finished Oct 01 12:43:52 PM PDT 23
Peak memory 205784 kb
Host smart-440f1d46-aa5a-4a8e-8ae7-23b5b61d73db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741888594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3741888594
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1225402056
Short name T368
Test name
Test status
Simulation time 44332197 ps
CPU time 0.81 seconds
Started Oct 01 12:43:24 PM PDT 23
Finished Oct 01 12:43:25 PM PDT 23
Peak memory 205684 kb
Host smart-40446ef5-038d-4a81-a8ab-3cab1fcfabd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225402056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1225402056
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2895388140
Short name T192
Test name
Test status
Simulation time 23611589 ps
CPU time 1.04 seconds
Started Oct 01 12:43:54 PM PDT 23
Finished Oct 01 12:43:56 PM PDT 23
Peak memory 205820 kb
Host smart-93298bfb-256d-4082-b312-f1d37301d8e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895388140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2895388140
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2589640247
Short name T402
Test name
Test status
Simulation time 114069052 ps
CPU time 2.26 seconds
Started Oct 01 12:43:08 PM PDT 23
Finished Oct 01 12:43:12 PM PDT 23
Peak memory 214160 kb
Host smart-6a6c0970-c5da-46bf-aeb1-b4203078d8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589640247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2589640247
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2843012050
Short name T342
Test name
Test status
Simulation time 47501157 ps
CPU time 1.5 seconds
Started Oct 01 12:43:39 PM PDT 23
Finished Oct 01 12:43:41 PM PDT 23
Peak memory 205812 kb
Host smart-25ad39b8-6446-420d-b1bc-89a33eb0371b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843012050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2843012050
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1167065211
Short name T365
Test name
Test status
Simulation time 18307386 ps
CPU time 0.77 seconds
Started Oct 01 12:45:11 PM PDT 23
Finished Oct 01 12:45:13 PM PDT 23
Peak memory 205500 kb
Host smart-111e20e9-c7bb-4071-9992-2f8bb132036a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167065211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1167065211
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.84317087
Short name T222
Test name
Test status
Simulation time 23602723 ps
CPU time 0.76 seconds
Started Oct 01 12:44:12 PM PDT 23
Finished Oct 01 12:44:13 PM PDT 23
Peak memory 205604 kb
Host smart-e151b6b1-65fa-4770-ba01-e76073f77c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84317087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.84317087
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2223419456
Short name T358
Test name
Test status
Simulation time 73511806 ps
CPU time 0.78 seconds
Started Oct 01 12:44:18 PM PDT 23
Finished Oct 01 12:44:19 PM PDT 23
Peak memory 205736 kb
Host smart-b0167b6e-32fb-4031-9338-68242ffebe5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223419456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2223419456
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.719335407
Short name T367
Test name
Test status
Simulation time 40596397 ps
CPU time 0.82 seconds
Started Oct 01 12:44:04 PM PDT 23
Finished Oct 01 12:44:05 PM PDT 23
Peak memory 205584 kb
Host smart-24741274-62ea-4656-b4d8-3da7e3241bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719335407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.719335407
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3511476799
Short name T430
Test name
Test status
Simulation time 94954141 ps
CPU time 0.78 seconds
Started Oct 01 12:43:50 PM PDT 23
Finished Oct 01 12:43:52 PM PDT 23
Peak memory 205548 kb
Host smart-a48ea859-ee3a-42ac-a657-c137fefd9607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511476799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3511476799
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3274413776
Short name T410
Test name
Test status
Simulation time 18610745 ps
CPU time 0.75 seconds
Started Oct 01 12:44:13 PM PDT 23
Finished Oct 01 12:44:14 PM PDT 23
Peak memory 205676 kb
Host smart-3cac5f07-425d-4fac-8e68-e798b024c4bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274413776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3274413776
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.620317574
Short name T381
Test name
Test status
Simulation time 16301578 ps
CPU time 0.85 seconds
Started Oct 01 12:45:18 PM PDT 23
Finished Oct 01 12:45:19 PM PDT 23
Peak memory 205760 kb
Host smart-a615d3e1-1615-4acb-8f3d-570a929a2a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620317574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.620317574
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1546691421
Short name T417
Test name
Test status
Simulation time 29386255 ps
CPU time 0.85 seconds
Started Oct 01 12:45:14 PM PDT 23
Finished Oct 01 12:45:16 PM PDT 23
Peak memory 205704 kb
Host smart-dd1e2543-a84b-44af-9e87-80fc4e1296c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546691421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1546691421
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2558809287
Short name T363
Test name
Test status
Simulation time 15403481 ps
CPU time 0.82 seconds
Started Oct 01 12:45:11 PM PDT 23
Finished Oct 01 12:45:12 PM PDT 23
Peak memory 205592 kb
Host smart-15c27536-b2bd-4e92-880d-6647f902cc24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558809287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2558809287
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2540321543
Short name T359
Test name
Test status
Simulation time 10643573 ps
CPU time 0.77 seconds
Started Oct 01 12:45:11 PM PDT 23
Finished Oct 01 12:45:12 PM PDT 23
Peak memory 205744 kb
Host smart-fcd540f6-64a0-4aaf-89e2-82dcb704c5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540321543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2540321543
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.336889191
Short name T333
Test name
Test status
Simulation time 12544554 ps
CPU time 0.92 seconds
Started Oct 01 12:42:41 PM PDT 23
Finished Oct 01 12:42:43 PM PDT 23
Peak memory 205892 kb
Host smart-a2b7ed10-0d9e-4477-8a57-4bc325d36a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336889191 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.336889191
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.708746298
Short name T371
Test name
Test status
Simulation time 14690580 ps
CPU time 0.9 seconds
Started Oct 01 12:43:38 PM PDT 23
Finished Oct 01 12:43:39 PM PDT 23
Peak memory 205764 kb
Host smart-a49e848a-04ff-4a25-bff8-b9a6b4f3bdd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708746298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.708746298
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.560389965
Short name T383
Test name
Test status
Simulation time 21688486 ps
CPU time 0.81 seconds
Started Oct 01 12:44:16 PM PDT 23
Finished Oct 01 12:44:17 PM PDT 23
Peak memory 205704 kb
Host smart-35174acb-6bf1-4c5b-8d14-f2f81488d497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560389965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.560389965
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3377419753
Short name T420
Test name
Test status
Simulation time 77809134 ps
CPU time 1 seconds
Started Oct 01 12:43:35 PM PDT 23
Finished Oct 01 12:43:37 PM PDT 23
Peak memory 205864 kb
Host smart-0dea8bd8-40fc-4182-9be5-b7a2b5915b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377419753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3377419753
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3903348509
Short name T426
Test name
Test status
Simulation time 122429756 ps
CPU time 2.39 seconds
Started Oct 01 12:43:21 PM PDT 23
Finished Oct 01 12:43:24 PM PDT 23
Peak memory 214036 kb
Host smart-132996cf-75cb-413b-bfce-6bfd3745083f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903348509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3903348509
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3962278226
Short name T395
Test name
Test status
Simulation time 294620999 ps
CPU time 1.95 seconds
Started Oct 01 12:43:40 PM PDT 23
Finished Oct 01 12:43:43 PM PDT 23
Peak memory 205808 kb
Host smart-25928a89-fe72-48e7-ae96-214fc36ac889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962278226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3962278226
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4090938536
Short name T392
Test name
Test status
Simulation time 251429274 ps
CPU time 1.02 seconds
Started Oct 01 12:42:55 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 214148 kb
Host smart-ea9fb29a-e57e-4af4-8b45-1c0d08182234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090938536 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4090938536
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3632436121
Short name T346
Test name
Test status
Simulation time 23450268 ps
CPU time 0.84 seconds
Started Oct 01 12:42:47 PM PDT 23
Finished Oct 01 12:42:48 PM PDT 23
Peak memory 205800 kb
Host smart-09ea8c8a-5b9e-454c-bbff-d2377a10ee66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632436121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3632436121
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.577892529
Short name T216
Test name
Test status
Simulation time 75187719 ps
CPU time 0.79 seconds
Started Oct 01 12:43:07 PM PDT 23
Finished Oct 01 12:43:11 PM PDT 23
Peak memory 205700 kb
Host smart-4f2d5aec-dddf-4eec-a44e-3771cd871220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577892529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.577892529
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3123504480
Short name T431
Test name
Test status
Simulation time 38807737 ps
CPU time 0.93 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:06 PM PDT 23
Peak memory 205704 kb
Host smart-20e31c6a-a76f-4742-bb1d-0d096a8edd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123504480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3123504480
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1167231687
Short name T436
Test name
Test status
Simulation time 607013001 ps
CPU time 1.91 seconds
Started Oct 01 12:43:18 PM PDT 23
Finished Oct 01 12:43:20 PM PDT 23
Peak memory 214104 kb
Host smart-81f7ee9c-4c26-433b-a968-a24b2543a462
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167231687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1167231687
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3398381530
Short name T369
Test name
Test status
Simulation time 591673578 ps
CPU time 2.25 seconds
Started Oct 01 12:43:01 PM PDT 23
Finished Oct 01 12:43:04 PM PDT 23
Peak memory 205784 kb
Host smart-98d38ca8-d08e-43b4-aba0-02db441d6362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398381530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3398381530
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2144017381
Short name T437
Test name
Test status
Simulation time 143724019 ps
CPU time 1.19 seconds
Started Oct 01 12:42:47 PM PDT 23
Finished Oct 01 12:42:48 PM PDT 23
Peak memory 215688 kb
Host smart-67776245-7014-4c23-adc8-b44f62352dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144017381 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2144017381
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.574651593
Short name T354
Test name
Test status
Simulation time 27844681 ps
CPU time 0.9 seconds
Started Oct 01 12:43:18 PM PDT 23
Finished Oct 01 12:43:21 PM PDT 23
Peak memory 205804 kb
Host smart-832dccfb-896c-40f6-9ff7-036c6bcca3ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574651593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.574651593
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.883825693
Short name T408
Test name
Test status
Simulation time 16866306 ps
CPU time 0.85 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 205788 kb
Host smart-516d4f6c-4672-4dcd-a1d6-9cbd6d37c701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883825693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.883825693
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3778966775
Short name T226
Test name
Test status
Simulation time 27706677 ps
CPU time 1.02 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:06 PM PDT 23
Peak memory 205860 kb
Host smart-a53e4be3-e037-465a-a2d3-5f9dcefb2df8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778966775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3778966775
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.292674356
Short name T341
Test name
Test status
Simulation time 143267810 ps
CPU time 2.75 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214072 kb
Host smart-b4110722-898c-457f-a040-0632e35acbb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292674356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.292674356
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3581331130
Short name T432
Test name
Test status
Simulation time 56531612 ps
CPU time 1.65 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:57 PM PDT 23
Peak memory 205800 kb
Host smart-7038d280-3da0-417f-87ec-119bf1dafdaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581331130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3581331130
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3707189426
Short name T350
Test name
Test status
Simulation time 28161231 ps
CPU time 1.08 seconds
Started Oct 01 12:43:00 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 214168 kb
Host smart-7b82cdba-80d3-4b38-8ca0-03ddf08fd52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707189426 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3707189426
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1303781284
Short name T427
Test name
Test status
Simulation time 26711426 ps
CPU time 0.88 seconds
Started Oct 01 12:42:41 PM PDT 23
Finished Oct 01 12:42:42 PM PDT 23
Peak memory 205804 kb
Host smart-8ea43a4e-fed8-4203-b2c9-a7f1f581b7ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303781284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1303781284
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1276744063
Short name T366
Test name
Test status
Simulation time 13114424 ps
CPU time 0.86 seconds
Started Oct 01 12:42:47 PM PDT 23
Finished Oct 01 12:42:48 PM PDT 23
Peak memory 205596 kb
Host smart-8dbcbe59-45b7-471f-be9a-a5980b1318de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276744063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1276744063
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3449387468
Short name T337
Test name
Test status
Simulation time 72576426 ps
CPU time 0.95 seconds
Started Oct 01 12:42:49 PM PDT 23
Finished Oct 01 12:42:50 PM PDT 23
Peak memory 205908 kb
Host smart-5ec37d92-c1c7-4b4d-bf40-23ef1df472ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449387468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3449387468
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2489974216
Short name T424
Test name
Test status
Simulation time 27141739 ps
CPU time 1.83 seconds
Started Oct 01 12:42:49 PM PDT 23
Finished Oct 01 12:42:56 PM PDT 23
Peak memory 214064 kb
Host smart-81f63375-1951-443b-a672-06c29af1d3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489974216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2489974216
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2775420934
Short name T373
Test name
Test status
Simulation time 123014424 ps
CPU time 2.14 seconds
Started Oct 01 12:43:09 PM PDT 23
Finished Oct 01 12:43:12 PM PDT 23
Peak memory 205736 kb
Host smart-f9f7b133-0f4c-4e03-8c51-350e8faf608b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775420934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2775420934
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.193034985
Short name T184
Test name
Test status
Simulation time 59624295 ps
CPU time 1.03 seconds
Started Oct 01 12:43:05 PM PDT 23
Finished Oct 01 12:43:07 PM PDT 23
Peak memory 214156 kb
Host smart-b42073ba-0370-4c86-98c4-2efc18ce9e7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193034985 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.193034985
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2964434211
Short name T380
Test name
Test status
Simulation time 13233400 ps
CPU time 0.79 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:42:27 PM PDT 23
Peak memory 205560 kb
Host smart-66032a69-0c40-4bfd-8d1b-49e66c498ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964434211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2964434211
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4285772454
Short name T343
Test name
Test status
Simulation time 20388835 ps
CPU time 0.8 seconds
Started Oct 01 12:42:53 PM PDT 23
Finished Oct 01 12:42:54 PM PDT 23
Peak memory 205688 kb
Host smart-0bbe3ce7-85c0-4192-adf6-fc54fb7ec850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285772454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4285772454
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2496259441
Short name T225
Test name
Test status
Simulation time 32325741 ps
CPU time 1.04 seconds
Started Oct 01 12:42:44 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 205808 kb
Host smart-fbb5cd6c-709a-4634-8c09-0ba0b7ce9662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496259441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2496259441
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.4236835792
Short name T450
Test name
Test status
Simulation time 416571359 ps
CPU time 3.63 seconds
Started Oct 01 12:42:49 PM PDT 23
Finished Oct 01 12:42:52 PM PDT 23
Peak memory 213988 kb
Host smart-3288d9d8-0a30-4517-b0d8-388b6b5cf541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236835792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.4236835792
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1122684569
Short name T251
Test name
Test status
Simulation time 76588985 ps
CPU time 1.65 seconds
Started Oct 01 12:42:58 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 205796 kb
Host smart-aade2b91-18e8-4fee-9e6e-64a83e422f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122684569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1122684569
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3343181381
Short name T458
Test name
Test status
Simulation time 21844299 ps
CPU time 0.95 seconds
Started Oct 01 12:41:17 PM PDT 23
Finished Oct 01 12:41:18 PM PDT 23
Peak memory 206160 kb
Host smart-ea4bfc5c-5e75-4149-aa12-3daca5569d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343181381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3343181381
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3685292421
Short name T469
Test name
Test status
Simulation time 106695366 ps
CPU time 1.05 seconds
Started Oct 01 12:41:22 PM PDT 23
Finished Oct 01 12:41:23 PM PDT 23
Peak memory 204740 kb
Host smart-c6b151fd-b10c-4fce-ad9f-4f81d66c04c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685292421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3685292421
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1417731464
Short name T126
Test name
Test status
Simulation time 55263713 ps
CPU time 0.87 seconds
Started Oct 01 12:41:22 PM PDT 23
Finished Oct 01 12:41:28 PM PDT 23
Peak memory 214404 kb
Host smart-0668e9a4-d08f-44de-b8f1-2ae19312b9fa
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417731464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1417731464
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2640298770
Short name T620
Test name
Test status
Simulation time 30473615 ps
CPU time 0.99 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:41:35 PM PDT 23
Peak memory 214676 kb
Host smart-3b1def26-8b97-464a-a6ed-0cb3cbe9fb22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640298770 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2640298770
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1773712741
Short name T505
Test name
Test status
Simulation time 21583897 ps
CPU time 1.04 seconds
Started Oct 01 12:41:20 PM PDT 23
Finished Oct 01 12:41:22 PM PDT 23
Peak memory 214376 kb
Host smart-de22223b-d20d-4409-9a92-f086b61e81ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773712741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1773712741
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2375503766
Short name T724
Test name
Test status
Simulation time 111657872 ps
CPU time 0.99 seconds
Started Oct 01 12:41:28 PM PDT 23
Finished Oct 01 12:41:29 PM PDT 23
Peak memory 214284 kb
Host smart-9b830790-d146-4464-a77e-4fea3b0fc1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375503766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2375503766
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.796532623
Short name T599
Test name
Test status
Simulation time 21400707 ps
CPU time 1.05 seconds
Started Oct 01 12:41:23 PM PDT 23
Finished Oct 01 12:41:24 PM PDT 23
Peak memory 214488 kb
Host smart-fe678ba3-af72-4727-8525-413c503b76b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796532623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.796532623
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1589491583
Short name T98
Test name
Test status
Simulation time 13310616 ps
CPU time 0.86 seconds
Started Oct 01 12:41:16 PM PDT 23
Finished Oct 01 12:41:17 PM PDT 23
Peak memory 204980 kb
Host smart-118e3897-fca8-41aa-9e51-5820b20b7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589491583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1589491583
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1408455874
Short name T661
Test name
Test status
Simulation time 38060432 ps
CPU time 0.78 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 12:41:25 PM PDT 23
Peak memory 204424 kb
Host smart-45762cb1-540c-4bb0-8e78-cfb9975a7de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408455874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1408455874
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2405805686
Short name T632
Test name
Test status
Simulation time 73432989 ps
CPU time 1.82 seconds
Started Oct 01 12:41:31 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 205536 kb
Host smart-d3c113e5-436e-4613-b6b7-71911411f556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405805686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2405805686
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.1169155027
Short name T477
Test name
Test status
Simulation time 265593538781 ps
CPU time 1560.45 seconds
Started Oct 01 12:41:22 PM PDT 23
Finished Oct 01 01:07:23 PM PDT 23
Peak memory 218684 kb
Host smart-5e18da95-535b-49a2-9c2a-e32d1073f2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169155027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1169155027
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1287641467
Short name T501
Test name
Test status
Simulation time 18374040 ps
CPU time 0.97 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 204644 kb
Host smart-b896ffb1-ad3a-43dd-b8a1-f882f55aec57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287641467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1287641467
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.917399309
Short name T93
Test name
Test status
Simulation time 11385424 ps
CPU time 0.81 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 214332 kb
Host smart-87e1bc9b-f2f0-4a24-8af9-3ac92a2c532e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917399309 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.917399309
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2251633662
Short name T90
Test name
Test status
Simulation time 69260524 ps
CPU time 0.98 seconds
Started Oct 01 12:41:19 PM PDT 23
Finished Oct 01 12:41:21 PM PDT 23
Peak memory 214676 kb
Host smart-ff2548d2-b7f5-4963-bd25-5f6d5dc0a0f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251633662 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2251633662
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.147383014
Short name T22
Test name
Test status
Simulation time 20063162 ps
CPU time 0.99 seconds
Started Oct 01 12:41:21 PM PDT 23
Finished Oct 01 12:41:22 PM PDT 23
Peak memory 215556 kb
Host smart-9c455c5c-68a6-4aa9-bcb8-171c515000da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147383014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.147383014
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3506517740
Short name T3
Test name
Test status
Simulation time 302102543 ps
CPU time 1.27 seconds
Started Oct 01 12:41:15 PM PDT 23
Finished Oct 01 12:41:16 PM PDT 23
Peak memory 214308 kb
Host smart-b7de24ca-3584-4076-b909-c6262a59f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506517740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3506517740
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1334373194
Short name T129
Test name
Test status
Simulation time 19655234 ps
CPU time 0.95 seconds
Started Oct 01 12:41:27 PM PDT 23
Finished Oct 01 12:41:28 PM PDT 23
Peak memory 214624 kb
Host smart-a6e55e20-91e8-41e7-88c6-5883e35a6848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334373194 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1334373194
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.731159151
Short name T119
Test name
Test status
Simulation time 13199526 ps
CPU time 0.87 seconds
Started Oct 01 12:41:16 PM PDT 23
Finished Oct 01 12:41:17 PM PDT 23
Peak memory 204748 kb
Host smart-4969bc97-a4a0-48a0-95b7-1f6b58429575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731159151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.731159151
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1463010785
Short name T18
Test name
Test status
Simulation time 203118050 ps
CPU time 3.54 seconds
Started Oct 01 12:41:29 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 233172 kb
Host smart-d3ac9496-3a88-4fc6-9ee9-94daac6fea39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463010785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1463010785
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2481048275
Short name T607
Test name
Test status
Simulation time 48672476 ps
CPU time 0.87 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 204704 kb
Host smart-6fec2226-3e84-47b1-813f-27825a1005eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481048275 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2481048275
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2865778492
Short name T549
Test name
Test status
Simulation time 1027801232 ps
CPU time 4.48 seconds
Started Oct 01 12:41:04 PM PDT 23
Finished Oct 01 12:41:09 PM PDT 23
Peak memory 205908 kb
Host smart-afb6f383-c601-4672-abbf-17326e3aed67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865778492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2865778492
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3010930064
Short name T490
Test name
Test status
Simulation time 105804149690 ps
CPU time 497.75 seconds
Started Oct 01 12:41:18 PM PDT 23
Finished Oct 01 12:49:36 PM PDT 23
Peak memory 215252 kb
Host smart-2ec2227f-ca1e-4e3c-96f1-cd311b11a660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010930064 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3010930064
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3076154868
Short name T695
Test name
Test status
Simulation time 24452999 ps
CPU time 1 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:41:36 PM PDT 23
Peak memory 206076 kb
Host smart-263b6a5b-97f3-4afb-a2d8-3b23a30358b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076154868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3076154868
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3458961991
Short name T684
Test name
Test status
Simulation time 242294425 ps
CPU time 0.99 seconds
Started Oct 01 12:41:41 PM PDT 23
Finished Oct 01 12:41:42 PM PDT 23
Peak memory 205216 kb
Host smart-eca03dbc-d15c-478b-ad66-4e4d706ec419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458961991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3458961991
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.2550212265
Short name T507
Test name
Test status
Simulation time 23526562 ps
CPU time 0.98 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 222156 kb
Host smart-33e1a744-b69c-4ec4-9efb-76d71cd8a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550212265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2550212265
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.694166607
Short name T96
Test name
Test status
Simulation time 65449088 ps
CPU time 1.08 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 214416 kb
Host smart-bcb9531e-bc2c-463e-b766-f5463a365cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694166607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.694166607
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3853117029
Short name T556
Test name
Test status
Simulation time 23422388 ps
CPU time 1.16 seconds
Started Oct 01 12:41:48 PM PDT 23
Finished Oct 01 12:41:50 PM PDT 23
Peak memory 221636 kb
Host smart-ccfec9ce-dbe2-4ac2-8785-0e6fcca690c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853117029 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3853117029
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.378130937
Short name T682
Test name
Test status
Simulation time 47294284 ps
CPU time 0.82 seconds
Started Oct 01 12:41:36 PM PDT 23
Finished Oct 01 12:41:37 PM PDT 23
Peak memory 204568 kb
Host smart-c00a6a44-b2f0-4b7b-a7f2-e7cb47008bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378130937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.378130937
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1248489883
Short name T491
Test name
Test status
Simulation time 381495109 ps
CPU time 2.17 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:41:42 PM PDT 23
Peak memory 205496 kb
Host smart-4ae519fd-e758-4485-b425-7d5d2f4eeb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248489883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1248489883
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3745805628
Short name T177
Test name
Test status
Simulation time 355090106330 ps
CPU time 1878.27 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 01:12:45 PM PDT 23
Peak memory 220564 kb
Host smart-703c8871-5999-4370-aba5-897dd593e147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745805628 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3745805628
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.4143326020
Short name T65
Test name
Test status
Simulation time 49457821 ps
CPU time 1 seconds
Started Oct 01 12:41:48 PM PDT 23
Finished Oct 01 12:41:49 PM PDT 23
Peak memory 206076 kb
Host smart-85851e44-356b-4bf8-8346-e19215f27c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143326020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4143326020
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1361779368
Short name T530
Test name
Test status
Simulation time 25544346 ps
CPU time 0.95 seconds
Started Oct 01 12:41:35 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 205516 kb
Host smart-4514974a-f196-4cc8-bac2-fa0d58d8748a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361779368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1361779368
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2709226560
Short name T67
Test name
Test status
Simulation time 13294378 ps
CPU time 0.85 seconds
Started Oct 01 12:41:41 PM PDT 23
Finished Oct 01 12:41:42 PM PDT 23
Peak memory 214648 kb
Host smart-0707d0d4-2c68-4f74-a462-aa1ab23af1a9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709226560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2709226560
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3429990667
Short name T667
Test name
Test status
Simulation time 35450109 ps
CPU time 0.98 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 214564 kb
Host smart-d76ec218-3b0c-4bd0-8a4e-db54641acb0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429990667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3429990667
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.448799123
Short name T581
Test name
Test status
Simulation time 127221482 ps
CPU time 1.03 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 216724 kb
Host smart-552e23e3-7d6c-4ee8-9dc9-4c77b24c3a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448799123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.448799123
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.2626870720
Short name T671
Test name
Test status
Simulation time 36889602 ps
CPU time 0.89 seconds
Started Oct 01 12:41:49 PM PDT 23
Finished Oct 01 12:41:50 PM PDT 23
Peak memory 214500 kb
Host smart-507a0ce7-a5be-4290-83d0-b0fa929f1b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626870720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2626870720
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4198810456
Short name T612
Test name
Test status
Simulation time 23233201 ps
CPU time 0.82 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 204900 kb
Host smart-5fd18337-6d88-4dae-b4cb-c9e2ed620e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198810456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4198810456
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2952185836
Short name T711
Test name
Test status
Simulation time 61162496 ps
CPU time 1.72 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:54 PM PDT 23
Peak memory 206088 kb
Host smart-e2905d31-5db5-4660-839b-aaa0aa356747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952185836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2952185836
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3067344300
Short name T656
Test name
Test status
Simulation time 691581376611 ps
CPU time 1429.19 seconds
Started Oct 01 12:41:55 PM PDT 23
Finished Oct 01 01:05:45 PM PDT 23
Peak memory 216940 kb
Host smart-4cba55fd-9bb3-4ece-9356-a2901a200cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067344300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3067344300
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.1929696780
Short name T246
Test name
Test status
Simulation time 19113711 ps
CPU time 0.99 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 206144 kb
Host smart-006f331b-5d5e-4426-8365-caf5169323f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929696780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1929696780
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_err.736320596
Short name T230
Test name
Test status
Simulation time 32635011 ps
CPU time 0.97 seconds
Started Oct 01 12:41:40 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 228540 kb
Host smart-70d1e60f-f6df-4fc7-98f5-5033534fa1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736320596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.736320596
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.711581363
Short name T266
Test name
Test status
Simulation time 18428780 ps
CPU time 0.97 seconds
Started Oct 01 12:41:36 PM PDT 23
Finished Oct 01 12:41:37 PM PDT 23
Peak memory 204956 kb
Host smart-ed9f6a5a-59c3-418e-bef8-1705917dd3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711581363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.711581363
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2038020922
Short name T295
Test name
Test status
Simulation time 12597988 ps
CPU time 0.9 seconds
Started Oct 01 12:42:01 PM PDT 23
Finished Oct 01 12:42:03 PM PDT 23
Peak memory 204756 kb
Host smart-390575c1-1dfb-4642-9561-1849509585de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038020922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2038020922
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.662050187
Short name T511
Test name
Test status
Simulation time 55944622 ps
CPU time 1.63 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:58 PM PDT 23
Peak memory 205408 kb
Host smart-44c3a901-4318-4655-9c9a-644909395975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662050187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.662050187
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_alert.946123460
Short name T289
Test name
Test status
Simulation time 26567445 ps
CPU time 0.88 seconds
Started Oct 01 12:42:03 PM PDT 23
Finished Oct 01 12:42:04 PM PDT 23
Peak memory 204988 kb
Host smart-3f91e4c0-6046-4285-be4b-ab586bcfe734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946123460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.946123460
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3201510966
Short name T503
Test name
Test status
Simulation time 87563894 ps
CPU time 0.76 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:40 PM PDT 23
Peak memory 204168 kb
Host smart-ca137b7d-20db-438a-84d4-7dc9d65c07d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201510966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3201510966
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2206836814
Short name T675
Test name
Test status
Simulation time 20890233 ps
CPU time 0.92 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 214680 kb
Host smart-b8b6438b-175b-456d-b629-a559f07f050d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206836814 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2206836814
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1892673078
Short name T635
Test name
Test status
Simulation time 25058806 ps
CPU time 0.86 seconds
Started Oct 01 12:41:43 PM PDT 23
Finished Oct 01 12:41:44 PM PDT 23
Peak memory 215728 kb
Host smart-193bcadc-8233-4e0d-a1f6-9c6f3d0b1330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892673078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1892673078
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1163646027
Short name T269
Test name
Test status
Simulation time 74150082 ps
CPU time 1.07 seconds
Started Oct 01 12:42:01 PM PDT 23
Finished Oct 01 12:42:02 PM PDT 23
Peak memory 214420 kb
Host smart-47d8eee0-b8cd-4562-912c-abd7ad4de955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163646027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1163646027
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3366341141
Short name T641
Test name
Test status
Simulation time 44594984 ps
CPU time 0.8 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:26 PM PDT 23
Peak memory 214228 kb
Host smart-6127f987-350d-4b1a-ba67-e242d4610d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366341141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3366341141
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3664998568
Short name T719
Test name
Test status
Simulation time 16075266 ps
CPU time 0.88 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 204928 kb
Host smart-48e4b1ee-48a5-4029-a8c3-1f7348d99a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664998568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3664998568
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.277745195
Short name T253
Test name
Test status
Simulation time 205286621 ps
CPU time 2.41 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 205860 kb
Host smart-e6a6d1b3-4e6a-4e5f-b6eb-c5998a795e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277745195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.277745195
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1581941761
Short name T183
Test name
Test status
Simulation time 66673964402 ps
CPU time 1110.63 seconds
Started Oct 01 12:41:19 PM PDT 23
Finished Oct 01 12:59:50 PM PDT 23
Peak memory 215216 kb
Host smart-fc326020-6835-419d-9ad6-a7d94553abf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581941761 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1581941761
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert_test.511180993
Short name T686
Test name
Test status
Simulation time 17258169 ps
CPU time 0.92 seconds
Started Oct 01 12:41:44 PM PDT 23
Finished Oct 01 12:41:46 PM PDT 23
Peak memory 205264 kb
Host smart-244ce30c-b7af-4fa9-b939-43aa96e63d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511180993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.511180993
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1426620118
Short name T92
Test name
Test status
Simulation time 20125370 ps
CPU time 0.96 seconds
Started Oct 01 12:41:47 PM PDT 23
Finished Oct 01 12:41:48 PM PDT 23
Peak memory 214572 kb
Host smart-d211eded-2e9a-4581-9d53-2c939fd54b7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426620118 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1426620118
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2355318214
Short name T323
Test name
Test status
Simulation time 29443437 ps
CPU time 1.21 seconds
Started Oct 01 12:41:48 PM PDT 23
Finished Oct 01 12:41:49 PM PDT 23
Peak memory 216984 kb
Host smart-f144726a-0f20-4a16-9b88-47a6746f8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355318214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2355318214
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.998061045
Short name T299
Test name
Test status
Simulation time 19983676 ps
CPU time 1.15 seconds
Started Oct 01 12:41:59 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 221492 kb
Host smart-8cd60de5-e388-4e04-b175-f2af7f138804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998061045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.998061045
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2890414689
Short name T518
Test name
Test status
Simulation time 25113225 ps
CPU time 0.87 seconds
Started Oct 01 12:41:53 PM PDT 23
Finished Oct 01 12:41:54 PM PDT 23
Peak memory 204588 kb
Host smart-75055eb4-85b2-4b2b-9cf4-080fac44b2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890414689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2890414689
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1649500439
Short name T49
Test name
Test status
Simulation time 70861149 ps
CPU time 1.01 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 204960 kb
Host smart-982d5a5b-18df-4821-a45e-f6e91dc70147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649500439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1649500439
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.817096721
Short name T625
Test name
Test status
Simulation time 59551375735 ps
CPU time 1462.67 seconds
Started Oct 01 12:42:02 PM PDT 23
Finished Oct 01 01:06:25 PM PDT 23
Peak memory 218548 kb
Host smart-3a1839dc-b4e6-471d-b90d-b951e70e9eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817096721 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.817096721
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.edn_alert.1637520387
Short name T282
Test name
Test status
Simulation time 65358580 ps
CPU time 0.91 seconds
Started Oct 01 12:41:59 PM PDT 23
Finished Oct 01 12:42:00 PM PDT 23
Peak memory 206116 kb
Host smart-ab0bfa7a-c9aa-456a-904e-4ebd68b9ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637520387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1637520387
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.744035044
Short name T573
Test name
Test status
Simulation time 14656671 ps
CPU time 0.86 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 205148 kb
Host smart-bb4e3ae3-779f-4f44-af4d-71776d379652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744035044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.744035044
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1812244812
Short name T603
Test name
Test status
Simulation time 14347788 ps
CPU time 0.89 seconds
Started Oct 01 12:42:03 PM PDT 23
Finished Oct 01 12:42:04 PM PDT 23
Peak memory 214552 kb
Host smart-3eef9e38-9926-472b-9df0-0e778b7bd5cb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812244812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1812244812
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1067808300
Short name T58
Test name
Test status
Simulation time 18838180 ps
CPU time 0.95 seconds
Started Oct 01 12:42:09 PM PDT 23
Finished Oct 01 12:42:10 PM PDT 23
Peak memory 214564 kb
Host smart-249dcc77-3348-4153-8564-61730c5a4cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067808300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1067808300
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.3179145124
Short name T7
Test name
Test status
Simulation time 20190292 ps
CPU time 1.14 seconds
Started Oct 01 12:41:51 PM PDT 23
Finished Oct 01 12:41:53 PM PDT 23
Peak memory 214432 kb
Host smart-0562c22d-eccd-469e-a84e-f5c7077cb13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179145124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3179145124
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2756101671
Short name T678
Test name
Test status
Simulation time 27988760 ps
CPU time 0.79 seconds
Started Oct 01 12:42:06 PM PDT 23
Finished Oct 01 12:42:07 PM PDT 23
Peak memory 214692 kb
Host smart-8269c98d-f494-4b19-88ce-45fc6605bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756101671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2756101671
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2400236263
Short name T707
Test name
Test status
Simulation time 35115484 ps
CPU time 0.81 seconds
Started Oct 01 12:41:33 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 204860 kb
Host smart-c507ee77-9a2a-4a37-ad72-1d6da8a831d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400236263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2400236263
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3163022277
Short name T664
Test name
Test status
Simulation time 218823918918 ps
CPU time 1161.48 seconds
Started Oct 01 12:42:01 PM PDT 23
Finished Oct 01 01:01:22 PM PDT 23
Peak memory 215804 kb
Host smart-5b32b70c-b216-45f2-af67-591b1b5ae9ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163022277 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3163022277
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert_test.234818530
Short name T459
Test name
Test status
Simulation time 31880347 ps
CPU time 0.88 seconds
Started Oct 01 12:42:00 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 205152 kb
Host smart-f920c59b-f283-4ca5-aebe-559ae85607bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234818530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.234818530
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_err.1115901324
Short name T728
Test name
Test status
Simulation time 72580244 ps
CPU time 1.09 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 221988 kb
Host smart-615f10dc-eee6-4d92-af2f-067a20982ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115901324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1115901324
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4124210730
Short name T474
Test name
Test status
Simulation time 17223064 ps
CPU time 0.94 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 204996 kb
Host smart-b3414098-ea50-4aa4-87f6-630e7ecfa400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124210730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4124210730
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2559133310
Short name T482
Test name
Test status
Simulation time 26566094 ps
CPU time 1.06 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:06 PM PDT 23
Peak memory 214524 kb
Host smart-0db12ea2-931f-4a5d-9669-ce327b57381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559133310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2559133310
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1511222081
Short name T513
Test name
Test status
Simulation time 30147921 ps
CPU time 1.06 seconds
Started Oct 01 12:42:00 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 205432 kb
Host smart-ed705084-46e9-41e2-b005-d2f8db695632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511222081 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1511222081
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3565423563
Short name T588
Test name
Test status
Simulation time 364313040 ps
CPU time 2.16 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 205556 kb
Host smart-b374f58e-8e3a-4ec2-ade8-6e14f35b1719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565423563 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3565423563
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_alert_test.1164475434
Short name T309
Test name
Test status
Simulation time 33824874 ps
CPU time 0.84 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 204664 kb
Host smart-b8f4bf54-f3d4-4932-ad67-aa89cd88e2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164475434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1164475434
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3133088416
Short name T673
Test name
Test status
Simulation time 15939946 ps
CPU time 0.93 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:53 PM PDT 23
Peak memory 214660 kb
Host smart-4e55f7da-bb92-40fe-9831-e37128ccf0d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133088416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3133088416
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.418246542
Short name T175
Test name
Test status
Simulation time 27795811 ps
CPU time 0.84 seconds
Started Oct 01 12:41:49 PM PDT 23
Finished Oct 01 12:41:50 PM PDT 23
Peak memory 215428 kb
Host smart-23b16680-9c9a-4443-ba19-0420bda11b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418246542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.418246542
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1769777065
Short name T712
Test name
Test status
Simulation time 185410591 ps
CPU time 1.42 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 205588 kb
Host smart-012ff1d7-29df-4490-b334-e72b4b3ac905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769777065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1769777065
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1455044830
Short name T2
Test name
Test status
Simulation time 30524213 ps
CPU time 1 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:58 PM PDT 23
Peak memory 221756 kb
Host smart-857f1d5b-37ed-4124-949b-c41a196776b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455044830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1455044830
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4088255642
Short name T624
Test name
Test status
Simulation time 32665181 ps
CPU time 0.85 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 204648 kb
Host smart-fe3e1d86-bff8-4637-bb4d-b64358bca568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088255642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4088255642
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1994629473
Short name T669
Test name
Test status
Simulation time 61535180 ps
CPU time 1.43 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 206080 kb
Host smart-8ce4d77f-aa98-43d1-8a68-23d8afd9e63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994629473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1994629473
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4235336427
Short name T716
Test name
Test status
Simulation time 141415315759 ps
CPU time 1458.02 seconds
Started Oct 01 12:41:59 PM PDT 23
Finished Oct 01 01:06:17 PM PDT 23
Peak memory 220832 kb
Host smart-7ada5108-7d59-43b2-b7e1-8430826e67e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235336427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4235336427
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.132217293
Short name T662
Test name
Test status
Simulation time 173335549 ps
CPU time 0.9 seconds
Started Oct 01 12:41:38 PM PDT 23
Finished Oct 01 12:41:39 PM PDT 23
Peak memory 206040 kb
Host smart-9e47c4ad-b277-4ca1-a9eb-1e0bac9c318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132217293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.132217293
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2601453971
Short name T600
Test name
Test status
Simulation time 32998231 ps
CPU time 0.73 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 204264 kb
Host smart-b9d2cffc-7d39-4440-bf2d-484e4b554775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601453971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2601453971
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1152783792
Short name T123
Test name
Test status
Simulation time 10624658 ps
CPU time 0.8 seconds
Started Oct 01 12:42:00 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 214340 kb
Host smart-3ed46599-9fe5-40ee-8170-4865ac97a80e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152783792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1152783792
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2089956417
Short name T523
Test name
Test status
Simulation time 31417381 ps
CPU time 0.97 seconds
Started Oct 01 12:41:48 PM PDT 23
Finished Oct 01 12:41:49 PM PDT 23
Peak memory 214664 kb
Host smart-3a1d76c2-1348-4740-ac92-e61a1240a5fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089956417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2089956417
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4191503937
Short name T158
Test name
Test status
Simulation time 20453968 ps
CPU time 1.05 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:41:59 PM PDT 23
Peak memory 222176 kb
Host smart-504c968d-93b9-4b0d-8f58-f6b477b46da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191503937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4191503937
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3176624942
Short name T715
Test name
Test status
Simulation time 39589817 ps
CPU time 1.47 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 214292 kb
Host smart-ac6dc477-7c7c-4043-8281-93504d2dbd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176624942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3176624942
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.1159433306
Short name T59
Test name
Test status
Simulation time 41252009 ps
CPU time 0.83 seconds
Started Oct 01 12:41:53 PM PDT 23
Finished Oct 01 12:41:54 PM PDT 23
Peak memory 204852 kb
Host smart-0dd9679d-cf26-43d5-883c-03e0ebcdefed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159433306 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1159433306
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2493499772
Short name T315
Test name
Test status
Simulation time 33319253 ps
CPU time 0.97 seconds
Started Oct 01 12:41:55 PM PDT 23
Finished Oct 01 12:41:56 PM PDT 23
Peak memory 204616 kb
Host smart-e0444fb2-e303-417d-acc8-6e95751faa28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493499772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2493499772
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2918145555
Short name T538
Test name
Test status
Simulation time 197578330227 ps
CPU time 742.95 seconds
Started Oct 01 12:41:44 PM PDT 23
Finished Oct 01 12:54:08 PM PDT 23
Peak memory 215448 kb
Host smart-707029b9-b5a1-4647-ab8a-6543435cc687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918145555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2918145555
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert_test.3808686179
Short name T76
Test name
Test status
Simulation time 45743193 ps
CPU time 1.31 seconds
Started Oct 01 12:41:57 PM PDT 23
Finished Oct 01 12:41:58 PM PDT 23
Peak memory 204748 kb
Host smart-bcacf727-c23f-44ca-af66-7325ce38c1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808686179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3808686179
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2381509343
Short name T83
Test name
Test status
Simulation time 30524299 ps
CPU time 0.94 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 214572 kb
Host smart-0ad6e078-07b9-46b0-a8bd-5e145f0727b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381509343 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2381509343
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1111132047
Short name T164
Test name
Test status
Simulation time 23302069 ps
CPU time 0.84 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:12 PM PDT 23
Peak memory 215268 kb
Host smart-79e0210e-ffdb-42eb-992a-90ae77732a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111132047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1111132047
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.923178822
Short name T31
Test name
Test status
Simulation time 51643096 ps
CPU time 1.07 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 205612 kb
Host smart-1f0d9c18-919b-4240-af60-3ce27c3855fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923178822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.923178822
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3251759282
Short name T586
Test name
Test status
Simulation time 81085649 ps
CPU time 0.94 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:41:59 PM PDT 23
Peak memory 221516 kb
Host smart-fd4d24eb-e777-444f-90dd-ec70253a7989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251759282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3251759282
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.9929615
Short name T464
Test name
Test status
Simulation time 18766755 ps
CPU time 0.88 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 205048 kb
Host smart-748a4a18-e90b-4f53-8783-7a4a19a2cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9929615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.9929615
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.836566508
Short name T680
Test name
Test status
Simulation time 175977224 ps
CPU time 3.47 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 206200 kb
Host smart-ad57115f-6238-43c8-a263-64951708a8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836566508 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.836566508
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2713147573
Short name T457
Test name
Test status
Simulation time 37055813798 ps
CPU time 446.4 seconds
Started Oct 01 12:41:57 PM PDT 23
Finished Oct 01 12:49:24 PM PDT 23
Peak memory 215268 kb
Host smart-4e3b8c67-00d2-43c5-b8db-14960a319078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713147573 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2713147573
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.2103338995
Short name T243
Test name
Test status
Simulation time 20205325 ps
CPU time 1.07 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 206180 kb
Host smart-e50ff00b-d44b-423b-91aa-53ad93461fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103338995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2103338995
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3448709034
Short name T608
Test name
Test status
Simulation time 15250404 ps
CPU time 0.77 seconds
Started Oct 01 12:41:33 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 204380 kb
Host smart-8a06b205-947f-4e5d-adf7-d31eff3a14c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448709034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3448709034
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.495037995
Short name T155
Test name
Test status
Simulation time 30613586 ps
CPU time 0.95 seconds
Started Oct 01 12:41:28 PM PDT 23
Finished Oct 01 12:41:29 PM PDT 23
Peak memory 214776 kb
Host smart-4c392a10-a1e4-4a80-8ef5-ab15e648cca5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495037995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.495037995
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_intr.3203424674
Short name T548
Test name
Test status
Simulation time 20716111 ps
CPU time 1.02 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 214464 kb
Host smart-2e9d4a6c-378a-4917-9920-7afa261e71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203424674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3203424674
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2203066141
Short name T280
Test name
Test status
Simulation time 46220620 ps
CPU time 0.9 seconds
Started Oct 01 12:41:29 PM PDT 23
Finished Oct 01 12:41:30 PM PDT 23
Peak memory 204692 kb
Host smart-a04c8832-9f15-4d70-94d1-b966c0af6ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203066141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2203066141
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3115093519
Short name T44
Test name
Test status
Simulation time 1332031565 ps
CPU time 6.17 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:38 PM PDT 23
Peak memory 233296 kb
Host smart-96866963-a780-453a-895c-dcb0b95d4965
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115093519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3115093519
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.222990681
Short name T681
Test name
Test status
Simulation time 14037359 ps
CPU time 0.89 seconds
Started Oct 01 12:41:20 PM PDT 23
Finished Oct 01 12:41:21 PM PDT 23
Peak memory 204768 kb
Host smart-2045d00d-f63c-4c88-8cfd-b89538781ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222990681 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.222990681
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.173702570
Short name T255
Test name
Test status
Simulation time 80617164 ps
CPU time 1.69 seconds
Started Oct 01 12:41:16 PM PDT 23
Finished Oct 01 12:41:18 PM PDT 23
Peak memory 205548 kb
Host smart-7460a53d-6083-432b-a791-46f2bff9557a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173702570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.173702570
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_alert.1331966310
Short name T11
Test name
Test status
Simulation time 20158095 ps
CPU time 0.97 seconds
Started Oct 01 12:41:57 PM PDT 23
Finished Oct 01 12:41:59 PM PDT 23
Peak memory 205228 kb
Host smart-3b1c909b-a78d-434e-a6f9-e24e762b56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331966310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1331966310
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2908588308
Short name T38
Test name
Test status
Simulation time 23679910 ps
CPU time 0.79 seconds
Started Oct 01 12:41:57 PM PDT 23
Finished Oct 01 12:41:58 PM PDT 23
Peak memory 204532 kb
Host smart-330789e8-8294-4e7f-94c2-dda4f92386a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908588308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2908588308
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1207519935
Short name T64
Test name
Test status
Simulation time 35569986 ps
CPU time 0.8 seconds
Started Oct 01 12:42:39 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 214356 kb
Host smart-1f3446bb-7292-4cb7-bf6f-5933555aff0d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207519935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1207519935
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.464913511
Short name T585
Test name
Test status
Simulation time 103197058 ps
CPU time 1.07 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214568 kb
Host smart-75027939-8b6d-47bc-ba45-c94743997b09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464913511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.464913511
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1327644602
Short name T170
Test name
Test status
Simulation time 18869946 ps
CPU time 0.99 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:41:59 PM PDT 23
Peak memory 215664 kb
Host smart-9ed150cc-3543-4ee2-8ccd-1dd7c5c09808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327644602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1327644602
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.669922987
Short name T57
Test name
Test status
Simulation time 129924793 ps
CPU time 1.09 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 205240 kb
Host smart-a1666054-ba12-44d2-9fbf-0d743aa51b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669922987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.669922987
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2325508050
Short name T623
Test name
Test status
Simulation time 63722091 ps
CPU time 0.91 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 221348 kb
Host smart-daf90369-a8cd-421b-ba7c-352155f3044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325508050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2325508050
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.4028681137
Short name T527
Test name
Test status
Simulation time 23940294 ps
CPU time 0.82 seconds
Started Oct 01 12:41:56 PM PDT 23
Finished Oct 01 12:41:57 PM PDT 23
Peak memory 204896 kb
Host smart-31bfc331-7fe6-49f5-a22d-461e3e205927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028681137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4028681137
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1553699493
Short name T60
Test name
Test status
Simulation time 234487992 ps
CPU time 1.79 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:56 PM PDT 23
Peak memory 205464 kb
Host smart-00db2334-bcab-47ea-a0e5-d42160764011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553699493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1553699493
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.484848467
Short name T592
Test name
Test status
Simulation time 100196947898 ps
CPU time 472.92 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:50:04 PM PDT 23
Peak memory 214620 kb
Host smart-3acf6b53-5a69-422b-a582-94b9fa943e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484848467 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.484848467
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.2378115564
Short name T516
Test name
Test status
Simulation time 286498049 ps
CPU time 0.91 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 205156 kb
Host smart-5f071cbe-7a91-402e-887a-36c9746fb35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378115564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2378115564
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2978633523
Short name T644
Test name
Test status
Simulation time 38434931 ps
CPU time 0.95 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 204556 kb
Host smart-4b9d920c-de3e-4242-ab99-9445833e2b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978633523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2978633523
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2202103653
Short name T238
Test name
Test status
Simulation time 22573291 ps
CPU time 0.89 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 214448 kb
Host smart-cb7afa67-1979-4900-b720-c2ecf31cfa3e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202103653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2202103653
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.378299709
Short name T676
Test name
Test status
Simulation time 66098118 ps
CPU time 0.98 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 214592 kb
Host smart-bd5764ca-5a05-450a-8b40-0bc575f4f0a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378299709 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.378299709
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4271060612
Short name T139
Test name
Test status
Simulation time 19984373 ps
CPU time 0.97 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 214392 kb
Host smart-e6bd77d7-9efe-42b1-8e1f-eb80b28c169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271060612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4271060612
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3645346809
Short name T544
Test name
Test status
Simulation time 43554955 ps
CPU time 0.88 seconds
Started Oct 01 12:42:00 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 204852 kb
Host smart-b721b247-0fb5-4c6e-bd86-c170396e26a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645346809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3645346809
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3665895224
Short name T545
Test name
Test status
Simulation time 30340645 ps
CPU time 1 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 221504 kb
Host smart-5c468a70-c7b4-47ce-949d-997e0a14ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665895224 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3665895224
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2572671121
Short name T714
Test name
Test status
Simulation time 42044536 ps
CPU time 0.83 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 204648 kb
Host smart-17f93f03-bc2e-4eca-9d9b-3f60a650568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572671121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2572671121
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1526096669
Short name T529
Test name
Test status
Simulation time 212017167 ps
CPU time 2.67 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 206060 kb
Host smart-7ca78320-b452-47f5-87c1-3ebf56d9cfbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526096669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1526096669
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2494454969
Short name T563
Test name
Test status
Simulation time 237913339296 ps
CPU time 897.83 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:57:38 PM PDT 23
Peak memory 214708 kb
Host smart-6b3ec0e5-59b2-4d10-ae04-1b72504986ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494454969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2494454969
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.3545826980
Short name T688
Test name
Test status
Simulation time 221141976 ps
CPU time 0.93 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 206036 kb
Host smart-6b801c28-ffdc-4b0a-81ae-1262dd4fd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545826980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3545826980
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.4180343007
Short name T327
Test name
Test status
Simulation time 12676555 ps
CPU time 0.83 seconds
Started Oct 01 12:42:06 PM PDT 23
Finished Oct 01 12:42:07 PM PDT 23
Peak memory 204528 kb
Host smart-69919565-9d7c-4579-9aa8-04f3b0bb96ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180343007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.4180343007
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2085594269
Short name T71
Test name
Test status
Simulation time 12483664 ps
CPU time 0.87 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 214464 kb
Host smart-8205c888-a65e-4e5c-bfc8-d89061a2cbc2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085594269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2085594269
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1085702922
Short name T118
Test name
Test status
Simulation time 30108598 ps
CPU time 1.05 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 214672 kb
Host smart-66b04fd5-77f0-456a-8b3b-1b93a22f0845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085702922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1085702922
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.785057299
Short name T5
Test name
Test status
Simulation time 36241526 ps
CPU time 0.88 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:42:27 PM PDT 23
Peak memory 214488 kb
Host smart-33fc5128-0136-421d-a921-ee0d012a0bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785057299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.785057299
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4136612342
Short name T267
Test name
Test status
Simulation time 14388154 ps
CPU time 0.94 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 205124 kb
Host smart-e9f11986-a14f-4cd2-bcd2-e825add05160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136612342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4136612342
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1962933923
Short name T499
Test name
Test status
Simulation time 58271629 ps
CPU time 0.85 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 214440 kb
Host smart-f3ccc743-ecdc-4445-bdbe-c3bfe0fdfddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962933923 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1962933923
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2681304993
Short name T646
Test name
Test status
Simulation time 14299991 ps
CPU time 0.9 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 204892 kb
Host smart-aa8d98b2-9003-4752-816d-96eaf18c19aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681304993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2681304993
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4034689718
Short name T452
Test name
Test status
Simulation time 236012200 ps
CPU time 2.94 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 205428 kb
Host smart-97499687-4ed9-40d7-bba3-7e2546a44b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034689718 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4034689718
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1609219681
Short name T578
Test name
Test status
Simulation time 122849115477 ps
CPU time 881.33 seconds
Started Oct 01 12:41:59 PM PDT 23
Finished Oct 01 12:56:41 PM PDT 23
Peak memory 214620 kb
Host smart-e4ac8410-d360-4947-b982-cfc7b14dd042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609219681 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1609219681
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.1346747335
Short name T73
Test name
Test status
Simulation time 19458942 ps
CPU time 0.93 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 205124 kb
Host smart-39ca41eb-36fe-4353-b6ad-a3e65ee9c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346747335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1346747335
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.3635418098
Short name T298
Test name
Test status
Simulation time 29222497 ps
CPU time 0.9 seconds
Started Oct 01 12:42:07 PM PDT 23
Finished Oct 01 12:42:08 PM PDT 23
Peak memory 204644 kb
Host smart-6864464d-faa3-4178-a6f4-179180c902ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635418098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3635418098
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2116108385
Short name T133
Test name
Test status
Simulation time 90218242 ps
CPU time 1 seconds
Started Oct 01 12:42:07 PM PDT 23
Finished Oct 01 12:42:08 PM PDT 23
Peak memory 214624 kb
Host smart-acda1564-169e-4ead-9d3d-6871f0911472
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116108385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2116108385
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3640698372
Short name T677
Test name
Test status
Simulation time 29794482 ps
CPU time 1.21 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 216764 kb
Host smart-dc643c46-e8a5-4023-9f6a-7c3e5676960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640698372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3640698372
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.965819966
Short name T100
Test name
Test status
Simulation time 65884913 ps
CPU time 1.26 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 205680 kb
Host smart-95d7b52a-35e1-4a27-b6c5-31f0b8fc09b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965819966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.965819966
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.382828893
Short name T320
Test name
Test status
Simulation time 68583159 ps
CPU time 0.86 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 204856 kb
Host smart-6e2c3a92-11aa-4584-9169-62e0329fc274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382828893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.382828893
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3712399849
Short name T512
Test name
Test status
Simulation time 22424691 ps
CPU time 1.04 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 205000 kb
Host smart-107242c7-17a8-4bb2-adec-a3c20bd95f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712399849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3712399849
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3118270871
Short name T178
Test name
Test status
Simulation time 79592901885 ps
CPU time 493.8 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:50:34 PM PDT 23
Peak memory 215444 kb
Host smart-705cedb1-7eab-46ef-98a1-d26324b27698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118270871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3118270871
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.1269624385
Short name T80
Test name
Test status
Simulation time 118561316 ps
CPU time 0.9 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 205012 kb
Host smart-431ccfe4-4778-4a07-8ff2-90ab9700ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269624385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1269624385
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4049010380
Short name T687
Test name
Test status
Simulation time 19735656 ps
CPU time 0.97 seconds
Started Oct 01 12:41:54 PM PDT 23
Finished Oct 01 12:41:55 PM PDT 23
Peak memory 204684 kb
Host smart-8f190fe3-c32c-4a26-86d8-5d8479b8b61c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049010380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4049010380
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1731596680
Short name T168
Test name
Test status
Simulation time 40500221 ps
CPU time 0.85 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214432 kb
Host smart-1862c36d-e08a-4841-84e6-d916c27a0a18
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731596680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1731596680
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.815563996
Short name T165
Test name
Test status
Simulation time 19130199 ps
CPU time 1.01 seconds
Started Oct 01 12:42:08 PM PDT 23
Finished Oct 01 12:42:10 PM PDT 23
Peak memory 215668 kb
Host smart-4f81877c-ea18-4670-a059-7921338cb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815563996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.815563996
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.3808339459
Short name T718
Test name
Test status
Simulation time 21511116 ps
CPU time 0.94 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:11 PM PDT 23
Peak memory 214820 kb
Host smart-316db9a1-226a-42b3-b02e-aaa3831b6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808339459 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3808339459
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2804247002
Short name T567
Test name
Test status
Simulation time 81006234 ps
CPU time 0.85 seconds
Started Oct 01 12:41:59 PM PDT 23
Finished Oct 01 12:42:01 PM PDT 23
Peak memory 204964 kb
Host smart-b1171d9a-ad25-4fef-a927-4db4cb4426cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804247002 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2804247002
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.4285129916
Short name T468
Test name
Test status
Simulation time 422977652 ps
CPU time 2.46 seconds
Started Oct 01 12:42:09 PM PDT 23
Finished Oct 01 12:42:12 PM PDT 23
Peak memory 205736 kb
Host smart-12ba4aad-fc91-4c8d-b460-c5d1760eac3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285129916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4285129916
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1159633600
Short name T610
Test name
Test status
Simulation time 119407539786 ps
CPU time 643.53 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:52:49 PM PDT 23
Peak memory 215056 kb
Host smart-527891e3-4143-4c31-8d99-eb0695c4b062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159633600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1159633600
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.2358155058
Short name T539
Test name
Test status
Simulation time 36968232 ps
CPU time 0.88 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 206072 kb
Host smart-a914720f-4763-458d-98bf-9bee2f836fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358155058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2358155058
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1457702331
Short name T517
Test name
Test status
Simulation time 52134048 ps
CPU time 0.95 seconds
Started Oct 01 12:42:02 PM PDT 23
Finished Oct 01 12:42:03 PM PDT 23
Peak memory 205548 kb
Host smart-6091b779-66b3-4ec9-85d5-07382c97ac95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457702331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1457702331
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3784285455
Short name T70
Test name
Test status
Simulation time 12022630 ps
CPU time 0.91 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 214576 kb
Host smart-ef5e7c24-cae5-4953-84df-4a8afd92220a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784285455 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3784285455
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1145349320
Short name T453
Test name
Test status
Simulation time 19095476 ps
CPU time 1.16 seconds
Started Oct 01 12:42:03 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 215540 kb
Host smart-de625626-df9b-4397-a8ce-a1768751c1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145349320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1145349320
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.3704956086
Short name T543
Test name
Test status
Simulation time 27616173 ps
CPU time 0.9 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 214400 kb
Host smart-b94813e7-5457-4815-949d-c61a989d0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704956086 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3704956086
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1354485692
Short name T700
Test name
Test status
Simulation time 13602307 ps
CPU time 0.87 seconds
Started Oct 01 12:42:01 PM PDT 23
Finished Oct 01 12:42:02 PM PDT 23
Peak memory 204688 kb
Host smart-58fef834-017f-4957-8155-286a1c429e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354485692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1354485692
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1379294063
Short name T510
Test name
Test status
Simulation time 301622115 ps
CPU time 3.94 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 206028 kb
Host smart-1cc40b35-0066-48c5-ac90-db9b625d247f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379294063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1379294063
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_alert.675052412
Short name T247
Test name
Test status
Simulation time 58773935 ps
CPU time 0.9 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 205188 kb
Host smart-c36443ce-7204-4d16-b182-e1a0b68e6dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675052412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.675052412
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.577308027
Short name T630
Test name
Test status
Simulation time 124755407 ps
CPU time 0.85 seconds
Started Oct 01 12:42:30 PM PDT 23
Finished Oct 01 12:42:36 PM PDT 23
Peak memory 205220 kb
Host smart-0e9071ac-6d6a-4002-a491-c7a98b903e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577308027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.577308027
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3762421133
Short name T652
Test name
Test status
Simulation time 97301030 ps
CPU time 0.98 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 216480 kb
Host smart-3c3ea5b5-6d1b-46e9-822d-40ad872ef3e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762421133 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3762421133
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2360576
Short name T466
Test name
Test status
Simulation time 20704051 ps
CPU time 1.08 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 215880 kb
Host smart-facf44dd-5bda-422d-ae44-2681ca71bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2360576
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3537368102
Short name T310
Test name
Test status
Simulation time 102809468 ps
CPU time 1.23 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 214392 kb
Host smart-c40d7227-8825-4889-9a7e-9a26df994dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537368102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3537368102
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2950475520
Short name T30
Test name
Test status
Simulation time 31317790 ps
CPU time 0.83 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214500 kb
Host smart-b6cc9e3d-783b-4e93-891c-dcb5b8c66322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950475520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2950475520
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.79676416
Short name T642
Test name
Test status
Simulation time 30375482 ps
CPU time 0.89 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:11 PM PDT 23
Peak memory 204880 kb
Host smart-f98482d0-3fd1-4878-a17c-59debe973400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79676416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.79676416
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1208247061
Short name T619
Test name
Test status
Simulation time 47782658 ps
CPU time 0.89 seconds
Started Oct 01 12:42:09 PM PDT 23
Finished Oct 01 12:42:10 PM PDT 23
Peak memory 204376 kb
Host smart-abd6d2fe-7430-4bde-8dca-836bd899bd01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208247061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1208247061
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1709470165
Short name T559
Test name
Test status
Simulation time 17220220233 ps
CPU time 205.44 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:45:48 PM PDT 23
Peak memory 215324 kb
Host smart-176cc3b0-0d56-4243-a863-82aa4b32b485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709470165 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1709470165
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.1663628791
Short name T665
Test name
Test status
Simulation time 15687397 ps
CPU time 0.97 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 206184 kb
Host smart-9669b14d-8fc8-40d8-9755-70c84f4a2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663628791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1663628791
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3215784600
Short name T598
Test name
Test status
Simulation time 22405215 ps
CPU time 0.84 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 204580 kb
Host smart-b26c42e6-5037-4b3f-ab6c-9fb4a859b7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215784600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3215784600
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2981754849
Short name T63
Test name
Test status
Simulation time 12214332 ps
CPU time 0.85 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:11 PM PDT 23
Peak memory 214408 kb
Host smart-2909b6d2-af3c-4f3c-a857-9993a413dd80
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981754849 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2981754849
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3430314393
Short name T481
Test name
Test status
Simulation time 23963966 ps
CPU time 1.01 seconds
Started Oct 01 12:42:09 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 214644 kb
Host smart-12120f6e-6c48-419f-8e58-c3507e31930e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430314393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3430314393
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4082781963
Short name T709
Test name
Test status
Simulation time 26109894 ps
CPU time 1.14 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 228684 kb
Host smart-702c1830-01fa-4d0b-b078-8b3785f02ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082781963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4082781963
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.336069565
Short name T89
Test name
Test status
Simulation time 188800240 ps
CPU time 1.32 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 214344 kb
Host smart-8afa1ff5-75b1-45c1-9315-21b82ba5501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336069565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.336069565
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.125270941
Short name T317
Test name
Test status
Simulation time 35538236 ps
CPU time 0.85 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 214436 kb
Host smart-603b1c42-a9be-4e5a-a2f7-4e7b069901f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125270941 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.125270941
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1747049760
Short name T629
Test name
Test status
Simulation time 15919547 ps
CPU time 0.9 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 204676 kb
Host smart-b3ed6429-5553-480b-aea5-6bdf937b2803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747049760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1747049760
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.402338224
Short name T112
Test name
Test status
Simulation time 646107105 ps
CPU time 2.44 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 205780 kb
Host smart-00b2a01d-2c51-47c9-b4fb-9206e27e4b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402338224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.402338224
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.933667489
Short name T615
Test name
Test status
Simulation time 271813388794 ps
CPU time 1762.42 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 01:11:36 PM PDT 23
Peak memory 221232 kb
Host smart-7f77a626-59e3-4db9-8a86-1507207beca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933667489 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.933667489
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.2135599648
Short name T291
Test name
Test status
Simulation time 82514802 ps
CPU time 0.93 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 206112 kb
Host smart-97c9b2fd-f3d3-47e2-9b28-a2fdfb49efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135599648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2135599648
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2085781385
Short name T502
Test name
Test status
Simulation time 30529320 ps
CPU time 0.81 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 204592 kb
Host smart-b0d28e90-1966-490e-b9f5-18535f796ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085781385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2085781385
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.23347599
Short name T717
Test name
Test status
Simulation time 14561148 ps
CPU time 0.9 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214528 kb
Host smart-193cafbd-d0a8-41cd-80c9-30d7b51b033c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347599 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.23347599
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1074237727
Short name T522
Test name
Test status
Simulation time 200174405 ps
CPU time 1.15 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 214640 kb
Host smart-622c6e97-ac8a-48e3-a3df-bdcd83f2c2f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074237727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1074237727
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.611397787
Short name T314
Test name
Test status
Simulation time 20141768 ps
CPU time 1.13 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 221496 kb
Host smart-6601b805-e2fb-4623-85ac-5cbe223cdd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611397787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.611397787
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_intr.2189215688
Short name T645
Test name
Test status
Simulation time 19687607 ps
CPU time 1.03 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214492 kb
Host smart-5fe1540c-1f4c-4699-97d4-6362a1de3a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189215688 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2189215688
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.535064350
Short name T300
Test name
Test status
Simulation time 32331052 ps
CPU time 0.82 seconds
Started Oct 01 12:42:10 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 204680 kb
Host smart-20a5b177-34b2-47e3-bd1b-37efa541ad62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535064350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.535064350
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1117073600
Short name T193
Test name
Test status
Simulation time 203114937 ps
CPU time 4.09 seconds
Started Oct 01 12:42:59 PM PDT 23
Finished Oct 01 12:43:04 PM PDT 23
Peak memory 206160 kb
Host smart-a5c49bbf-7fe5-4045-a16a-f59dd6c40d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117073600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1117073600
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.632996081
Short name T465
Test name
Test status
Simulation time 19043398934 ps
CPU time 460.92 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:49:40 PM PDT 23
Peak memory 214572 kb
Host smart-f6513b65-6442-418f-b21b-5596d50afcca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632996081 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.632996081
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.3129092751
Short name T285
Test name
Test status
Simulation time 20399602 ps
CPU time 0.99 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 206196 kb
Host smart-eba2d611-6dd3-4557-8743-4fa329127427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129092751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3129092751
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1180429976
Short name T575
Test name
Test status
Simulation time 30201977 ps
CPU time 0.86 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 204584 kb
Host smart-ff62ca53-ace5-44d0-8df8-f686441cf34b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180429976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1180429976
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2039283709
Short name T569
Test name
Test status
Simulation time 12019905 ps
CPU time 0.82 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 214480 kb
Host smart-b6b727d0-d6a1-4d5c-8088-88dcf633653f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039283709 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2039283709
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1423276850
Short name T605
Test name
Test status
Simulation time 68016577 ps
CPU time 0.95 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 214676 kb
Host smart-10b685b1-9e4a-4d6f-9b28-b937792cfe7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423276850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1423276850
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3286498526
Short name T307
Test name
Test status
Simulation time 51967205 ps
CPU time 0.77 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 214360 kb
Host smart-e73971c5-3a78-4bac-9650-64d4f0f87cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286498526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3286498526
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2412307774
Short name T519
Test name
Test status
Simulation time 92084427 ps
CPU time 1.21 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214352 kb
Host smart-f89234da-71ab-4348-b539-4e15dacb35a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412307774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2412307774
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1575765374
Short name T520
Test name
Test status
Simulation time 25541671 ps
CPU time 1 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:27 PM PDT 23
Peak memory 221700 kb
Host smart-5317fa78-8d61-41c6-8064-4affe46e0d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575765374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1575765374
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1310721841
Short name T455
Test name
Test status
Simulation time 148997311 ps
CPU time 0.84 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 204812 kb
Host smart-fe05c33c-976b-458f-8498-c36cc3e31606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310721841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1310721841
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.4258007032
Short name T564
Test name
Test status
Simulation time 39502038 ps
CPU time 0.99 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:42:00 PM PDT 23
Peak memory 204384 kb
Host smart-3209cf1f-46f6-40d2-b304-130484cb4cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258007032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4258007032
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3905838983
Short name T498
Test name
Test status
Simulation time 41622258179 ps
CPU time 731.47 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:54:31 PM PDT 23
Peak memory 215024 kb
Host smart-822acb10-2502-4493-87f9-f6bf601922ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905838983 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3905838983
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.1931658854
Short name T702
Test name
Test status
Simulation time 64414296 ps
CPU time 0.94 seconds
Started Oct 01 12:41:36 PM PDT 23
Finished Oct 01 12:41:37 PM PDT 23
Peak memory 205284 kb
Host smart-892ff207-389d-429c-beb9-64c845ad3c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931658854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1931658854
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.173967535
Short name T16
Test name
Test status
Simulation time 16171408 ps
CPU time 0.94 seconds
Started Oct 01 12:41:15 PM PDT 23
Finished Oct 01 12:41:16 PM PDT 23
Peak memory 205408 kb
Host smart-2028f060-fd1b-401b-afc6-3f28baefd4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173967535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.173967535
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.238573879
Short name T152
Test name
Test status
Simulation time 35007448 ps
CPU time 1 seconds
Started Oct 01 12:41:28 PM PDT 23
Finished Oct 01 12:41:29 PM PDT 23
Peak memory 214676 kb
Host smart-baa850a9-0747-4863-8930-1970e345214a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238573879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.238573879
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.968705259
Short name T706
Test name
Test status
Simulation time 24394443 ps
CPU time 1.04 seconds
Started Oct 01 12:41:13 PM PDT 23
Finished Oct 01 12:41:14 PM PDT 23
Peak memory 222128 kb
Host smart-c07865a2-2202-4eeb-829d-dd110ae3f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968705259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.968705259
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3852229396
Short name T571
Test name
Test status
Simulation time 28221694 ps
CPU time 1.09 seconds
Started Oct 01 12:41:29 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 205608 kb
Host smart-d85345f8-77c7-415a-8070-80e00263c792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852229396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3852229396
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1210342423
Short name T492
Test name
Test status
Simulation time 19026857 ps
CPU time 1.1 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:32 PM PDT 23
Peak memory 221696 kb
Host smart-439ce6c1-e144-4c68-b152-f597333f7b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210342423 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1210342423
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2185918564
Short name T277
Test name
Test status
Simulation time 13311809 ps
CPU time 0.87 seconds
Started Oct 01 12:41:20 PM PDT 23
Finished Oct 01 12:41:21 PM PDT 23
Peak memory 204916 kb
Host smart-09e472b6-8cba-472a-ba45-0110ecc65dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185918564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2185918564
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.781936835
Short name T19
Test name
Test status
Simulation time 417383038 ps
CPU time 6.36 seconds
Started Oct 01 12:41:41 PM PDT 23
Finished Oct 01 12:41:48 PM PDT 23
Peak memory 233972 kb
Host smart-45bf77f9-95e1-4369-a6ea-80a0c63dc7b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781936835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.781936835
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2391812986
Short name T722
Test name
Test status
Simulation time 18373039 ps
CPU time 0.84 seconds
Started Oct 01 12:41:16 PM PDT 23
Finished Oct 01 12:41:17 PM PDT 23
Peak memory 204724 kb
Host smart-25a9a662-64bb-4d39-8b7d-20c787ef44c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391812986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2391812986
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1029294335
Short name T540
Test name
Test status
Simulation time 32148983 ps
CPU time 1.13 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:26 PM PDT 23
Peak memory 204820 kb
Host smart-178ba20e-66ec-49ff-802f-3cbc3b66ff86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029294335 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1029294335
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3279314479
Short name T701
Test name
Test status
Simulation time 98024029726 ps
CPU time 471.64 seconds
Started Oct 01 12:41:17 PM PDT 23
Finished Oct 01 12:49:09 PM PDT 23
Peak memory 216188 kb
Host smart-453c52da-9190-4350-879b-35d36aa81b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279314479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3279314479
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1902854067
Short name T721
Test name
Test status
Simulation time 16344785 ps
CPU time 0.94 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 205088 kb
Host smart-24122754-7091-46e7-bcdc-f6346b66985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902854067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1902854067
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3933124254
Short name T668
Test name
Test status
Simulation time 20696344 ps
CPU time 0.81 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 204360 kb
Host smart-28efaed1-6c00-4de6-9a5c-e80717be2ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933124254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3933124254
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2355086796
Short name T88
Test name
Test status
Simulation time 11433281 ps
CPU time 0.84 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 214376 kb
Host smart-ce952325-a5b2-4288-9ffd-a6e2e5544a36
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355086796 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2355086796
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.881742476
Short name T694
Test name
Test status
Simulation time 17127912 ps
CPU time 0.92 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 214684 kb
Host smart-d9ec24a8-557c-4b3b-92f6-6425efc8e4c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881742476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.881742476
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3545361736
Short name T541
Test name
Test status
Simulation time 21193380 ps
CPU time 1.03 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 215700 kb
Host smart-4c655eb8-f8b5-48fc-947e-e6ff3f98f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545361736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3545361736
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.251067269
Short name T476
Test name
Test status
Simulation time 46073054 ps
CPU time 1.11 seconds
Started Oct 01 12:42:29 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 205016 kb
Host smart-bd75ae83-7503-4f61-a024-2e3fee2e708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251067269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.251067269
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.754110679
Short name T561
Test name
Test status
Simulation time 26520575 ps
CPU time 1.02 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 221780 kb
Host smart-8959da88-2ea1-4a63-a723-9745bee7e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754110679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.754110679
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3332465600
Short name T322
Test name
Test status
Simulation time 26890033 ps
CPU time 0.8 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 204712 kb
Host smart-4a15e51b-b3c8-48b6-8c36-e6f2b0771685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332465600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3332465600
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.566870359
Short name T191
Test name
Test status
Simulation time 302047984 ps
CPU time 1.74 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 205468 kb
Host smart-601b3383-f739-4efa-a4c7-1fa0597b7e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566870359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.566870359
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.47611541
Short name T604
Test name
Test status
Simulation time 190883860875 ps
CPU time 550.05 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:51:26 PM PDT 23
Peak memory 215120 kb
Host smart-77f28ab3-5647-4a0b-b4da-d7533fd7b918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47611541 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.47611541
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.4181590257
Short name T627
Test name
Test status
Simulation time 56456893 ps
CPU time 0.89 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 206076 kb
Host smart-68a59e4a-4dfd-4536-9ec8-123768907c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181590257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4181590257
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.249782110
Short name T303
Test name
Test status
Simulation time 48091954 ps
CPU time 0.85 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 204360 kb
Host smart-d4c90894-c55f-499f-a667-ae2c320058ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249782110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.249782110
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2330993675
Short name T145
Test name
Test status
Simulation time 134699512 ps
CPU time 1.07 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 214664 kb
Host smart-d084319a-118d-4a8e-bca8-c94e12e54c15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330993675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2330993675
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.234650028
Short name T151
Test name
Test status
Simulation time 62932290 ps
CPU time 1.03 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214616 kb
Host smart-985de9f5-0c5e-4a72-ab58-eb3eefa6dfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234650028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.234650028
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1192125781
Short name T508
Test name
Test status
Simulation time 16118110 ps
CPU time 1 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 205480 kb
Host smart-e0e30486-7288-4798-bc1c-419ab2cadebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192125781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1192125781
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2682825083
Short name T456
Test name
Test status
Simulation time 21968324 ps
CPU time 0.92 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 214524 kb
Host smart-b2d8825a-3f5f-4c32-b407-8facfcb9e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682825083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2682825083
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1036830574
Short name T48
Test name
Test status
Simulation time 38639049 ps
CPU time 0.82 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 204848 kb
Host smart-80744a3f-084b-4e05-8501-69efdd4c5ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036830574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1036830574
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.34848351
Short name T674
Test name
Test status
Simulation time 360192771 ps
CPU time 4.03 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 206196 kb
Host smart-804cc4b6-e817-460f-830a-6d86cc4e2f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848351 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.34848351
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1940619822
Short name T704
Test name
Test status
Simulation time 606932382243 ps
CPU time 1764.49 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 01:11:43 PM PDT 23
Peak memory 220632 kb
Host smart-89a9d9c2-a186-4cae-ac79-63f59ee2e5f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940619822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1940619822
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.52384502
Short name T729
Test name
Test status
Simulation time 39116871 ps
CPU time 0.97 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:12 PM PDT 23
Peak memory 205260 kb
Host smart-b390d11e-7737-40d2-b73a-25256ec35ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52384502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.52384502
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.403294828
Short name T68
Test name
Test status
Simulation time 21559566 ps
CPU time 0.8 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 204360 kb
Host smart-e2aa5201-21be-4cf4-96d8-8a3753cbc307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403294828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.403294828
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1091790909
Short name T122
Test name
Test status
Simulation time 10579794 ps
CPU time 0.82 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 214464 kb
Host smart-2f4b5ebc-1996-4c24-bdc4-b65347bd8211
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091790909 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1091790909
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4175057294
Short name T56
Test name
Test status
Simulation time 60087617 ps
CPU time 0.92 seconds
Started Oct 01 12:42:08 PM PDT 23
Finished Oct 01 12:42:09 PM PDT 23
Peak memory 214560 kb
Host smart-8754e12b-7853-42c5-b88c-a0581b3df808
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175057294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4175057294
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.384315379
Short name T199
Test name
Test status
Simulation time 22782137 ps
CPU time 0.91 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 215488 kb
Host smart-5095e5e2-160d-42ae-af24-bdfafac9a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384315379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.384315379
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2341288841
Short name T265
Test name
Test status
Simulation time 62541694 ps
CPU time 1.01 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 205328 kb
Host smart-5003aa45-4e90-4bc5-aa56-8f91388e4529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341288841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2341288841
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2182560630
Short name T526
Test name
Test status
Simulation time 19139431 ps
CPU time 1 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214484 kb
Host smart-7c23a2b0-3405-4ace-b3db-3c9c99e1243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182560630 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2182560630
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3962102484
Short name T611
Test name
Test status
Simulation time 17449446 ps
CPU time 0.93 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 204884 kb
Host smart-dcde7e24-9e2b-4fae-9f3e-3c3d89cbd9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962102484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3962102484
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.646002309
Short name T308
Test name
Test status
Simulation time 90726824 ps
CPU time 2.38 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 205884 kb
Host smart-0801d06b-6082-47b0-ba52-73bf61b298d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646002309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.646002309
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.38570993
Short name T484
Test name
Test status
Simulation time 263724571632 ps
CPU time 1495.01 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 01:07:13 PM PDT 23
Peak memory 218388 kb
Host smart-0bdd90f2-e395-413d-ab2d-8276fbe8a306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570993 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.38570993
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.911679253
Short name T290
Test name
Test status
Simulation time 87046479 ps
CPU time 0.96 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 206136 kb
Host smart-6c4ff83f-87ca-4007-9e0a-c3429a59809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911679253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.911679253
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2843334102
Short name T658
Test name
Test status
Simulation time 25351909 ps
CPU time 1 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:36 PM PDT 23
Peak memory 204696 kb
Host smart-f9f9f7e2-1856-438a-b5f4-3dc90552e997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843334102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2843334102
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2546175938
Short name T621
Test name
Test status
Simulation time 39488118 ps
CPU time 0.84 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214488 kb
Host smart-b750a11e-c24f-4391-825f-693a6cda0207
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546175938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2546175938
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3609172332
Short name T27
Test name
Test status
Simulation time 91341594 ps
CPU time 1.05 seconds
Started Oct 01 12:42:06 PM PDT 23
Finished Oct 01 12:42:07 PM PDT 23
Peak memory 214676 kb
Host smart-13726e8c-add3-43e4-89c3-196969b095d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609172332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3609172332
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1493127390
Short name T40
Test name
Test status
Simulation time 41355373 ps
CPU time 0.93 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 221524 kb
Host smart-4c0cb420-a39b-4340-ae16-5bd75e1852b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493127390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1493127390
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.4276759069
Short name T726
Test name
Test status
Simulation time 33044672 ps
CPU time 0.99 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 205084 kb
Host smart-0b8a3970-aa4e-49fa-bac8-60334cac64c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276759069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4276759069
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1928665199
Short name T110
Test name
Test status
Simulation time 23346560 ps
CPU time 0.87 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 214800 kb
Host smart-99db9690-a9e2-4422-a1fe-e3339a7010c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928665199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1928665199
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1168023564
Short name T534
Test name
Test status
Simulation time 13558635 ps
CPU time 0.92 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 204860 kb
Host smart-52cfa562-ec8b-4f6d-b54f-964196f86759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168023564 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1168023564
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2127796908
Short name T596
Test name
Test status
Simulation time 96162480 ps
CPU time 1.36 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 206052 kb
Host smart-d9ee4688-d8d8-4529-afee-6f014083dd7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127796908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2127796908
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1844794121
Short name T723
Test name
Test status
Simulation time 20999375769 ps
CPU time 245.13 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:46:37 PM PDT 23
Peak memory 214616 kb
Host smart-a6387bd5-b851-45bb-8758-d5ebbfdd05a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844794121 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1844794121
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1115819427
Short name T10
Test name
Test status
Simulation time 39339574 ps
CPU time 0.93 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 205060 kb
Host smart-6bcb5e24-caed-49ce-b0d4-3453a3334f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115819427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1115819427
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1906774546
Short name T560
Test name
Test status
Simulation time 15907133 ps
CPU time 0.94 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 205204 kb
Host smart-b2be28d8-18c2-46c5-b5b3-f957027b39ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906774546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1906774546
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1800255628
Short name T159
Test name
Test status
Simulation time 12048123 ps
CPU time 0.87 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 214476 kb
Host smart-2d9b5c56-2cb3-4548-acfc-609be46f80ee
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800255628 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1800255628
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2687765583
Short name T173
Test name
Test status
Simulation time 22403474 ps
CPU time 0.98 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 221588 kb
Host smart-60508fe8-7447-47ff-a68a-15468909d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687765583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2687765583
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3312541118
Short name T37
Test name
Test status
Simulation time 32648037 ps
CPU time 0.94 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 204952 kb
Host smart-d027ca15-9337-49f8-b422-201b319cb3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312541118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3312541118
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1601750133
Short name T546
Test name
Test status
Simulation time 24291082 ps
CPU time 0.96 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 221520 kb
Host smart-c20cfaf3-6d96-434f-ae1b-8654a8de1078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601750133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1601750133
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3275939102
Short name T97
Test name
Test status
Simulation time 16528266 ps
CPU time 0.88 seconds
Started Oct 01 12:42:30 PM PDT 23
Finished Oct 01 12:42:31 PM PDT 23
Peak memory 204888 kb
Host smart-5ab71fea-b31f-493b-83a4-246c4913c97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275939102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3275939102
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3220015313
Short name T179
Test name
Test status
Simulation time 64855380225 ps
CPU time 1403.22 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 01:05:47 PM PDT 23
Peak memory 216644 kb
Host smart-2f0f5147-43f4-4383-be30-e568189d4349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220015313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3220015313
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2923708688
Short name T244
Test name
Test status
Simulation time 18248507 ps
CPU time 0.97 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 205136 kb
Host smart-44981614-11a5-47a4-8313-ff765debada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923708688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2923708688
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2379094600
Short name T532
Test name
Test status
Simulation time 16190332 ps
CPU time 0.88 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 205276 kb
Host smart-f0c739b3-449e-4c87-a19f-42194e83f7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379094600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2379094600
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1771671188
Short name T595
Test name
Test status
Simulation time 28947433 ps
CPU time 0.78 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 214468 kb
Host smart-4493c5a0-d40b-484a-9c03-8abdb31be37c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771671188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1771671188
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.770623221
Short name T156
Test name
Test status
Simulation time 27146753 ps
CPU time 0.93 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214656 kb
Host smart-eb42763a-54f6-46f0-bddd-1d5107538a65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770623221 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.770623221
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.568367927
Short name T537
Test name
Test status
Simulation time 66084487 ps
CPU time 0.92 seconds
Started Oct 01 12:42:13 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 214520 kb
Host smart-dc82c14e-a5f8-41e6-912d-2cbcfd846e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568367927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.568367927
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.659694373
Short name T577
Test name
Test status
Simulation time 18927390 ps
CPU time 1.08 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 214468 kb
Host smart-0107a900-22b5-4f71-a649-5390683c7e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659694373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.659694373
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.487765061
Short name T460
Test name
Test status
Simulation time 19173765 ps
CPU time 1.1 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:42 PM PDT 23
Peak memory 222212 kb
Host smart-9fbc6e13-1a08-4d39-a038-a157afc21e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487765061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.487765061
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3573972874
Short name T713
Test name
Test status
Simulation time 23424573 ps
CPU time 0.86 seconds
Started Oct 01 12:42:09 PM PDT 23
Finished Oct 01 12:42:10 PM PDT 23
Peak memory 204896 kb
Host smart-55cc6818-88d0-49cd-aad1-ffcbeea4a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573972874 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3573972874
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1936136977
Short name T324
Test name
Test status
Simulation time 256183397 ps
CPU time 3.24 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:14 PM PDT 23
Peak memory 206104 kb
Host smart-88fae37a-5b52-4eab-985b-d335a9bf5a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936136977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1936136977
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3821536039
Short name T180
Test name
Test status
Simulation time 144448014115 ps
CPU time 1165.02 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 01:01:47 PM PDT 23
Peak memory 217644 kb
Host smart-eb6b0568-bcea-4e66-bd52-ba5e51527019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821536039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3821536039
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1559071
Short name T485
Test name
Test status
Simulation time 58338283 ps
CPU time 0.92 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 206128 kb
Host smart-0610b01f-bc7d-4ce4-9085-59d85ad8a64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1559071
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.143897909
Short name T514
Test name
Test status
Simulation time 19203234 ps
CPU time 0.79 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 204376 kb
Host smart-f5e5d19b-1ba7-4251-829d-2a1bf28a88f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143897909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.143897909
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3248054361
Short name T601
Test name
Test status
Simulation time 17359309 ps
CPU time 0.84 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214532 kb
Host smart-7a172e6c-8a58-402a-826f-6f7df52d9f71
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248054361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3248054361
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2626075335
Short name T136
Test name
Test status
Simulation time 34275968 ps
CPU time 1.01 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:16 PM PDT 23
Peak memory 214688 kb
Host smart-97c79c4a-08dd-455f-97eb-5b8dceef5a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626075335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2626075335
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2941342429
Short name T142
Test name
Test status
Simulation time 49861583 ps
CPU time 1.06 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 228896 kb
Host smart-2c4d9706-c229-41d8-b781-018043b53b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941342429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2941342429
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2144690693
Short name T594
Test name
Test status
Simulation time 37787547 ps
CPU time 0.8 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 204828 kb
Host smart-3d3935e4-0bc3-414f-b9c8-c5c6915fce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144690693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2144690693
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1324656121
Short name T109
Test name
Test status
Simulation time 24800157 ps
CPU time 0.91 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214808 kb
Host smart-a31ffa9c-b41d-4b0d-bc47-d91fcc269ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324656121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1324656121
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.848654419
Short name T593
Test name
Test status
Simulation time 14708793 ps
CPU time 0.9 seconds
Started Oct 01 12:42:46 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 204880 kb
Host smart-a130dbb0-d5c5-4a57-b381-cb94738b7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848654419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.848654419
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1677473048
Short name T579
Test name
Test status
Simulation time 81561461 ps
CPU time 2 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 205656 kb
Host smart-f810d11d-00e9-4c05-bfcf-a6a6376f734e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677473048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1677473048
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3324269675
Short name T114
Test name
Test status
Simulation time 603346675939 ps
CPU time 1210.79 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 01:02:42 PM PDT 23
Peak memory 217224 kb
Host smart-2c422ebf-6d51-4fb6-9fc8-8e0ae80cd41c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324269675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3324269675
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3165795431
Short name T72
Test name
Test status
Simulation time 29165765 ps
CPU time 0.95 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 206068 kb
Host smart-76760116-b5ac-4d42-b7e2-646791904aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165795431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3165795431
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3059824798
Short name T479
Test name
Test status
Simulation time 29744954 ps
CPU time 0.83 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 205328 kb
Host smart-55edc744-9fae-427d-ba54-5ece2bd824cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059824798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3059824798
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.694619889
Short name T698
Test name
Test status
Simulation time 13329681 ps
CPU time 0.89 seconds
Started Oct 01 12:42:08 PM PDT 23
Finished Oct 01 12:42:09 PM PDT 23
Peak memory 214640 kb
Host smart-7e885d98-cb3a-408b-8a0a-23eafb643e29
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694619889 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.694619889
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.655689522
Short name T241
Test name
Test status
Simulation time 89357104 ps
CPU time 1.08 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 214612 kb
Host smart-78488bf2-27f9-4e27-b8b9-9eb9cf876509
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655689522 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.655689522
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3634873640
Short name T589
Test name
Test status
Simulation time 64024311 ps
CPU time 0.9 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 214448 kb
Host smart-866db66a-d72c-4c50-8b58-1d9899a3302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634873640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3634873640
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_intr.3218207051
Short name T696
Test name
Test status
Simulation time 23768455 ps
CPU time 0.83 seconds
Started Oct 01 12:42:36 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 214704 kb
Host smart-ba0fa45d-7e0d-423b-a58f-33e2da9d744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218207051 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3218207051
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.257801292
Short name T703
Test name
Test status
Simulation time 19025341 ps
CPU time 0.92 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 204772 kb
Host smart-5743845d-373c-4f42-b73b-773182863d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257801292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.257801292
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1189900023
Short name T515
Test name
Test status
Simulation time 192854758 ps
CPU time 3.53 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 206208 kb
Host smart-a3f1e4b9-8abd-4244-8197-f35ea2c6bb4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189900023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1189900023
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1094849970
Short name T461
Test name
Test status
Simulation time 235313164293 ps
CPU time 1555.87 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 01:08:24 PM PDT 23
Peak memory 221060 kb
Host smart-9fd6e139-cea7-4fc0-acd5-cc71139c53b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094849970 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1094849970
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2745188179
Short name T294
Test name
Test status
Simulation time 17873851 ps
CPU time 0.94 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:26 PM PDT 23
Peak memory 205268 kb
Host smart-ecf927a4-d234-4117-aff8-92383a22b8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745188179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2745188179
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1047539399
Short name T473
Test name
Test status
Simulation time 15330081 ps
CPU time 0.88 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 205472 kb
Host smart-3a7f7608-0409-4656-b1c5-ad1c5f2defa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047539399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1047539399
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.468180627
Short name T228
Test name
Test status
Simulation time 71211080 ps
CPU time 0.8 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 214480 kb
Host smart-5a9b6f3c-c34a-4acb-a110-1cca71f86374
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468180627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.468180627
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4042833985
Short name T81
Test name
Test status
Simulation time 42039626 ps
CPU time 1.03 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 214548 kb
Host smart-536fb12b-dd2e-42ee-a4f3-4f92dbe813dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042833985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4042833985
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1992658022
Short name T42
Test name
Test status
Simulation time 26839983 ps
CPU time 0.95 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 221592 kb
Host smart-ec29e864-be29-4b12-bc7c-56daac693dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992658022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1992658022
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_intr.1091849943
Short name T488
Test name
Test status
Simulation time 40149087 ps
CPU time 0.8 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 214492 kb
Host smart-371d1400-8c8b-47a0-a12c-b6aa927dfa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091849943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1091849943
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.852202505
Short name T51
Test name
Test status
Simulation time 15035729 ps
CPU time 0.86 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 205020 kb
Host smart-8e37ce6a-e4af-4a67-b134-68e90ca4e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852202505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.852202505
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2572727168
Short name T524
Test name
Test status
Simulation time 117148212 ps
CPU time 0.9 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 204172 kb
Host smart-496c9309-b237-403a-8446-3d5297e29f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572727168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2572727168
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1856596351
Short name T181
Test name
Test status
Simulation time 114336610653 ps
CPU time 928.07 seconds
Started Oct 01 12:42:08 PM PDT 23
Finished Oct 01 12:57:37 PM PDT 23
Peak memory 215464 kb
Host smart-c470c9a3-e371-4a9e-a737-9b24bfa1d119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856596351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1856596351
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2881172235
Short name T506
Test name
Test status
Simulation time 169285820 ps
CPU time 0.92 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 204996 kb
Host smart-3c28c5bf-ef6c-4b21-84e3-49566abd801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881172235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2881172235
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3006383868
Short name T497
Test name
Test status
Simulation time 51401106 ps
CPU time 0.84 seconds
Started Oct 01 12:42:11 PM PDT 23
Finished Oct 01 12:42:12 PM PDT 23
Peak memory 204700 kb
Host smart-d7c4af60-d037-45c6-9751-5d2d0cecf399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006383868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3006383868
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1839620305
Short name T552
Test name
Test status
Simulation time 40051519 ps
CPU time 0.8 seconds
Started Oct 01 12:42:07 PM PDT 23
Finished Oct 01 12:42:08 PM PDT 23
Peak memory 214408 kb
Host smart-f3e247cf-7bbc-4b25-9615-c8a22d4db991
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839620305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1839620305
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.1297583585
Short name T146
Test name
Test status
Simulation time 42553701 ps
CPU time 0.94 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:42:43 PM PDT 23
Peak memory 215768 kb
Host smart-4e21883f-182b-4210-a032-141870216620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297583585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1297583585
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.447181899
Short name T670
Test name
Test status
Simulation time 68658170 ps
CPU time 1.6 seconds
Started Oct 01 12:42:15 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 205212 kb
Host smart-62c8c486-e8a4-4650-abff-58b430dc8628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447181899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.447181899
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.681528363
Short name T576
Test name
Test status
Simulation time 111223135 ps
CPU time 0.86 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 205016 kb
Host smart-edfe3812-96e9-4391-9687-7c7f3c19fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681528363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.681528363
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3918187642
Short name T17
Test name
Test status
Simulation time 447036562 ps
CPU time 3.05 seconds
Started Oct 01 12:42:39 PM PDT 23
Finished Oct 01 12:42:42 PM PDT 23
Peak memory 206036 kb
Host smart-591bce25-14ef-484e-a1b2-be048677fdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918187642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3918187642
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1393125409
Short name T725
Test name
Test status
Simulation time 146358015133 ps
CPU time 795.42 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:55:42 PM PDT 23
Peak memory 214964 kb
Host smart-3863f100-28e9-40e9-b3a6-b181e7d1d8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393125409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1393125409
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2452324634
Short name T542
Test name
Test status
Simulation time 67202021 ps
CPU time 0.99 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 205136 kb
Host smart-eb6ecb77-a288-4294-ae75-19af6835bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452324634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2452324634
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.640492588
Short name T318
Test name
Test status
Simulation time 45142655 ps
CPU time 0.81 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 12:41:25 PM PDT 23
Peak memory 204464 kb
Host smart-3d805be0-77b4-4163-9e7e-a196b19b4583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640492588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.640492588
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3558618447
Short name T169
Test name
Test status
Simulation time 86749198 ps
CPU time 0.86 seconds
Started Oct 01 12:41:14 PM PDT 23
Finished Oct 01 12:41:15 PM PDT 23
Peak memory 214432 kb
Host smart-9da24c4c-f158-4df1-b8f9-4dccfaebd107
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558618447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3558618447
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.532257847
Short name T551
Test name
Test status
Simulation time 26669001 ps
CPU time 0.98 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 12:41:26 PM PDT 23
Peak memory 214644 kb
Host smart-b2c5262a-b4d2-48b0-97ae-c2d367436b64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532257847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.532257847
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1517371057
Short name T174
Test name
Test status
Simulation time 47366368 ps
CPU time 0.78 seconds
Started Oct 01 12:41:27 PM PDT 23
Finished Oct 01 12:41:28 PM PDT 23
Peak memory 215436 kb
Host smart-54b81288-bac5-4504-bd97-779ec6b61921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517371057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1517371057
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.973515766
Short name T570
Test name
Test status
Simulation time 119782689 ps
CPU time 0.9 seconds
Started Oct 01 12:41:14 PM PDT 23
Finished Oct 01 12:41:15 PM PDT 23
Peak memory 205068 kb
Host smart-f555fa83-fb9d-4a48-bf45-7d9c4cc02f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973515766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.973515766
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3607087442
Short name T297
Test name
Test status
Simulation time 18451425 ps
CPU time 1.04 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:41:35 PM PDT 23
Peak memory 221652 kb
Host smart-b83e0a4c-e536-48e9-82ec-c6d3bf6cde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607087442 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3607087442
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.560145171
Short name T45
Test name
Test status
Simulation time 1287701377 ps
CPU time 6 seconds
Started Oct 01 12:41:13 PM PDT 23
Finished Oct 01 12:41:19 PM PDT 23
Peak memory 233152 kb
Host smart-f7212bdd-4653-45d1-9ac8-db8c456ab570
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560145171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.560145171
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1060014080
Short name T46
Test name
Test status
Simulation time 13332833 ps
CPU time 0.84 seconds
Started Oct 01 12:41:31 PM PDT 23
Finished Oct 01 12:41:32 PM PDT 23
Peak memory 204684 kb
Host smart-d0773a02-9d98-4a5f-871b-b0a4c2252edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060014080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1060014080
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1132786720
Short name T697
Test name
Test status
Simulation time 150184366 ps
CPU time 2.74 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:29 PM PDT 23
Peak memory 205668 kb
Host smart-7005c6f2-7b03-49e2-b35e-3ae8677691a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132786720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1132786720
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2458534205
Short name T321
Test name
Test status
Simulation time 48630618634 ps
CPU time 587.72 seconds
Started Oct 01 12:41:17 PM PDT 23
Finished Oct 01 12:51:05 PM PDT 23
Peak memory 216072 kb
Host smart-464fd4e9-9993-4673-b75c-a4983dd39382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458534205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2458534205
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2618857634
Short name T489
Test name
Test status
Simulation time 52080215 ps
CPU time 0.94 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 205724 kb
Host smart-e533d406-c389-4c55-8605-1575a68f08be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618857634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2618857634
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.456161988
Short name T478
Test name
Test status
Simulation time 16229998 ps
CPU time 0.91 seconds
Started Oct 01 12:42:04 PM PDT 23
Finished Oct 01 12:42:05 PM PDT 23
Peak memory 204668 kb
Host smart-91cf991e-782c-4556-b692-90d83f8a4f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456161988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.456161988
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.774298513
Short name T270
Test name
Test status
Simulation time 24673646 ps
CPU time 1.06 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 214528 kb
Host smart-c3cd79e7-75aa-4f6a-ad07-83427a2c40b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774298513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.774298513
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2985845446
Short name T304
Test name
Test status
Simulation time 34749896 ps
CPU time 0.83 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 215488 kb
Host smart-334e7bcc-c509-4bd9-bd5d-7f8e9e5ac914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985845446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2985845446
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2420477748
Short name T558
Test name
Test status
Simulation time 21773916 ps
CPU time 1.12 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 214404 kb
Host smart-ae87261c-fd77-4190-9b16-59bb629ff983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420477748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2420477748
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3177955348
Short name T326
Test name
Test status
Simulation time 20711125 ps
CPU time 0.93 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 214588 kb
Host smart-20bc4949-2f0c-409b-87db-6b1a82ea30cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177955348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3177955348
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3536391904
Short name T535
Test name
Test status
Simulation time 88124100 ps
CPU time 0.8 seconds
Started Oct 01 12:42:36 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 204748 kb
Host smart-fb9e0e22-2baf-4bc0-9eb3-9892f568cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536391904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3536391904
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2560099767
Short name T650
Test name
Test status
Simulation time 117473625 ps
CPU time 2.49 seconds
Started Oct 01 12:42:05 PM PDT 23
Finished Oct 01 12:42:08 PM PDT 23
Peak memory 205948 kb
Host smart-042ea98c-bb90-4351-a298-a99530c2451d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560099767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2560099767
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3964831679
Short name T666
Test name
Test status
Simulation time 98515734998 ps
CPU time 2159.12 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 01:18:18 PM PDT 23
Peak memory 222160 kb
Host smart-91a61f13-153c-4229-b8b9-273420b060e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964831679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3964831679
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.754415847
Short name T66
Test name
Test status
Simulation time 18380015 ps
CPU time 0.94 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 205168 kb
Host smart-fb63826d-1a91-413b-b60f-70ad7fa55cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754415847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.754415847
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2294847694
Short name T653
Test name
Test status
Simulation time 75910696 ps
CPU time 0.91 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:44 PM PDT 23
Peak memory 204668 kb
Host smart-5671a02a-6681-4e7c-8e2b-77e9729d7444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294847694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2294847694
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2348814143
Short name T128
Test name
Test status
Simulation time 13819434 ps
CPU time 0.89 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 214668 kb
Host smart-14db817f-cdfa-4cf4-ae4e-4159798c516a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348814143 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2348814143
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.949397642
Short name T137
Test name
Test status
Simulation time 26284841 ps
CPU time 1.03 seconds
Started Oct 01 12:42:44 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 214624 kb
Host smart-0aa4ec66-ebd7-454f-b4d6-0752c997bf10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949397642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.949397642
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2164739265
Short name T467
Test name
Test status
Simulation time 33137680 ps
CPU time 0.81 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 215392 kb
Host smart-a767c790-9699-4a60-b119-8b5bea5f201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164739265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2164739265
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1013946923
Short name T663
Test name
Test status
Simulation time 47678740 ps
CPU time 0.97 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 214412 kb
Host smart-07099b4d-fc6c-4d67-af47-f389d16ae7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013946923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1013946923
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1218067434
Short name T614
Test name
Test status
Simulation time 22949445 ps
CPU time 0.95 seconds
Started Oct 01 12:42:48 PM PDT 23
Finished Oct 01 12:42:49 PM PDT 23
Peak memory 214420 kb
Host smart-faf0857d-0f55-4918-a362-3e3f1ca3e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218067434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1218067434
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.599272273
Short name T463
Test name
Test status
Simulation time 22507038 ps
CPU time 0.83 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 204620 kb
Host smart-795229b8-dfc0-452a-9ae1-dc696cc8dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599272273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.599272273
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.14154922
Short name T555
Test name
Test status
Simulation time 119029398 ps
CPU time 1.62 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 205692 kb
Host smart-9ec7e700-7496-4221-bd27-d2c274d7d7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154922 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.14154922
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1796012096
Short name T554
Test name
Test status
Simulation time 29532992920 ps
CPU time 324.08 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:47:43 PM PDT 23
Peak memory 215544 kb
Host smart-1673c6ca-0dbb-43f4-a1f2-b7225c6e27a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796012096 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1796012096
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.56111501
Short name T281
Test name
Test status
Simulation time 17227788 ps
CPU time 0.97 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 12:42:34 PM PDT 23
Peak memory 206128 kb
Host smart-c0483d3f-b933-453d-b394-9b382ce774dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56111501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.56111501
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1371488716
Short name T480
Test name
Test status
Simulation time 68105695 ps
CPU time 0.78 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 205004 kb
Host smart-fc2ec373-72af-4443-929c-c7d7869273bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371488716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1371488716
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3491944751
Short name T79
Test name
Test status
Simulation time 12622740 ps
CPU time 0.93 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 214680 kb
Host smart-4b91b1cd-f27f-4bf8-b1ae-1f3267f93a41
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491944751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3491944751
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3600645824
Short name T271
Test name
Test status
Simulation time 59393733 ps
CPU time 1.01 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 214704 kb
Host smart-a2419721-83b6-4a9f-830d-28c7bfdd0329
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600645824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3600645824
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2179961436
Short name T130
Test name
Test status
Simulation time 27766682 ps
CPU time 1.11 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 228864 kb
Host smart-0e812b06-b8cf-460c-b626-097fca09f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179961436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2179961436
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1383844891
Short name T94
Test name
Test status
Simulation time 27093481 ps
CPU time 0.98 seconds
Started Oct 01 12:42:12 PM PDT 23
Finished Oct 01 12:42:13 PM PDT 23
Peak memory 205100 kb
Host smart-1a2373b6-c1be-4512-ba46-eace53476633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383844891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1383844891
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2435798256
Short name T316
Test name
Test status
Simulation time 37771961 ps
CPU time 0.87 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 214612 kb
Host smart-a7bb4e44-3922-47db-812d-699d7cf32ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435798256 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2435798256
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2811496369
Short name T550
Test name
Test status
Simulation time 14802563 ps
CPU time 0.89 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 204724 kb
Host smart-51c015a9-6c65-4341-b328-fb283cebcc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811496369 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2811496369
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1766527133
Short name T525
Test name
Test status
Simulation time 76535500 ps
CPU time 1.68 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 205356 kb
Host smart-d9032dab-5003-4eaf-a4cb-2ceee2e5abf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766527133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1766527133
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2480338686
Short name T486
Test name
Test status
Simulation time 60295688070 ps
CPU time 646.05 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:53:31 PM PDT 23
Peak memory 215280 kb
Host smart-2b39d1c3-9d60-4cf6-b9bb-40d4d3f6540f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480338686 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2480338686
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2415932440
Short name T483
Test name
Test status
Simulation time 28671274 ps
CPU time 0.9 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 206108 kb
Host smart-6fd61bfc-ee19-48ad-ad25-051b4aa8aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415932440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2415932440
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2523756627
Short name T454
Test name
Test status
Simulation time 41189729 ps
CPU time 0.78 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 205052 kb
Host smart-9bcde723-bc8a-4845-b8af-8357ad322547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523756627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2523756627
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.175849362
Short name T590
Test name
Test status
Simulation time 31126288 ps
CPU time 0.83 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:46 PM PDT 23
Peak memory 214300 kb
Host smart-9bdc4e1f-8c38-4519-86a2-a4daadb1ea96
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175849362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.175849362
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.156534873
Short name T580
Test name
Test status
Simulation time 49774739 ps
CPU time 1.02 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214652 kb
Host smart-f4ac57f7-078d-4911-887c-2b6fb0667ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156534873 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.156534873
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3894343991
Short name T50
Test name
Test status
Simulation time 91552583 ps
CPU time 1.02 seconds
Started Oct 01 12:42:34 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 216944 kb
Host smart-c92cb7f7-a55c-4812-923b-0225a5f8c655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894343991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3894343991
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.857278658
Short name T55
Test name
Test status
Simulation time 24701638 ps
CPU time 1.09 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 205228 kb
Host smart-2052fee6-159b-4ea3-876d-821cbb9d7df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857278658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.857278658
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3438888434
Short name T647
Test name
Test status
Simulation time 41866964 ps
CPU time 0.91 seconds
Started Oct 01 12:42:16 PM PDT 23
Finished Oct 01 12:42:17 PM PDT 23
Peak memory 221440 kb
Host smart-52312f90-a422-4724-a1f1-b6ac747144cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438888434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3438888434
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2413430841
Short name T602
Test name
Test status
Simulation time 27152066 ps
CPU time 0.87 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 205032 kb
Host smart-578763dd-3a3b-43d4-8979-418b55b46ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413430841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2413430841
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.263084193
Short name T690
Test name
Test status
Simulation time 767819922 ps
CPU time 3.77 seconds
Started Oct 01 12:42:41 PM PDT 23
Finished Oct 01 12:42:45 PM PDT 23
Peak memory 206092 kb
Host smart-79c0cb38-24f9-4a3e-89e2-c27ca7989ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263084193 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.263084193
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2926253473
Short name T626
Test name
Test status
Simulation time 33762757503 ps
CPU time 806.64 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:56:09 PM PDT 23
Peak memory 215100 kb
Host smart-ebf545a2-a9c6-4a42-923a-1455a78c5cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926253473 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2926253473
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1437853511
Short name T475
Test name
Test status
Simulation time 20196543 ps
CPU time 1.01 seconds
Started Oct 01 12:42:35 PM PDT 23
Finished Oct 01 12:42:36 PM PDT 23
Peak memory 206044 kb
Host smart-e683166f-535a-414c-9b73-0f5d4f00b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437853511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1437853511
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.12881245
Short name T649
Test name
Test status
Simulation time 101598405 ps
CPU time 0.86 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:42:43 PM PDT 23
Peak memory 205100 kb
Host smart-7b64b14c-086f-4fb2-8a55-127dafcf59f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12881245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.12881245
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.590888481
Short name T120
Test name
Test status
Simulation time 12715014 ps
CPU time 0.86 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214648 kb
Host smart-f2beaa1a-3edb-4e70-9aef-638425dfff0a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590888481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.590888481
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1853525350
Short name T54
Test name
Test status
Simulation time 77542498 ps
CPU time 0.92 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 206528 kb
Host smart-246a7b3a-0193-4f36-a8ba-23ffe1595132
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853525350 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1853525350
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1663788121
Short name T613
Test name
Test status
Simulation time 31986773 ps
CPU time 0.91 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:42:27 PM PDT 23
Peak memory 215408 kb
Host smart-820a45a3-0ede-4f79-8078-6c157fda9d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663788121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1663788121
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3203065318
Short name T638
Test name
Test status
Simulation time 53464702 ps
CPU time 0.9 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 205112 kb
Host smart-90de36f1-b838-418e-b0ae-2c93581a0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203065318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3203065318
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1937946779
Short name T102
Test name
Test status
Simulation time 17418053 ps
CPU time 0.99 seconds
Started Oct 01 12:42:29 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 214656 kb
Host smart-9b5f1f86-a800-495b-9c01-5d69a6ba1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937946779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1937946779
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.707636494
Short name T493
Test name
Test status
Simulation time 15021575 ps
CPU time 0.87 seconds
Started Oct 01 12:42:34 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 204588 kb
Host smart-6f617b69-2b52-4c64-985d-1d3e02d7e432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707636494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.707636494
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3579010567
Short name T312
Test name
Test status
Simulation time 117797900 ps
CPU time 1.65 seconds
Started Oct 01 12:42:30 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 206204 kb
Host smart-127deaf6-1abd-4a91-bbd1-0e8a8065f03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579010567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3579010567
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2304293598
Short name T637
Test name
Test status
Simulation time 623238766126 ps
CPU time 1470.91 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 01:06:50 PM PDT 23
Peak memory 218956 kb
Host smart-fbb6b687-c1b9-4252-b98f-49d5f583aa84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304293598 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2304293598
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.49693291
Short name T278
Test name
Test status
Simulation time 36939994 ps
CPU time 0.95 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:29 PM PDT 23
Peak memory 205264 kb
Host smart-f258eff1-ba13-44f5-9d59-0874a9e1c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49693291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.49693291
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2169768309
Short name T683
Test name
Test status
Simulation time 56743798 ps
CPU time 0.83 seconds
Started Oct 01 12:42:41 PM PDT 23
Finished Oct 01 12:42:42 PM PDT 23
Peak memory 205356 kb
Host smart-8f72dfaf-6f52-4847-8f77-6704a3db15e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169768309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2169768309
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2550162897
Short name T528
Test name
Test status
Simulation time 20644825 ps
CPU time 0.81 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 214420 kb
Host smart-112c886a-4691-404f-9b59-ee3784834fa7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550162897 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2550162897
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.913266326
Short name T148
Test name
Test status
Simulation time 280709932 ps
CPU time 0.97 seconds
Started Oct 01 12:42:27 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 214704 kb
Host smart-fb4eadec-4e9e-4735-ac13-df83dd0ee96c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913266326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.913266326
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.165295930
Short name T149
Test name
Test status
Simulation time 23421222 ps
CPU time 1.15 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:42:44 PM PDT 23
Peak memory 214460 kb
Host smart-69d11021-aacf-4fd3-b432-a8f679673857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165295930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.165295930
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4182239510
Short name T260
Test name
Test status
Simulation time 57725981 ps
CPU time 1.06 seconds
Started Oct 01 12:42:29 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 205312 kb
Host smart-0a71ef25-d4ed-423b-a0e2-ce9ec82a85e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182239510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4182239510
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.922770413
Short name T74
Test name
Test status
Simulation time 20402173 ps
CPU time 0.94 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214644 kb
Host smart-0f3375e3-bf7c-49df-95d9-ff56d344ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922770413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.922770413
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1702977658
Short name T495
Test name
Test status
Simulation time 17094679 ps
CPU time 0.89 seconds
Started Oct 01 12:42:34 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 204684 kb
Host smart-f3131f8a-ab0b-4737-a8c1-81b4a470797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702977658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1702977658
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3850076261
Short name T197
Test name
Test status
Simulation time 252096993 ps
CPU time 1.82 seconds
Started Oct 01 12:42:25 PM PDT 23
Finished Oct 01 12:42:27 PM PDT 23
Peak memory 205652 kb
Host smart-7386fb06-23ea-4e92-8bf1-0903b57ef900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850076261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3850076261
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3340399341
Short name T116
Test name
Test status
Simulation time 54100214828 ps
CPU time 687.16 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:54:06 PM PDT 23
Peak memory 215604 kb
Host smart-80fd9af9-da9e-48f2-b981-fd855030562e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340399341 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3340399341
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1353398264
Short name T288
Test name
Test status
Simulation time 18580612 ps
CPU time 0.94 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 206092 kb
Host smart-981114fb-7134-447f-b822-f1018e16111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353398264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1353398264
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2603981442
Short name T301
Test name
Test status
Simulation time 16771068 ps
CPU time 0.95 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:42:43 PM PDT 23
Peak memory 205260 kb
Host smart-245f7bf2-ba17-49db-a210-9c00fa576a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603981442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2603981442
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2774316844
Short name T99
Test name
Test status
Simulation time 21101566 ps
CPU time 0.84 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214504 kb
Host smart-1b3d0ca3-a0e2-44fe-9e2f-79aae160ba19
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774316844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2774316844
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.3494335602
Short name T171
Test name
Test status
Simulation time 23531443 ps
CPU time 0.89 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 215456 kb
Host smart-539f3806-63fd-46e4-9478-9edc994fe0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494335602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3494335602
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2476320940
Short name T77
Test name
Test status
Simulation time 64932648 ps
CPU time 0.99 seconds
Started Oct 01 12:42:47 PM PDT 23
Finished Oct 01 12:42:48 PM PDT 23
Peak memory 205508 kb
Host smart-bf0e80f3-14d5-4dac-8231-a946fa5cf186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476320940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2476320940
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2755248790
Short name T583
Test name
Test status
Simulation time 29942082 ps
CPU time 0.84 seconds
Started Oct 01 12:42:39 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 214300 kb
Host smart-a0f231ec-8627-44ef-a732-b95596da0cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755248790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2755248790
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1987550577
Short name T296
Test name
Test status
Simulation time 15598003 ps
CPU time 0.89 seconds
Started Oct 01 12:42:45 PM PDT 23
Finished Oct 01 12:42:46 PM PDT 23
Peak memory 204680 kb
Host smart-3dc8f906-5f12-403f-a42a-6b9ea6b9dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987550577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1987550577
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.594807962
Short name T720
Test name
Test status
Simulation time 22631465 ps
CPU time 1.01 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 204992 kb
Host smart-32e6688f-3b66-48b6-834a-052cf549c277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594807962 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.594807962
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.856650743
Short name T451
Test name
Test status
Simulation time 11374284815 ps
CPU time 259.68 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:47:00 PM PDT 23
Peak memory 215736 kb
Host smart-143d240b-3d6c-4b73-878b-544e310f2c5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856650743 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.856650743
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2336297114
Short name T648
Test name
Test status
Simulation time 17054647 ps
CPU time 0.95 seconds
Started Oct 01 12:42:43 PM PDT 23
Finished Oct 01 12:42:44 PM PDT 23
Peak memory 204972 kb
Host smart-d3a430de-f82f-43f8-bb0b-d88680f296d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336297114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2336297114
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.576550990
Short name T504
Test name
Test status
Simulation time 14850562 ps
CPU time 0.88 seconds
Started Oct 01 12:42:14 PM PDT 23
Finished Oct 01 12:42:15 PM PDT 23
Peak memory 205240 kb
Host smart-ccf7e6e7-8a6a-41f6-a465-fde2eeea87fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576550990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.576550990
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.246599165
Short name T617
Test name
Test status
Simulation time 16234680 ps
CPU time 0.79 seconds
Started Oct 01 12:42:36 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 214428 kb
Host smart-f813ed02-6ab4-4319-bced-e913088a9370
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246599165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.246599165
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2818064330
Short name T587
Test name
Test status
Simulation time 403546916 ps
CPU time 1.01 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:51 PM PDT 23
Peak memory 214672 kb
Host smart-819b06d6-6f4b-44ec-b393-a8f111c56018
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818064330 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2818064330
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2853250291
Short name T115
Test name
Test status
Simulation time 18216262 ps
CPU time 0.98 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 215556 kb
Host smart-4e2c402b-d033-46ba-8056-4967ea2a9117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853250291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2853250291
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_intr.3624835838
Short name T103
Test name
Test status
Simulation time 30495411 ps
CPU time 0.82 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 214780 kb
Host smart-477995a4-26f8-4bd5-973b-aef4cfb982b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624835838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3624835838
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2113140217
Short name T634
Test name
Test status
Simulation time 35400669 ps
CPU time 0.88 seconds
Started Oct 01 12:43:00 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 204776 kb
Host smart-8359fcc1-b8e5-4463-b3e8-93fc9c697ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113140217 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2113140217
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1385762020
Short name T659
Test name
Test status
Simulation time 89530309 ps
CPU time 2.05 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:52 PM PDT 23
Peak memory 205700 kb
Host smart-ca152c4c-217e-4ce1-8c30-0d2ba7d578f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385762020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1385762020
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3834537240
Short name T699
Test name
Test status
Simulation time 217361300535 ps
CPU time 721.62 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:54:28 PM PDT 23
Peak memory 216032 kb
Host smart-b355a2d8-8ed5-42bd-92b8-60336a5e2d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834537240 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3834537240
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.4033417510
Short name T651
Test name
Test status
Simulation time 14040341 ps
CPU time 0.83 seconds
Started Oct 01 12:42:24 PM PDT 23
Finished Oct 01 12:42:25 PM PDT 23
Peak memory 205172 kb
Host smart-2edb8fbd-652c-4ded-8d34-113b999f66e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033417510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4033417510
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2870164874
Short name T166
Test name
Test status
Simulation time 22580147 ps
CPU time 0.82 seconds
Started Oct 01 12:42:40 PM PDT 23
Finished Oct 01 12:42:41 PM PDT 23
Peak memory 214308 kb
Host smart-14890977-5b91-4cb5-afab-5ca035004502
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870164874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2870164874
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1522257729
Short name T229
Test name
Test status
Simulation time 60207346 ps
CPU time 0.97 seconds
Started Oct 01 12:42:46 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 214744 kb
Host smart-82357f7a-aeba-45f3-b950-7e3250027ba5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522257729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1522257729
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1559909738
Short name T272
Test name
Test status
Simulation time 86682276 ps
CPU time 1.13 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:23 PM PDT 23
Peak memory 214524 kb
Host smart-b25dd1fa-78c9-408f-ad46-79274d3b78e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559909738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1559909738
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3873431321
Short name T276
Test name
Test status
Simulation time 23330680 ps
CPU time 0.91 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:32 PM PDT 23
Peak memory 205012 kb
Host smart-ed20bee6-503f-4163-9bd8-2fa44a2093b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873431321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3873431321
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.765551895
Short name T29
Test name
Test status
Simulation time 26340189 ps
CPU time 0.91 seconds
Started Oct 01 12:42:34 PM PDT 23
Finished Oct 01 12:42:35 PM PDT 23
Peak memory 214480 kb
Host smart-5803fffd-35b9-4c95-b648-74a65558eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765551895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.765551895
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3121420447
Short name T597
Test name
Test status
Simulation time 20890662 ps
CPU time 0.81 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 204904 kb
Host smart-f77b4bc8-a7be-46f3-b278-4fc997bfc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121420447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3121420447
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.818051593
Short name T705
Test name
Test status
Simulation time 198135135 ps
CPU time 4.15 seconds
Started Oct 01 12:42:36 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 206012 kb
Host smart-9f3dfeb0-a142-4141-be6a-dfb420f9c6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818051593 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.818051593
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1345973226
Short name T685
Test name
Test status
Simulation time 34362748020 ps
CPU time 412.28 seconds
Started Oct 01 12:42:41 PM PDT 23
Finished Oct 01 12:49:33 PM PDT 23
Peak memory 214904 kb
Host smart-5500b245-b292-461c-bbe3-8ef13cdd2133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345973226 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1345973226
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1081311644
Short name T689
Test name
Test status
Simulation time 100915671 ps
CPU time 0.89 seconds
Started Oct 01 12:42:39 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 206144 kb
Host smart-a388f79b-3f75-4386-ab5c-760e43ff2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081311644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1081311644
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4216441066
Short name T606
Test name
Test status
Simulation time 155318695 ps
CPU time 0.93 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 205260 kb
Host smart-16ba6728-1309-406b-bae0-4f04abbff514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216441066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4216441066
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1797762688
Short name T568
Test name
Test status
Simulation time 28372530 ps
CPU time 1.06 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 214532 kb
Host smart-31e077de-87dc-4318-84ff-2e9d625aa46c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797762688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1797762688
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1604294135
Short name T313
Test name
Test status
Simulation time 32333384 ps
CPU time 0.94 seconds
Started Oct 01 12:42:46 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 221492 kb
Host smart-f069b0c3-988b-4ef8-b65b-d798e70cb04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604294135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1604294135
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.2338402589
Short name T472
Test name
Test status
Simulation time 23889845 ps
CPU time 0.96 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 214604 kb
Host smart-18132106-2a51-4d10-8129-c2278d5bf765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338402589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2338402589
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1521792286
Short name T657
Test name
Test status
Simulation time 124300179 ps
CPU time 0.82 seconds
Started Oct 01 12:42:36 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 205112 kb
Host smart-857b2693-0e0b-4cea-813c-a6785dfee439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521792286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1521792286
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3027131996
Short name T194
Test name
Test status
Simulation time 222972841 ps
CPU time 1.58 seconds
Started Oct 01 12:42:29 PM PDT 23
Finished Oct 01 12:42:31 PM PDT 23
Peak memory 205520 kb
Host smart-9233ff0b-f277-410b-8b9a-211e50495dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027131996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3027131996
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.380825534
Short name T259
Test name
Test status
Simulation time 715062238576 ps
CPU time 1814.99 seconds
Started Oct 01 12:42:33 PM PDT 23
Finished Oct 01 01:12:49 PM PDT 23
Peak memory 222256 kb
Host smart-a3a29e68-5146-4dba-a5ab-a96f801257c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380825534 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.380825534
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1915363777
Short name T242
Test name
Test status
Simulation time 24457170 ps
CPU time 0.95 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 206168 kb
Host smart-c53787dc-f68b-4ad3-9c6d-795c9032d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915363777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1915363777
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3658994408
Short name T710
Test name
Test status
Simulation time 19117011 ps
CPU time 0.78 seconds
Started Oct 01 12:41:51 PM PDT 23
Finished Oct 01 12:41:52 PM PDT 23
Peak memory 204264 kb
Host smart-27312b01-9be6-4a72-ab75-5e45c0670888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658994408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3658994408
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1643838903
Short name T121
Test name
Test status
Simulation time 22153364 ps
CPU time 0.84 seconds
Started Oct 01 12:41:08 PM PDT 23
Finished Oct 01 12:41:09 PM PDT 23
Peak memory 214400 kb
Host smart-e7257af9-fd76-4cc9-a97d-8b8c045af18b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643838903 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1643838903
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1288942222
Short name T496
Test name
Test status
Simulation time 25199101 ps
CPU time 0.89 seconds
Started Oct 01 12:41:19 PM PDT 23
Finished Oct 01 12:41:20 PM PDT 23
Peak memory 214668 kb
Host smart-afe88e2d-28c5-4739-81e9-8ee6b8ff9af8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288942222 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1288942222
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3434888899
Short name T227
Test name
Test status
Simulation time 47984404 ps
CPU time 0.94 seconds
Started Oct 01 12:41:39 PM PDT 23
Finished Oct 01 12:41:41 PM PDT 23
Peak memory 214520 kb
Host smart-5f1e6302-fd4d-46d5-b313-8a97bad2fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434888899 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3434888899
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4024449472
Short name T268
Test name
Test status
Simulation time 15300179 ps
CPU time 0.97 seconds
Started Oct 01 12:41:21 PM PDT 23
Finished Oct 01 12:41:22 PM PDT 23
Peak memory 205140 kb
Host smart-d6e93f19-f23e-4e6a-8b4a-bc5e7d5bd4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024449472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4024449472
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.142219087
Short name T462
Test name
Test status
Simulation time 22614987 ps
CPU time 1.14 seconds
Started Oct 01 12:41:28 PM PDT 23
Finished Oct 01 12:41:30 PM PDT 23
Peak memory 221772 kb
Host smart-6e7f3aa2-ea05-4230-bdb1-ae731fe2d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142219087 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.142219087
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.1080817177
Short name T609
Test name
Test status
Simulation time 17818422 ps
CPU time 0.9 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 12:41:25 PM PDT 23
Peak memory 204748 kb
Host smart-504cc3b4-ae5b-44e9-a382-8b115b376761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080817177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1080817177
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3331524
Short name T487
Test name
Test status
Simulation time 64989794 ps
CPU time 1.84 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 205688 kb
Host smart-ab0922c0-ea0e-4256-b45d-6d8d8109aa5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331524 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3331524
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2813932391
Short name T182
Test name
Test status
Simulation time 88408736226 ps
CPU time 1837.89 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 01:12:10 PM PDT 23
Peak memory 220276 kb
Host smart-55639a0d-8940-48c2-bf23-972d5b3e5df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813932391 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2813932391
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.445681609
Short name T75
Test name
Test status
Simulation time 44637045 ps
CPU time 0.79 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 215452 kb
Host smart-7f728894-57a6-4bc3-9f06-a4cdb4a234ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445681609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.445681609
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.3514628329
Short name T161
Test name
Test status
Simulation time 19256261 ps
CPU time 1.08 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 221568 kb
Host smart-21784c46-f8a9-484a-9830-712fb6dfb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514628329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3514628329
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.1466967452
Short name T319
Test name
Test status
Simulation time 43328544 ps
CPU time 1.19 seconds
Started Oct 01 12:42:39 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 222128 kb
Host smart-535dfeef-41ad-435f-b689-b7a71fdadb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466967452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1466967452
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.1542479843
Short name T565
Test name
Test status
Simulation time 38703867 ps
CPU time 0.88 seconds
Started Oct 01 12:42:35 PM PDT 23
Finished Oct 01 12:42:37 PM PDT 23
Peak memory 215572 kb
Host smart-9aedabb3-0ec5-4263-8053-35d90822d480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542479843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1542479843
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.2273353494
Short name T134
Test name
Test status
Simulation time 21662460 ps
CPU time 1 seconds
Started Oct 01 12:42:19 PM PDT 23
Finished Oct 01 12:42:20 PM PDT 23
Peak memory 214508 kb
Host smart-2f8333f1-e92c-4658-ad89-69a34215ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273353494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2273353494
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.3895008926
Short name T325
Test name
Test status
Simulation time 21755145 ps
CPU time 0.95 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:21 PM PDT 23
Peak memory 221496 kb
Host smart-0474c49e-327e-4775-9e4a-2b0c55f0c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895008926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3895008926
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.558421538
Short name T636
Test name
Test status
Simulation time 24929991 ps
CPU time 0.89 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 215640 kb
Host smart-b9bb5126-aaa6-4993-99b8-f4134daf9c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558421538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.558421538
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.3772147755
Short name T232
Test name
Test status
Simulation time 92570264 ps
CPU time 1 seconds
Started Oct 01 12:43:02 PM PDT 23
Finished Oct 01 12:43:04 PM PDT 23
Peak memory 216728 kb
Host smart-a782191e-7fbf-4841-a3e5-da2d11e80142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772147755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3772147755
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.4105043734
Short name T622
Test name
Test status
Simulation time 22419292 ps
CPU time 0.85 seconds
Started Oct 01 12:42:21 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 215564 kb
Host smart-1289311d-29e7-43a9-b91e-1eb3ab3134e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105043734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.4105043734
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.1831830078
Short name T547
Test name
Test status
Simulation time 17354995 ps
CPU time 0.96 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 205336 kb
Host smart-b334c2da-8448-4b27-9162-95ab639aa21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831830078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1831830078
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.4112769290
Short name T521
Test name
Test status
Simulation time 109431924 ps
CPU time 0.83 seconds
Started Oct 01 12:41:37 PM PDT 23
Finished Oct 01 12:41:38 PM PDT 23
Peak memory 205252 kb
Host smart-22572b57-3eee-45e3-afb5-a897c75cae64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112769290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4112769290
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3028025534
Short name T672
Test name
Test status
Simulation time 17982020 ps
CPU time 0.81 seconds
Started Oct 01 12:41:49 PM PDT 23
Finished Oct 01 12:41:50 PM PDT 23
Peak memory 214372 kb
Host smart-6c67cc0b-aff1-49ba-995a-ce1e2bfb39f1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028025534 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3028025534
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.410850124
Short name T144
Test name
Test status
Simulation time 49520662 ps
CPU time 0.96 seconds
Started Oct 01 12:41:31 PM PDT 23
Finished Oct 01 12:41:32 PM PDT 23
Peak memory 214700 kb
Host smart-073f0718-4029-4e67-885a-6b7b8124085b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410850124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.410850124
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3643690761
Short name T618
Test name
Test status
Simulation time 32832572 ps
CPU time 0.94 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 215844 kb
Host smart-d8c8bdf9-a067-4b18-bbd1-a73717f02cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643690761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3643690761
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_intr.24125961
Short name T107
Test name
Test status
Simulation time 23798524 ps
CPU time 1.03 seconds
Started Oct 01 12:41:43 PM PDT 23
Finished Oct 01 12:41:44 PM PDT 23
Peak memory 225596 kb
Host smart-bbcadd9f-f05d-4c34-8bdd-d50bfed46cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24125961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.24125961
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.829707477
Short name T574
Test name
Test status
Simulation time 39648778 ps
CPU time 0.88 seconds
Started Oct 01 12:41:36 PM PDT 23
Finished Oct 01 12:41:38 PM PDT 23
Peak memory 204828 kb
Host smart-58d7b4b2-caa8-48bf-a6d3-8e6b7b422c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829707477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.829707477
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2030195013
Short name T640
Test name
Test status
Simulation time 135492300 ps
CPU time 1.48 seconds
Started Oct 01 12:41:33 PM PDT 23
Finished Oct 01 12:41:34 PM PDT 23
Peak memory 205424 kb
Host smart-eba2d596-df7d-4571-85cb-fc841677d604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030195013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2030195013
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2741386923
Short name T470
Test name
Test status
Simulation time 38686694805 ps
CPU time 847.92 seconds
Started Oct 01 12:41:13 PM PDT 23
Finished Oct 01 12:55:21 PM PDT 23
Peak memory 215656 kb
Host smart-f3b9e90b-fb2f-4dd7-9f19-753c17addcec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741386923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2741386923
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3863989180
Short name T135
Test name
Test status
Simulation time 34232850 ps
CPU time 0.97 seconds
Started Oct 01 12:42:20 PM PDT 23
Finished Oct 01 12:42:22 PM PDT 23
Peak memory 228608 kb
Host smart-07d6cfdf-5fd1-43e4-a7c2-e41295429ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863989180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3863989180
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.927321449
Short name T708
Test name
Test status
Simulation time 58074191 ps
CPU time 1.17 seconds
Started Oct 01 12:42:23 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214468 kb
Host smart-e5a94a00-8bb9-453a-88b9-d8d83ac6e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927321449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.927321449
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.1774044153
Short name T157
Test name
Test status
Simulation time 30553120 ps
CPU time 0.84 seconds
Started Oct 01 12:42:46 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 215436 kb
Host smart-c53a3554-716f-44ef-8fe8-a59176ed2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774044153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1774044153
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.1707453787
Short name T237
Test name
Test status
Simulation time 23606372 ps
CPU time 0.9 seconds
Started Oct 01 12:42:18 PM PDT 23
Finished Oct 01 12:42:19 PM PDT 23
Peak memory 214592 kb
Host smart-f975c628-7db4-458e-a35b-b8dedaec4f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707453787 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1707453787
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.3803186926
Short name T141
Test name
Test status
Simulation time 24113405 ps
CPU time 1.07 seconds
Started Oct 01 12:42:17 PM PDT 23
Finished Oct 01 12:42:18 PM PDT 23
Peak memory 214412 kb
Host smart-8bf6a2f5-f841-4c26-83e0-35d294a60ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803186926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3803186926
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.3110699119
Short name T494
Test name
Test status
Simulation time 17961777 ps
CPU time 1.27 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:40 PM PDT 23
Peak memory 215720 kb
Host smart-0921959b-7105-42da-984a-f307f20bcdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110699119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3110699119
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.1427372989
Short name T43
Test name
Test status
Simulation time 24719203 ps
CPU time 1.19 seconds
Started Oct 01 12:42:26 PM PDT 23
Finished Oct 01 12:42:28 PM PDT 23
Peak memory 228760 kb
Host smart-5dfcaf01-fb8a-4260-a243-47cc3c7fc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427372989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1427372989
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.27380808
Short name T692
Test name
Test status
Simulation time 18015051 ps
CPU time 1.39 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 221816 kb
Host smart-64b1b462-9b6b-405e-a58a-d789f080d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27380808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.27380808
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.3621956759
Short name T311
Test name
Test status
Simulation time 39405177 ps
CPU time 0.82 seconds
Started Oct 01 12:42:38 PM PDT 23
Finished Oct 01 12:42:39 PM PDT 23
Peak memory 215324 kb
Host smart-80d9e40d-c1bf-411a-97ed-f4825e0830b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621956759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3621956759
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.2922923401
Short name T292
Test name
Test status
Simulation time 76429933 ps
CPU time 0.92 seconds
Started Oct 01 12:41:09 PM PDT 23
Finished Oct 01 12:41:11 PM PDT 23
Peak memory 206148 kb
Host smart-53487bdb-d8ca-46ad-b374-6ffa9f69c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922923401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2922923401
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1640398893
Short name T533
Test name
Test status
Simulation time 148781563 ps
CPU time 0.84 seconds
Started Oct 01 12:41:09 PM PDT 23
Finished Oct 01 12:41:10 PM PDT 23
Peak memory 205412 kb
Host smart-505708e1-c8c4-4362-9237-fc5edd080d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640398893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1640398893
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1433593108
Short name T36
Test name
Test status
Simulation time 15450974 ps
CPU time 0.81 seconds
Started Oct 01 12:41:20 PM PDT 23
Finished Oct 01 12:41:22 PM PDT 23
Peak memory 214512 kb
Host smart-500e4ad5-8bf8-476f-8b0c-6b780f6ce237
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433593108 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1433593108
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.73302529
Short name T639
Test name
Test status
Simulation time 29917151 ps
CPU time 0.96 seconds
Started Oct 01 12:41:18 PM PDT 23
Finished Oct 01 12:41:19 PM PDT 23
Peak memory 214536 kb
Host smart-fd8bc565-255e-494d-b772-3c7c9b73dd49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73302529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.73302529
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1897143685
Short name T500
Test name
Test status
Simulation time 29717997 ps
CPU time 0.97 seconds
Started Oct 01 12:41:41 PM PDT 23
Finished Oct 01 12:41:46 PM PDT 23
Peak memory 221436 kb
Host smart-dc91949b-bf1f-4a58-9204-e912449aad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897143685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1897143685
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4060384676
Short name T87
Test name
Test status
Simulation time 73356265 ps
CPU time 1.08 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 205612 kb
Host smart-76e2d046-46ab-4b48-90ec-bc1591307f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060384676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4060384676
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.917197503
Short name T106
Test name
Test status
Simulation time 29169467 ps
CPU time 0.95 seconds
Started Oct 01 12:41:23 PM PDT 23
Finished Oct 01 12:41:24 PM PDT 23
Peak memory 225448 kb
Host smart-34c0acdb-f70b-46fd-bcd1-877fb11ff790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917197503 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.917197503
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4282921224
Short name T655
Test name
Test status
Simulation time 15546100 ps
CPU time 0.88 seconds
Started Oct 01 12:41:26 PM PDT 23
Finished Oct 01 12:41:27 PM PDT 23
Peak memory 205060 kb
Host smart-0c67bc1c-c727-47d5-9261-54fffd9eb47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282921224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4282921224
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.127103362
Short name T47
Test name
Test status
Simulation time 18635881 ps
CPU time 0.89 seconds
Started Oct 01 12:41:23 PM PDT 23
Finished Oct 01 12:41:24 PM PDT 23
Peak memory 204680 kb
Host smart-119d0594-7487-4995-aa71-30198be733de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127103362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.127103362
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3845324025
Short name T14
Test name
Test status
Simulation time 108671272 ps
CPU time 1.57 seconds
Started Oct 01 12:41:19 PM PDT 23
Finished Oct 01 12:41:21 PM PDT 23
Peak memory 206248 kb
Host smart-4ab62032-d21e-4a91-b04d-00080e50d4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845324025 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3845324025
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2035731256
Short name T471
Test name
Test status
Simulation time 257899040139 ps
CPU time 1465.43 seconds
Started Oct 01 12:41:24 PM PDT 23
Finished Oct 01 01:05:50 PM PDT 23
Peak memory 216320 kb
Host smart-733c5139-9598-496c-814e-e9fdf26f8770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035731256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2035731256
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1523798972
Short name T553
Test name
Test status
Simulation time 29242991 ps
CPU time 0.91 seconds
Started Oct 01 12:42:28 PM PDT 23
Finished Oct 01 12:42:30 PM PDT 23
Peak memory 215524 kb
Host smart-adda2a6e-7159-41b8-8777-cd0e46abe197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523798972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1523798972
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.631565804
Short name T198
Test name
Test status
Simulation time 21097251 ps
CPU time 1.16 seconds
Started Oct 01 12:42:48 PM PDT 23
Finished Oct 01 12:42:49 PM PDT 23
Peak memory 222196 kb
Host smart-d0b97f82-3806-4b65-bccd-ad64ffea4d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631565804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.631565804
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.2476886872
Short name T140
Test name
Test status
Simulation time 44184095 ps
CPU time 1.01 seconds
Started Oct 01 12:42:22 PM PDT 23
Finished Oct 01 12:42:24 PM PDT 23
Peak memory 214508 kb
Host smart-713b597f-c80d-4a5b-997c-fd2448fb94ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476886872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2476886872
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.2840395052
Short name T240
Test name
Test status
Simulation time 29307931 ps
CPU time 0.8 seconds
Started Oct 01 12:42:42 PM PDT 23
Finished Oct 01 12:42:43 PM PDT 23
Peak memory 214352 kb
Host smart-93c4cf91-25d8-4d24-8984-4383ca913f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840395052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2840395052
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.708533190
Short name T236
Test name
Test status
Simulation time 24202013 ps
CPU time 1.21 seconds
Started Oct 01 12:42:59 PM PDT 23
Finished Oct 01 12:43:06 PM PDT 23
Peak memory 228540 kb
Host smart-6ddcd9a8-dbac-4659-b104-6825b2497572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708533190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.708533190
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.2897513577
Short name T132
Test name
Test status
Simulation time 33523079 ps
CPU time 1.05 seconds
Started Oct 01 12:43:26 PM PDT 23
Finished Oct 01 12:43:27 PM PDT 23
Peak memory 220324 kb
Host smart-2f66a9d9-959e-4e9d-bb91-9a3324d6128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897513577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.2897513577
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.1846702435
Short name T35
Test name
Test status
Simulation time 43489687 ps
CPU time 1.08 seconds
Started Oct 01 12:43:20 PM PDT 23
Finished Oct 01 12:43:21 PM PDT 23
Peak memory 214560 kb
Host smart-5a69f061-71c6-477f-89ef-105bf846797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846702435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1846702435
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.1663495050
Short name T274
Test name
Test status
Simulation time 51143352 ps
CPU time 1.17 seconds
Started Oct 01 12:43:05 PM PDT 23
Finished Oct 01 12:43:08 PM PDT 23
Peak memory 214640 kb
Host smart-fc2bdc8c-0db6-4d4f-b6e8-2f9a96f33b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663495050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1663495050
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.2048721623
Short name T679
Test name
Test status
Simulation time 32510597 ps
CPU time 1.05 seconds
Started Oct 01 12:43:19 PM PDT 23
Finished Oct 01 12:43:21 PM PDT 23
Peak memory 230388 kb
Host smart-b37a52fb-681a-46ee-9eee-9e47f2529ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048721623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2048721623
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.3449268555
Short name T143
Test name
Test status
Simulation time 119279311 ps
CPU time 0.88 seconds
Started Oct 01 12:43:14 PM PDT 23
Finished Oct 01 12:43:15 PM PDT 23
Peak memory 214608 kb
Host smart-25ce9ab5-ae73-424c-b14f-537612ddc664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449268555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3449268555
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.626681254
Short name T293
Test name
Test status
Simulation time 18210402 ps
CPU time 0.93 seconds
Started Oct 01 12:41:33 PM PDT 23
Finished Oct 01 12:41:35 PM PDT 23
Peak memory 205112 kb
Host smart-cded0633-c772-4029-8b43-f64e75909638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626681254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.626681254
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3318819470
Short name T95
Test name
Test status
Simulation time 13378469 ps
CPU time 0.81 seconds
Started Oct 01 12:41:22 PM PDT 23
Finished Oct 01 12:41:23 PM PDT 23
Peak memory 204516 kb
Host smart-43c41e59-2982-41bd-a8c0-e2dceaaf067c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318819470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3318819470
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.41782506
Short name T176
Test name
Test status
Simulation time 10655312 ps
CPU time 0.83 seconds
Started Oct 01 12:41:22 PM PDT 23
Finished Oct 01 12:41:23 PM PDT 23
Peak memory 214316 kb
Host smart-330ca300-bf88-48e8-b47b-75472f25ce61
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41782506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.41782506
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3680211768
Short name T693
Test name
Test status
Simulation time 13664599 ps
CPU time 0.87 seconds
Started Oct 01 12:41:52 PM PDT 23
Finished Oct 01 12:41:53 PM PDT 23
Peak memory 214704 kb
Host smart-b7746a5e-743b-4cc3-9656-732ca4d72b17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680211768 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3680211768
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3015589126
Short name T131
Test name
Test status
Simulation time 27236349 ps
CPU time 1.01 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 228596 kb
Host smart-26afc6e8-ed5c-4e4c-aefc-ff662b224bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015589126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3015589126
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2048341381
Short name T33
Test name
Test status
Simulation time 37053011 ps
CPU time 1.1 seconds
Started Oct 01 12:41:23 PM PDT 23
Finished Oct 01 12:41:24 PM PDT 23
Peak memory 205208 kb
Host smart-c48c4064-0fd7-43d3-82d0-e2fc735664c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048341381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2048341381
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1766494154
Short name T531
Test name
Test status
Simulation time 37662136 ps
CPU time 0.79 seconds
Started Oct 01 12:41:30 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 214612 kb
Host smart-b91d6664-07c2-4391-8108-09091d748d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766494154 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1766494154
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3689415483
Short name T286
Test name
Test status
Simulation time 129270254 ps
CPU time 0.79 seconds
Started Oct 01 12:41:37 PM PDT 23
Finished Oct 01 12:41:38 PM PDT 23
Peak memory 204620 kb
Host smart-a4389e85-8ba9-4abc-9c78-1163006b99b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689415483 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3689415483
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2329396704
Short name T591
Test name
Test status
Simulation time 22098233 ps
CPU time 0.85 seconds
Started Oct 01 12:41:17 PM PDT 23
Finished Oct 01 12:41:18 PM PDT 23
Peak memory 204788 kb
Host smart-7a333266-cc91-45cb-a36e-ef3162e3c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329396704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2329396704
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1442140304
Short name T631
Test name
Test status
Simulation time 1144361720 ps
CPU time 3.58 seconds
Started Oct 01 12:41:14 PM PDT 23
Finished Oct 01 12:41:18 PM PDT 23
Peak memory 206188 kb
Host smart-b270d8cd-685a-4070-ba26-a61ff7e27e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442140304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1442140304
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4176096762
Short name T572
Test name
Test status
Simulation time 18117024919 ps
CPU time 370.02 seconds
Started Oct 01 12:41:27 PM PDT 23
Finished Oct 01 12:47:37 PM PDT 23
Peak memory 215676 kb
Host smart-1ccb4b4d-b9ad-40ca-9c0d-7f105938170a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176096762 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.4176096762
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3198064186
Short name T12
Test name
Test status
Simulation time 52040207 ps
CPU time 0.85 seconds
Started Oct 01 12:43:04 PM PDT 23
Finished Oct 01 12:43:05 PM PDT 23
Peak memory 214416 kb
Host smart-f1d240fc-91a9-473c-a702-7c0b92eed043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198064186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3198064186
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.2029425611
Short name T275
Test name
Test status
Simulation time 55263410 ps
CPU time 1.12 seconds
Started Oct 01 12:42:46 PM PDT 23
Finished Oct 01 12:42:47 PM PDT 23
Peak memory 214644 kb
Host smart-54d1ed7e-cd4f-4f41-93e7-749f67d22dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029425611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2029425611
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.786271090
Short name T509
Test name
Test status
Simulation time 18891332 ps
CPU time 1.15 seconds
Started Oct 01 12:43:17 PM PDT 23
Finished Oct 01 12:43:18 PM PDT 23
Peak memory 215424 kb
Host smart-31441bd6-994a-4854-bf67-6286fd6d01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786271090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.786271090
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.444463456
Short name T235
Test name
Test status
Simulation time 47401323 ps
CPU time 0.94 seconds
Started Oct 01 12:43:07 PM PDT 23
Finished Oct 01 12:43:11 PM PDT 23
Peak memory 214656 kb
Host smart-781db719-9cf5-4692-b81b-a6eebfdc346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444463456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.444463456
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.2243571212
Short name T584
Test name
Test status
Simulation time 44212684 ps
CPU time 1.11 seconds
Started Oct 01 12:43:21 PM PDT 23
Finished Oct 01 12:43:22 PM PDT 23
Peak memory 216792 kb
Host smart-4762edce-8db1-4d09-88b0-67fcc0ca7cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243571212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2243571212
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.2389135783
Short name T306
Test name
Test status
Simulation time 22272220 ps
CPU time 0.97 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 221492 kb
Host smart-740cb1b9-f50b-45ad-a932-fc3dae1de2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389135783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2389135783
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.3098722523
Short name T162
Test name
Test status
Simulation time 18515906 ps
CPU time 1 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 215680 kb
Host smart-ad44d6a6-50f1-4e03-94e0-a6dbf7a23250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098722523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3098722523
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.4274002930
Short name T252
Test name
Test status
Simulation time 33434842 ps
CPU time 0.93 seconds
Started Oct 01 12:42:32 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 214336 kb
Host smart-cf23418e-a46f-46a1-9ca9-fdc27e3fe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274002930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4274002930
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.3655671047
Short name T536
Test name
Test status
Simulation time 52727786 ps
CPU time 1.18 seconds
Started Oct 01 12:42:55 PM PDT 23
Finished Oct 01 12:42:57 PM PDT 23
Peak memory 214604 kb
Host smart-8334c9ab-8591-4965-ba9f-fb6b172620c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655671047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3655671047
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.3063161558
Short name T557
Test name
Test status
Simulation time 18358529 ps
CPU time 1.43 seconds
Started Oct 01 12:42:52 PM PDT 23
Finished Oct 01 12:42:53 PM PDT 23
Peak memory 222304 kb
Host smart-832d8357-9d23-484b-b83d-fb4394d73c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063161558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3063161558
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1807267569
Short name T245
Test name
Test status
Simulation time 140593318 ps
CPU time 0.97 seconds
Started Oct 01 12:41:34 PM PDT 23
Finished Oct 01 12:41:35 PM PDT 23
Peak memory 205236 kb
Host smart-7f9715e8-31a4-427b-a646-437189ed56d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807267569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1807267569
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1952894087
Short name T582
Test name
Test status
Simulation time 44033591 ps
CPU time 0.83 seconds
Started Oct 01 12:41:35 PM PDT 23
Finished Oct 01 12:41:36 PM PDT 23
Peak memory 204652 kb
Host smart-b6c83b8a-d704-4f39-9894-f68f857dc4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952894087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1952894087
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3153179487
Short name T234
Test name
Test status
Simulation time 13463031 ps
CPU time 0.86 seconds
Started Oct 01 12:41:25 PM PDT 23
Finished Oct 01 12:41:26 PM PDT 23
Peak memory 214328 kb
Host smart-901af165-b392-4969-a7d2-0123d30ba3f3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153179487 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3153179487
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1026311022
Short name T643
Test name
Test status
Simulation time 24576401 ps
CPU time 0.95 seconds
Started Oct 01 12:41:58 PM PDT 23
Finished Oct 01 12:41:59 PM PDT 23
Peak memory 214676 kb
Host smart-2bbcc1f2-375a-4471-b07b-86e81fa9699a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026311022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1026311022
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1480218
Short name T231
Test name
Test status
Simulation time 18627517 ps
CPU time 1.06 seconds
Started Oct 01 12:41:43 PM PDT 23
Finished Oct 01 12:41:44 PM PDT 23
Peak memory 221636 kb
Host smart-70a51e30-831c-48d2-8d13-3e85067c6763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480218 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1480218
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_intr.3032343969
Short name T562
Test name
Test status
Simulation time 26258293 ps
CPU time 0.9 seconds
Started Oct 01 12:41:15 PM PDT 23
Finished Oct 01 12:41:16 PM PDT 23
Peak memory 214484 kb
Host smart-1e5d1a83-87b3-46f4-bae9-08cda8760d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032343969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3032343969
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3421553975
Short name T727
Test name
Test status
Simulation time 19564063 ps
CPU time 0.87 seconds
Started Oct 01 12:41:32 PM PDT 23
Finished Oct 01 12:41:33 PM PDT 23
Peak memory 204856 kb
Host smart-e3db39cd-bc43-41ea-8b01-07ddcbdfd0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421553975 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3421553975
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.679278673
Short name T566
Test name
Test status
Simulation time 18043509 ps
CPU time 0.8 seconds
Started Oct 01 12:41:16 PM PDT 23
Finished Oct 01 12:41:17 PM PDT 23
Peak memory 204660 kb
Host smart-02c5e9af-c60f-4944-99fe-d55b448969d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679278673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.679278673
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.566033229
Short name T616
Test name
Test status
Simulation time 40004245 ps
CPU time 1.27 seconds
Started Oct 01 12:41:29 PM PDT 23
Finished Oct 01 12:41:31 PM PDT 23
Peak memory 205484 kb
Host smart-c2c6714d-c3e9-4f88-90eb-6e456db14a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566033229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.566033229
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1110433120
Short name T20
Test name
Test status
Simulation time 195106091517 ps
CPU time 1226.41 seconds
Started Oct 01 12:41:20 PM PDT 23
Finished Oct 01 01:01:46 PM PDT 23
Peak memory 218432 kb
Host smart-4f7db19e-24ca-4513-b4ac-cd750f5cce68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110433120 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1110433120
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3508755559
Short name T305
Test name
Test status
Simulation time 67003910 ps
CPU time 1.07 seconds
Started Oct 01 12:42:31 PM PDT 23
Finished Oct 01 12:42:33 PM PDT 23
Peak memory 221952 kb
Host smart-eb9270b8-ce27-40af-9b63-f726f9e54f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508755559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3508755559
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.2012295441
Short name T150
Test name
Test status
Simulation time 24800060 ps
CPU time 1.05 seconds
Started Oct 01 12:42:37 PM PDT 23
Finished Oct 01 12:42:38 PM PDT 23
Peak memory 228424 kb
Host smart-5585bdbd-68c3-4cc9-a96b-7018cee1bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012295441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2012295441
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.3722423817
Short name T147
Test name
Test status
Simulation time 35015496 ps
CPU time 1.14 seconds
Started Oct 01 12:42:35 PM PDT 23
Finished Oct 01 12:42:36 PM PDT 23
Peak memory 221996 kb
Host smart-386da0bd-9761-4381-8ee4-031d4d245638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722423817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3722423817
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.1473861160
Short name T691
Test name
Test status
Simulation time 32699607 ps
CPU time 0.94 seconds
Started Oct 01 12:43:20 PM PDT 23
Finished Oct 01 12:43:21 PM PDT 23
Peak memory 222088 kb
Host smart-d8e61683-5b8b-4414-88ca-34e9221c97f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473861160 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1473861160
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.2479814950
Short name T163
Test name
Test status
Simulation time 20135663 ps
CPU time 0.98 seconds
Started Oct 01 12:43:02 PM PDT 23
Finished Oct 01 12:43:04 PM PDT 23
Peak memory 215584 kb
Host smart-26e447a0-f01b-4c9b-a9ae-ece2fa4946a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479814950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2479814950
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.2792597554
Short name T302
Test name
Test status
Simulation time 32290970 ps
CPU time 0.92 seconds
Started Oct 01 12:43:28 PM PDT 23
Finished Oct 01 12:43:29 PM PDT 23
Peak memory 222016 kb
Host smart-300b3d8b-778b-40e4-a306-4dfd1ee790a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792597554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2792597554
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.1248860335
Short name T660
Test name
Test status
Simulation time 20166566 ps
CPU time 1.01 seconds
Started Oct 01 12:43:29 PM PDT 23
Finished Oct 01 12:43:30 PM PDT 23
Peak memory 214572 kb
Host smart-4fc62d96-b1ab-47c2-a04c-2455357ef64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248860335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1248860335
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.2552112248
Short name T633
Test name
Test status
Simulation time 19151964 ps
CPU time 1.37 seconds
Started Oct 01 12:42:50 PM PDT 23
Finished Oct 01 12:42:51 PM PDT 23
Peak memory 222236 kb
Host smart-81670f93-52ae-41fc-8573-f0e38339a939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552112248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2552112248
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.1524282300
Short name T6
Test name
Test status
Simulation time 57275094 ps
CPU time 1 seconds
Started Oct 01 12:43:13 PM PDT 23
Finished Oct 01 12:43:15 PM PDT 23
Peak memory 228688 kb
Host smart-b23996ca-6aba-46ed-a150-1e4f79e2196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524282300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1524282300
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.1524184311
Short name T39
Test name
Test status
Simulation time 41615656 ps
CPU time 1.16 seconds
Started Oct 01 12:43:00 PM PDT 23
Finished Oct 01 12:43:01 PM PDT 23
Peak memory 222016 kb
Host smart-5c0eecaa-c803-4703-9237-6379cec41b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524184311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1524184311
Directory /workspace/99.edn_err/latest
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