Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
88613 |
1 |
|
|
T2 |
18 |
|
T8 |
4 |
|
T9 |
9 |
all_pins[1] |
88613 |
1 |
|
|
T2 |
18 |
|
T8 |
4 |
|
T9 |
9 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
167469 |
1 |
|
|
T2 |
36 |
|
T8 |
8 |
|
T9 |
18 |
values[0x1] |
9757 |
1 |
|
|
T43 |
33 |
|
T44 |
3 |
|
T45 |
1 |
transitions[0x0=>0x1] |
8858 |
1 |
|
|
T43 |
30 |
|
T44 |
3 |
|
T45 |
1 |
transitions[0x1=>0x0] |
8882 |
1 |
|
|
T43 |
30 |
|
T44 |
3 |
|
T45 |
1 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
80695 |
1 |
|
|
T2 |
18 |
|
T8 |
4 |
|
T9 |
9 |
all_pins[0] |
values[0x1] |
7918 |
1 |
|
|
T43 |
24 |
|
T44 |
3 |
|
T45 |
1 |
all_pins[0] |
transitions[0x0=>0x1] |
7436 |
1 |
|
|
T43 |
22 |
|
T44 |
3 |
|
T45 |
1 |
all_pins[0] |
transitions[0x1=>0x0] |
1357 |
1 |
|
|
T43 |
7 |
|
T20 |
18 |
|
T21 |
33 |
all_pins[1] |
values[0x0] |
86774 |
1 |
|
|
T2 |
18 |
|
T8 |
4 |
|
T9 |
9 |
all_pins[1] |
values[0x1] |
1839 |
1 |
|
|
T43 |
9 |
|
T20 |
25 |
|
T21 |
46 |
all_pins[1] |
transitions[0x0=>0x1] |
1422 |
1 |
|
|
T43 |
8 |
|
T20 |
15 |
|
T21 |
36 |
all_pins[1] |
transitions[0x1=>0x0] |
7525 |
1 |
|
|
T43 |
23 |
|
T44 |
3 |
|
T45 |
1 |