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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.85 99.02 92.46 96.84 94.74 98.62 99.77 96.52


Total test records in report: 729
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T161 /workspace/coverage/default/96.edn_err.1502949799 Oct 04 01:47:55 PM PDT 23 Oct 04 01:47:57 PM PDT 23 49805666 ps
T310 /workspace/coverage/default/7.edn_alert.1278228152 Oct 04 01:50:53 PM PDT 23 Oct 04 01:50:54 PM PDT 23 22173647 ps
T150 /workspace/coverage/default/56.edn_err.3478411897 Oct 04 01:54:46 PM PDT 23 Oct 04 01:54:48 PM PDT 23 68595014 ps
T169 /workspace/coverage/default/11.edn_err.1860367189 Oct 04 01:53:11 PM PDT 23 Oct 04 01:53:13 PM PDT 23 18456358 ps
T553 /workspace/coverage/default/40.edn_alert.3071147252 Oct 04 01:46:26 PM PDT 23 Oct 04 01:46:27 PM PDT 23 20768083 ps
T554 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.356094829 Oct 04 01:43:37 PM PDT 23 Oct 04 01:51:02 PM PDT 23 17730866478 ps
T555 /workspace/coverage/default/32.edn_alert_test.2335027415 Oct 04 01:55:07 PM PDT 23 Oct 04 01:55:08 PM PDT 23 54131695 ps
T308 /workspace/coverage/default/0.edn_regwen.840392987 Oct 04 01:49:49 PM PDT 23 Oct 04 01:49:52 PM PDT 23 12592518 ps
T102 /workspace/coverage/default/18.edn_genbits.4294231844 Oct 04 01:53:24 PM PDT 23 Oct 04 01:53:26 PM PDT 23 76590056 ps
T556 /workspace/coverage/default/36.edn_intr.337484564 Oct 04 01:50:33 PM PDT 23 Oct 04 01:50:34 PM PDT 23 31160895 ps
T557 /workspace/coverage/default/14.edn_disable.461080380 Oct 04 01:45:47 PM PDT 23 Oct 04 01:45:48 PM PDT 23 51832336 ps
T558 /workspace/coverage/default/22.edn_alert.2980217079 Oct 04 01:53:15 PM PDT 23 Oct 04 01:53:17 PM PDT 23 33776358 ps
T279 /workspace/coverage/default/6.edn_genbits.747965242 Oct 04 01:53:00 PM PDT 23 Oct 04 01:53:02 PM PDT 23 17707588 ps
T559 /workspace/coverage/default/33.edn_intr.2342182988 Oct 04 01:48:25 PM PDT 23 Oct 04 01:48:27 PM PDT 23 32738310 ps
T560 /workspace/coverage/default/28.edn_alert_test.3083298027 Oct 04 01:49:10 PM PDT 23 Oct 04 01:49:11 PM PDT 23 39512930 ps
T561 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.394531239 Oct 04 01:46:00 PM PDT 23 Oct 04 01:56:06 PM PDT 23 26124728883 ps
T562 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.387888013 Oct 04 01:53:17 PM PDT 23 Oct 04 02:03:22 PM PDT 23 85728384427 ps
T563 /workspace/coverage/default/19.edn_smoke.3608664738 Oct 04 01:47:58 PM PDT 23 Oct 04 01:48:00 PM PDT 23 46232664 ps
T293 /workspace/coverage/default/35.edn_genbits.3961124453 Oct 04 01:43:03 PM PDT 23 Oct 04 01:43:05 PM PDT 23 27278501 ps
T564 /workspace/coverage/default/37.edn_disable.1230309370 Oct 04 01:43:09 PM PDT 23 Oct 04 01:43:10 PM PDT 23 15419843 ps
T565 /workspace/coverage/default/6.edn_alert_test.3519918496 Oct 04 01:51:13 PM PDT 23 Oct 04 01:51:14 PM PDT 23 53098100 ps
T566 /workspace/coverage/default/25.edn_disable_auto_req_mode.1461529542 Oct 04 01:44:10 PM PDT 23 Oct 04 01:44:11 PM PDT 23 26488926 ps
T179 /workspace/coverage/default/42.edn_disable.2695030985 Oct 04 01:49:37 PM PDT 23 Oct 04 01:49:38 PM PDT 23 47395498 ps
T567 /workspace/coverage/default/11.edn_alert.3334802725 Oct 04 01:49:49 PM PDT 23 Oct 04 01:49:52 PM PDT 23 53472679 ps
T568 /workspace/coverage/default/4.edn_stress_all.604884689 Oct 04 01:42:20 PM PDT 23 Oct 04 01:42:24 PM PDT 23 779005087 ps
T569 /workspace/coverage/default/21.edn_stress_all.3994169048 Oct 04 01:47:56 PM PDT 23 Oct 04 01:48:00 PM PDT 23 609898726 ps
T570 /workspace/coverage/default/2.edn_err.3164470857 Oct 04 01:50:14 PM PDT 23 Oct 04 01:50:15 PM PDT 23 22097822 ps
T571 /workspace/coverage/default/28.edn_alert.3150313023 Oct 04 01:49:06 PM PDT 23 Oct 04 01:49:07 PM PDT 23 20624981 ps
T264 /workspace/coverage/default/83.edn_err.3626023301 Oct 04 01:49:53 PM PDT 23 Oct 04 01:49:55 PM PDT 23 29250963 ps
T572 /workspace/coverage/default/19.edn_alert.89692581 Oct 04 01:48:21 PM PDT 23 Oct 04 01:48:23 PM PDT 23 33623727 ps
T573 /workspace/coverage/default/11.edn_genbits.532979185 Oct 04 01:49:50 PM PDT 23 Oct 04 01:49:52 PM PDT 23 226640794 ps
T158 /workspace/coverage/default/44.edn_disable_auto_req_mode.3589267627 Oct 04 01:54:34 PM PDT 23 Oct 04 01:54:35 PM PDT 23 46501970 ps
T176 /workspace/coverage/default/74.edn_err.2134753774 Oct 04 01:46:43 PM PDT 23 Oct 04 01:46:44 PM PDT 23 19042141 ps
T574 /workspace/coverage/default/45.edn_genbits.575266764 Oct 04 01:48:18 PM PDT 23 Oct 04 01:48:19 PM PDT 23 16648495 ps
T575 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3657022797 Oct 04 01:53:24 PM PDT 23 Oct 04 02:11:48 PM PDT 23 72378642224 ps
T576 /workspace/coverage/default/15.edn_disable_auto_req_mode.1799760728 Oct 04 01:45:12 PM PDT 23 Oct 04 01:45:14 PM PDT 23 50129500 ps
T577 /workspace/coverage/default/19.edn_alert_test.963265075 Oct 04 01:49:38 PM PDT 23 Oct 04 01:49:40 PM PDT 23 150942724 ps
T578 /workspace/coverage/default/13.edn_stress_all.967054530 Oct 04 01:52:42 PM PDT 23 Oct 04 01:52:44 PM PDT 23 173214348 ps
T579 /workspace/coverage/default/16.edn_genbits.2375822284 Oct 04 01:52:53 PM PDT 23 Oct 04 01:52:55 PM PDT 23 87398562 ps
T580 /workspace/coverage/default/7.edn_intr.1257642071 Oct 04 01:42:30 PM PDT 23 Oct 04 01:42:31 PM PDT 23 90658589 ps
T581 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2766537428 Oct 04 01:42:06 PM PDT 23 Oct 04 01:48:14 PM PDT 23 161396229360 ps
T582 /workspace/coverage/default/17.edn_disable.3609018250 Oct 04 01:45:29 PM PDT 23 Oct 04 01:45:30 PM PDT 23 12404658 ps
T583 /workspace/coverage/default/49.edn_genbits.2153444004 Oct 04 01:46:18 PM PDT 23 Oct 04 01:46:20 PM PDT 23 186899803 ps
T584 /workspace/coverage/default/16.edn_intr.71002765 Oct 04 01:53:23 PM PDT 23 Oct 04 01:53:24 PM PDT 23 34920611 ps
T585 /workspace/coverage/default/40.edn_intr.3391864536 Oct 04 01:50:35 PM PDT 23 Oct 04 01:50:37 PM PDT 23 22722223 ps
T11 /workspace/coverage/default/28.edn_genbits.3004236476 Oct 04 01:53:25 PM PDT 23 Oct 04 01:53:27 PM PDT 23 24028388 ps
T108 /workspace/coverage/default/8.edn_intr.3312595525 Oct 04 01:50:32 PM PDT 23 Oct 04 01:50:34 PM PDT 23 23374813 ps
T164 /workspace/coverage/default/90.edn_err.3571863174 Oct 04 01:49:32 PM PDT 23 Oct 04 01:49:33 PM PDT 23 19514831 ps
T586 /workspace/coverage/default/12.edn_intr.3046024583 Oct 04 01:50:33 PM PDT 23 Oct 04 01:50:35 PM PDT 23 19717186 ps
T587 /workspace/coverage/default/0.edn_stress_all.342742390 Oct 04 01:50:48 PM PDT 23 Oct 04 01:50:52 PM PDT 23 535942486 ps
T256 /workspace/coverage/default/1.edn_disable.1141482387 Oct 04 01:52:16 PM PDT 23 Oct 04 01:52:17 PM PDT 23 48781984 ps
T312 /workspace/coverage/default/2.edn_alert.963676462 Oct 04 01:45:49 PM PDT 23 Oct 04 01:45:50 PM PDT 23 19076563 ps
T588 /workspace/coverage/default/66.edn_err.212466008 Oct 04 01:48:25 PM PDT 23 Oct 04 01:48:27 PM PDT 23 22583576 ps
T589 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1852280705 Oct 04 01:49:48 PM PDT 23 Oct 04 02:05:52 PM PDT 23 98881869857 ps
T590 /workspace/coverage/default/18.edn_smoke.3701720206 Oct 04 01:50:38 PM PDT 23 Oct 04 01:50:39 PM PDT 23 24585961 ps
T591 /workspace/coverage/default/93.edn_err.4126452210 Oct 04 01:51:38 PM PDT 23 Oct 04 01:51:40 PM PDT 23 30058947 ps
T592 /workspace/coverage/default/12.edn_smoke.1334609840 Oct 04 01:53:25 PM PDT 23 Oct 04 01:53:26 PM PDT 23 14034171 ps
T593 /workspace/coverage/default/39.edn_alert_test.2320084096 Oct 04 01:43:21 PM PDT 23 Oct 04 01:43:22 PM PDT 23 27280251 ps
T594 /workspace/coverage/default/45.edn_smoke.1461852347 Oct 04 01:50:53 PM PDT 23 Oct 04 01:50:55 PM PDT 23 36630871 ps
T595 /workspace/coverage/default/7.edn_stress_all.1670307085 Oct 04 01:49:38 PM PDT 23 Oct 04 01:49:41 PM PDT 23 88864035 ps
T596 /workspace/coverage/default/61.edn_err.527898907 Oct 04 01:49:41 PM PDT 23 Oct 04 01:49:43 PM PDT 23 69544041 ps
T174 /workspace/coverage/default/69.edn_err.2957984312 Oct 04 01:46:51 PM PDT 23 Oct 04 01:46:53 PM PDT 23 24685851 ps
T597 /workspace/coverage/default/23.edn_err.3498563724 Oct 04 01:44:00 PM PDT 23 Oct 04 01:44:02 PM PDT 23 32987479 ps
T258 /workspace/coverage/default/52.edn_err.2422644676 Oct 04 01:46:31 PM PDT 23 Oct 04 01:46:33 PM PDT 23 20030232 ps
T138 /workspace/coverage/default/35.edn_disable.2494956712 Oct 04 01:54:55 PM PDT 23 Oct 04 01:54:56 PM PDT 23 30899306 ps
T598 /workspace/coverage/default/50.edn_err.2332404172 Oct 04 01:49:52 PM PDT 23 Oct 04 01:49:55 PM PDT 23 40522316 ps
T309 /workspace/coverage/default/4.edn_alert.3167139906 Oct 04 01:51:54 PM PDT 23 Oct 04 01:51:55 PM PDT 23 21523657 ps
T599 /workspace/coverage/default/23.edn_alert_test.2035819465 Oct 04 01:47:58 PM PDT 23 Oct 04 01:48:00 PM PDT 23 14431146 ps
T292 /workspace/coverage/default/12.edn_genbits.1363174450 Oct 04 01:53:04 PM PDT 23 Oct 04 01:53:06 PM PDT 23 56585303 ps
T275 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4025874075 Oct 04 01:46:03 PM PDT 23 Oct 04 02:08:22 PM PDT 23 237144787209 ps
T600 /workspace/coverage/default/31.edn_intr.249996292 Oct 04 01:53:11 PM PDT 23 Oct 04 01:53:12 PM PDT 23 23302741 ps
T601 /workspace/coverage/default/3.edn_disable.4166439955 Oct 04 01:49:47 PM PDT 23 Oct 04 01:49:50 PM PDT 23 64717668 ps
T302 /workspace/coverage/default/6.edn_alert.1960688845 Oct 04 01:50:32 PM PDT 23 Oct 04 01:50:34 PM PDT 23 37530436 ps
T602 /workspace/coverage/default/18.edn_err.1514422180 Oct 04 01:47:03 PM PDT 23 Oct 04 01:47:04 PM PDT 23 38050528 ps
T603 /workspace/coverage/default/3.edn_disable_auto_req_mode.3932860355 Oct 04 01:51:59 PM PDT 23 Oct 04 01:52:00 PM PDT 23 41092591 ps
T604 /workspace/coverage/default/39.edn_intr.677440403 Oct 04 01:53:09 PM PDT 23 Oct 04 01:53:10 PM PDT 23 43076623 ps
T605 /workspace/coverage/default/33.edn_alert.1118102465 Oct 04 01:50:33 PM PDT 23 Oct 04 01:50:35 PM PDT 23 35336547 ps
T606 /workspace/coverage/default/25.edn_alert_test.2381937830 Oct 04 01:50:19 PM PDT 23 Oct 04 01:50:21 PM PDT 23 16435721 ps
T607 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1850133491 Oct 04 01:49:54 PM PDT 23 Oct 04 02:35:35 PM PDT 23 261103452734 ps
T608 /workspace/coverage/default/15.edn_genbits.3034527011 Oct 04 01:53:29 PM PDT 23 Oct 04 01:53:31 PM PDT 23 207101082 ps
T609 /workspace/coverage/default/42.edn_genbits.924099986 Oct 04 01:48:05 PM PDT 23 Oct 04 01:48:07 PM PDT 23 13598325 ps
T610 /workspace/coverage/default/17.edn_disable_auto_req_mode.400705531 Oct 04 01:43:25 PM PDT 23 Oct 04 01:43:27 PM PDT 23 55666050 ps
T611 /workspace/coverage/default/28.edn_stress_all.2017854104 Oct 04 01:52:40 PM PDT 23 Oct 04 01:52:44 PM PDT 23 327885741 ps
T612 /workspace/coverage/default/14.edn_genbits.822240039 Oct 04 01:42:03 PM PDT 23 Oct 04 01:42:05 PM PDT 23 109518590 ps
T249 /workspace/coverage/default/48.edn_err.4210139129 Oct 04 01:50:39 PM PDT 23 Oct 04 01:50:41 PM PDT 23 30031467 ps
T613 /workspace/coverage/default/26.edn_alert.2093967053 Oct 04 01:45:14 PM PDT 23 Oct 04 01:45:16 PM PDT 23 45700259 ps
T614 /workspace/coverage/default/25.edn_stress_all.2922215792 Oct 04 01:49:50 PM PDT 23 Oct 04 01:49:54 PM PDT 23 120790366 ps
T615 /workspace/coverage/default/7.edn_stress_all_with_rand_reset.367353077 Oct 04 01:43:02 PM PDT 23 Oct 04 02:32:16 PM PDT 23 584254027126 ps
T616 /workspace/coverage/default/14.edn_stress_all.2643762581 Oct 04 01:51:55 PM PDT 23 Oct 04 01:51:58 PM PDT 23 927421731 ps
T617 /workspace/coverage/default/8.edn_err.197770083 Oct 04 01:41:50 PM PDT 23 Oct 04 01:41:51 PM PDT 23 49412224 ps
T173 /workspace/coverage/default/12.edn_err.2773076063 Oct 04 01:53:34 PM PDT 23 Oct 04 01:53:36 PM PDT 23 32699470 ps
T618 /workspace/coverage/default/5.edn_smoke.810702575 Oct 04 01:50:35 PM PDT 23 Oct 04 01:50:36 PM PDT 23 44265303 ps
T619 /workspace/coverage/default/25.edn_alert.1124700588 Oct 04 01:54:11 PM PDT 23 Oct 04 01:54:12 PM PDT 23 34643842 ps
T620 /workspace/coverage/default/55.edn_err.428428001 Oct 04 01:50:48 PM PDT 23 Oct 04 01:50:50 PM PDT 23 22442509 ps
T162 /workspace/coverage/default/85.edn_err.2121772199 Oct 04 01:50:40 PM PDT 23 Oct 04 01:50:42 PM PDT 23 31336395 ps
T621 /workspace/coverage/default/13.edn_disable_auto_req_mode.4260122827 Oct 04 01:53:58 PM PDT 23 Oct 04 01:54:00 PM PDT 23 90112079 ps
T622 /workspace/coverage/default/34.edn_disable.134688256 Oct 04 01:49:48 PM PDT 23 Oct 04 01:49:51 PM PDT 23 35616377 ps
T623 /workspace/coverage/default/0.edn_alert_test.2870292248 Oct 04 01:49:08 PM PDT 23 Oct 04 01:49:10 PM PDT 23 51042073 ps
T624 /workspace/coverage/default/23.edn_alert.2356543215 Oct 04 01:49:53 PM PDT 23 Oct 04 01:49:55 PM PDT 23 25553516 ps
T12 /workspace/coverage/default/5.edn_genbits.4280340659 Oct 04 01:49:45 PM PDT 23 Oct 04 01:49:49 PM PDT 23 30514196 ps
T625 /workspace/coverage/default/46.edn_stress_all.793032208 Oct 04 01:49:50 PM PDT 23 Oct 04 01:49:55 PM PDT 23 146357293 ps
T626 /workspace/coverage/default/17.edn_genbits.1243363190 Oct 04 01:55:22 PM PDT 23 Oct 04 01:55:25 PM PDT 23 116543928 ps
T627 /workspace/coverage/default/10.edn_intr.1385573145 Oct 04 01:45:35 PM PDT 23 Oct 04 01:45:36 PM PDT 23 23433987 ps
T628 /workspace/coverage/default/24.edn_alert_test.3280116131 Oct 04 01:49:45 PM PDT 23 Oct 04 01:49:48 PM PDT 23 37170948 ps
T629 /workspace/coverage/default/44.edn_genbits.1879096037 Oct 04 01:45:51 PM PDT 23 Oct 04 01:45:53 PM PDT 23 80925096 ps
T630 /workspace/coverage/default/41.edn_stress_all.531977653 Oct 04 01:47:59 PM PDT 23 Oct 04 01:48:01 PM PDT 23 41653218 ps
T631 /workspace/coverage/default/11.edn_disable_auto_req_mode.1848913375 Oct 04 01:41:55 PM PDT 23 Oct 04 01:41:57 PM PDT 23 53543462 ps
T632 /workspace/coverage/default/29.edn_alert_test.1620109360 Oct 04 01:53:57 PM PDT 23 Oct 04 01:53:59 PM PDT 23 18859851 ps
T633 /workspace/coverage/default/10.edn_err.1231871404 Oct 04 01:45:26 PM PDT 23 Oct 04 01:45:28 PM PDT 23 29133307 ps
T261 /workspace/coverage/default/6.edn_disable.3948854129 Oct 04 01:51:12 PM PDT 23 Oct 04 01:51:13 PM PDT 23 22221522 ps
T634 /workspace/coverage/default/18.edn_alert_test.4191445958 Oct 04 01:52:51 PM PDT 23 Oct 04 01:52:53 PM PDT 23 33082451 ps
T254 /workspace/coverage/default/82.edn_err.806355112 Oct 04 01:49:49 PM PDT 23 Oct 04 01:49:52 PM PDT 23 29581722 ps
T635 /workspace/coverage/default/21.edn_err.2878385132 Oct 04 01:42:20 PM PDT 23 Oct 04 01:42:22 PM PDT 23 75316761 ps
T636 /workspace/coverage/default/30.edn_alert.1796114977 Oct 04 01:53:56 PM PDT 23 Oct 04 01:53:57 PM PDT 23 20359961 ps
T637 /workspace/coverage/default/4.edn_err.1941729113 Oct 04 01:41:27 PM PDT 23 Oct 04 01:41:28 PM PDT 23 31651558 ps
T638 /workspace/coverage/default/38.edn_genbits.1568050973 Oct 04 01:49:43 PM PDT 23 Oct 04 01:49:45 PM PDT 23 26109567 ps
T639 /workspace/coverage/default/13.edn_smoke.1823840035 Oct 04 01:49:47 PM PDT 23 Oct 04 01:49:49 PM PDT 23 14503013 ps
T177 /workspace/coverage/default/94.edn_err.3999713862 Oct 04 01:49:51 PM PDT 23 Oct 04 01:49:53 PM PDT 23 95233090 ps
T640 /workspace/coverage/default/59.edn_err.1562576541 Oct 04 01:53:24 PM PDT 23 Oct 04 01:53:26 PM PDT 23 22933830 ps
T641 /workspace/coverage/default/14.edn_alert_test.169423266 Oct 04 01:49:49 PM PDT 23 Oct 04 01:49:52 PM PDT 23 135722005 ps
T642 /workspace/coverage/default/39.edn_disable_auto_req_mode.1359940909 Oct 04 01:50:14 PM PDT 23 Oct 04 01:50:16 PM PDT 23 30799069 ps
T643 /workspace/coverage/default/14.edn_smoke.3569634929 Oct 04 01:42:00 PM PDT 23 Oct 04 01:42:02 PM PDT 23 15668820 ps
T128 /workspace/coverage/default/23.edn_disable_auto_req_mode.1554771664 Oct 04 01:50:46 PM PDT 23 Oct 04 01:50:47 PM PDT 23 91632974 ps
T644 /workspace/coverage/default/13.edn_alert_test.531431859 Oct 04 01:48:17 PM PDT 23 Oct 04 01:48:19 PM PDT 23 21803464 ps
T288 /workspace/coverage/default/7.edn_genbits.2454872239 Oct 04 01:49:49 PM PDT 23 Oct 04 01:49:52 PM PDT 23 18291354 ps
T645 /workspace/coverage/default/43.edn_alert_test.4203822407 Oct 04 01:49:44 PM PDT 23 Oct 04 01:49:47 PM PDT 23 36412861 ps
T151 /workspace/coverage/default/75.edn_err.279319994 Oct 04 01:48:44 PM PDT 23 Oct 04 01:48:45 PM PDT 23 31507000 ps
T259 /workspace/coverage/default/6.edn_err.1622417238 Oct 04 01:43:54 PM PDT 23 Oct 04 01:43:55 PM PDT 23 33247651 ps
T646 /workspace/coverage/default/2.edn_stress_all.3453036607 Oct 04 01:51:10 PM PDT 23 Oct 04 01:51:12 PM PDT 23 80079183 ps
T647 /workspace/coverage/default/47.edn_stress_all.810166975 Oct 04 01:49:47 PM PDT 23 Oct 04 01:49:52 PM PDT 23 896355892 ps
T276 /workspace/coverage/default/27.edn_stress_all.1929497266 Oct 04 01:44:43 PM PDT 23 Oct 04 01:44:46 PM PDT 23 254285878 ps
T648 /workspace/coverage/default/49.edn_alert.2105298164 Oct 04 01:50:27 PM PDT 23 Oct 04 01:50:29 PM PDT 23 18317040 ps
T649 /workspace/coverage/default/87.edn_err.3278989830 Oct 04 01:48:05 PM PDT 23 Oct 04 01:48:07 PM PDT 23 23855481 ps
T650 /workspace/coverage/default/4.edn_disable.1407980647 Oct 04 01:42:59 PM PDT 23 Oct 04 01:43:00 PM PDT 23 21874905 ps
T651 /workspace/coverage/default/3.edn_stress_all.923197838 Oct 04 01:48:05 PM PDT 23 Oct 04 01:48:10 PM PDT 23 319636750 ps
T652 /workspace/coverage/default/34.edn_smoke.2624703241 Oct 04 01:42:55 PM PDT 23 Oct 04 01:42:56 PM PDT 23 15360801 ps
T653 /workspace/coverage/default/10.edn_smoke.1928625317 Oct 04 01:48:07 PM PDT 23 Oct 04 01:48:09 PM PDT 23 12338224 ps
T654 /workspace/coverage/default/12.edn_stress_all.2979230245 Oct 04 01:46:18 PM PDT 23 Oct 04 01:46:21 PM PDT 23 122790272 ps
T655 /workspace/coverage/default/58.edn_err.4109265311 Oct 04 01:48:09 PM PDT 23 Oct 04 01:48:12 PM PDT 23 58289165 ps
T656 /workspace/coverage/default/21.edn_alert.2748761172 Oct 04 01:43:35 PM PDT 23 Oct 04 01:43:37 PM PDT 23 57296347 ps
T657 /workspace/coverage/default/47.edn_intr.709238623 Oct 04 01:50:58 PM PDT 23 Oct 04 01:51:00 PM PDT 23 19681359 ps
T266 /workspace/coverage/default/32.edn_err.1954009662 Oct 04 01:53:48 PM PDT 23 Oct 04 01:53:50 PM PDT 23 22839813 ps
T260 /workspace/coverage/default/15.edn_err.2607994367 Oct 04 01:51:15 PM PDT 23 Oct 04 01:51:17 PM PDT 23 32757909 ps
T658 /workspace/coverage/default/30.edn_err.2253477233 Oct 04 01:43:38 PM PDT 23 Oct 04 01:43:40 PM PDT 23 28892483 ps
T659 /workspace/coverage/default/11.edn_smoke.4228771855 Oct 04 01:45:24 PM PDT 23 Oct 04 01:45:26 PM PDT 23 22421117 ps
T660 /workspace/coverage/default/68.edn_err.4046854337 Oct 04 01:50:39 PM PDT 23 Oct 04 01:50:41 PM PDT 23 18484634 ps
T661 /workspace/coverage/default/38.edn_alert_test.3183458905 Oct 04 01:52:20 PM PDT 23 Oct 04 01:52:21 PM PDT 23 34782296 ps
T662 /workspace/coverage/default/45.edn_stress_all.2952553017 Oct 04 01:46:24 PM PDT 23 Oct 04 01:46:26 PM PDT 23 38835707 ps
T663 /workspace/coverage/default/49.edn_intr.3842829482 Oct 04 01:46:26 PM PDT 23 Oct 04 01:46:27 PM PDT 23 36923764 ps
T135 /workspace/coverage/default/25.edn_disable.2768877243 Oct 04 01:47:27 PM PDT 23 Oct 04 01:47:28 PM PDT 23 19985794 ps
T664 /workspace/coverage/default/43.edn_smoke.2211484252 Oct 04 01:48:03 PM PDT 23 Oct 04 01:48:04 PM PDT 23 48546882 ps
T665 /workspace/coverage/default/1.edn_alert.545858079 Oct 04 01:42:30 PM PDT 23 Oct 04 01:42:31 PM PDT 23 18763361 ps
T666 /workspace/coverage/default/13.edn_alert.2336094179 Oct 04 01:45:56 PM PDT 23 Oct 04 01:45:57 PM PDT 23 20003547 ps
T667 /workspace/coverage/default/32.edn_disable_auto_req_mode.3539260872 Oct 04 01:45:52 PM PDT 23 Oct 04 01:45:53 PM PDT 23 58414932 ps
T668 /workspace/coverage/default/30.edn_alert_test.1272942477 Oct 04 01:50:33 PM PDT 23 Oct 04 01:50:36 PM PDT 23 12671346 ps
T669 /workspace/coverage/default/17.edn_smoke.764108136 Oct 04 01:43:13 PM PDT 23 Oct 04 01:43:14 PM PDT 23 58036625 ps
T670 /workspace/coverage/default/41.edn_alert_test.3151878531 Oct 04 01:49:47 PM PDT 23 Oct 04 01:49:49 PM PDT 23 16223971 ps
T671 /workspace/coverage/default/21.edn_genbits.1979850342 Oct 04 01:51:35 PM PDT 23 Oct 04 01:51:37 PM PDT 23 28330478 ps
T672 /workspace/coverage/default/36.edn_smoke.2563776549 Oct 04 01:47:58 PM PDT 23 Oct 04 01:48:00 PM PDT 23 24263287 ps
T673 /workspace/coverage/default/18.edn_disable_auto_req_mode.3169515656 Oct 04 01:45:26 PM PDT 23 Oct 04 01:45:27 PM PDT 23 44912814 ps
T674 /workspace/coverage/default/9.edn_alert.2467865842 Oct 04 01:45:57 PM PDT 23 Oct 04 01:45:59 PM PDT 23 21539257 ps
T257 /workspace/coverage/default/19.edn_disable.3379309835 Oct 04 01:45:58 PM PDT 23 Oct 04 01:46:00 PM PDT 23 24423986 ps
T675 /workspace/coverage/default/33.edn_err.1614044337 Oct 04 01:43:59 PM PDT 23 Oct 04 01:44:01 PM PDT 23 162230010 ps
T676 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.135387768 Oct 04 01:53:41 PM PDT 23 Oct 04 02:08:31 PM PDT 23 136152507860 ps
T677 /workspace/coverage/default/60.edn_err.2579707968 Oct 04 01:50:03 PM PDT 23 Oct 04 01:50:05 PM PDT 23 30136167 ps
T678 /workspace/coverage/default/39.edn_alert.2630564240 Oct 04 01:49:26 PM PDT 23 Oct 04 01:49:27 PM PDT 23 262792477 ps
T679 /workspace/coverage/default/99.edn_err.1433805499 Oct 04 01:51:23 PM PDT 23 Oct 04 01:51:25 PM PDT 23 21984418 ps
T265 /workspace/coverage/default/26.edn_disable.3080420662 Oct 04 01:44:44 PM PDT 23 Oct 04 01:44:45 PM PDT 23 19753789 ps
T680 /workspace/coverage/default/15.edn_alert_test.4079373760 Oct 04 01:42:04 PM PDT 23 Oct 04 01:42:05 PM PDT 23 30352716 ps
T681 /workspace/coverage/default/15.edn_intr.590574529 Oct 04 01:51:37 PM PDT 23 Oct 04 01:51:38 PM PDT 23 17741261 ps
T682 /workspace/coverage/default/41.edn_err.344236439 Oct 04 01:49:30 PM PDT 23 Oct 04 01:49:31 PM PDT 23 18021779 ps
T683 /workspace/coverage/default/3.edn_smoke.1621078771 Oct 04 01:43:59 PM PDT 23 Oct 04 01:44:01 PM PDT 23 18776812 ps
T684 /workspace/coverage/default/10.edn_disable_auto_req_mode.3058364924 Oct 04 02:14:08 PM PDT 23 Oct 04 02:14:09 PM PDT 23 42238049 ps
T685 /workspace/coverage/default/34.edn_stress_all.1670746470 Oct 04 01:50:35 PM PDT 23 Oct 04 01:50:39 PM PDT 23 336760166 ps
T686 /workspace/coverage/default/48.edn_genbits.859235766 Oct 04 01:54:34 PM PDT 23 Oct 04 01:54:36 PM PDT 23 27687967 ps
T255 /workspace/coverage/default/44.edn_err.1281366173 Oct 04 01:52:12 PM PDT 23 Oct 04 01:52:14 PM PDT 23 54372580 ps
T687 /workspace/coverage/default/3.edn_intr.2006619531 Oct 04 01:53:05 PM PDT 23 Oct 04 01:53:07 PM PDT 23 58604224 ps
T688 /workspace/coverage/default/4.edn_smoke.816505950 Oct 04 01:54:23 PM PDT 23 Oct 04 01:54:25 PM PDT 23 18186279 ps
T689 /workspace/coverage/default/37.edn_alert_test.2707995600 Oct 04 01:51:10 PM PDT 23 Oct 04 01:51:12 PM PDT 23 20182744 ps
T690 /workspace/coverage/default/30.edn_smoke.2439283475 Oct 04 01:54:57 PM PDT 23 Oct 04 01:54:59 PM PDT 23 15595181 ps
T691 /workspace/coverage/default/29.edn_stress_all.3502972830 Oct 04 01:54:23 PM PDT 23 Oct 04 01:54:28 PM PDT 23 141207960 ps
T692 /workspace/coverage/default/12.edn_disable_auto_req_mode.1910090574 Oct 04 01:47:49 PM PDT 23 Oct 04 01:47:50 PM PDT 23 27037265 ps
T693 /workspace/coverage/default/3.edn_genbits.2413361753 Oct 04 01:51:54 PM PDT 23 Oct 04 01:51:55 PM PDT 23 23654380 ps
T694 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3232630008 Oct 04 01:46:25 PM PDT 23 Oct 04 01:52:24 PM PDT 23 28292034681 ps
T695 /workspace/coverage/default/24.edn_stress_all.2124507649 Oct 04 01:42:29 PM PDT 23 Oct 04 01:42:32 PM PDT 23 90663825 ps
T696 /workspace/coverage/default/73.edn_err.1089853313 Oct 04 01:50:31 PM PDT 23 Oct 04 01:50:34 PM PDT 23 18053568 ps
T697 /workspace/coverage/default/32.edn_stress_all.643562219 Oct 04 01:48:34 PM PDT 23 Oct 04 01:48:38 PM PDT 23 664749808 ps
T280 /workspace/coverage/default/31.edn_stress_all.4115692556 Oct 04 01:42:52 PM PDT 23 Oct 04 01:42:56 PM PDT 23 706090699 ps
T55 /workspace/coverage/default/1.edn_sec_cm.1910077520 Oct 04 01:43:17 PM PDT 23 Oct 04 01:43:21 PM PDT 23 257819001 ps
T698 /workspace/coverage/default/20.edn_err.2745722023 Oct 04 01:51:13 PM PDT 23 Oct 04 01:51:15 PM PDT 23 26527992 ps
T311 /workspace/coverage/default/44.edn_alert.1146509504 Oct 04 01:54:23 PM PDT 23 Oct 04 01:54:25 PM PDT 23 31811263 ps
T165 /workspace/coverage/default/0.edn_err.3662067682 Oct 04 01:42:55 PM PDT 23 Oct 04 01:42:56 PM PDT 23 19352747 ps
T699 /workspace/coverage/default/5.edn_regwen.2991819124 Oct 04 01:44:04 PM PDT 23 Oct 04 01:44:06 PM PDT 23 21398626 ps
T700 /workspace/coverage/default/48.edn_alert_test.3044217832 Oct 04 01:46:31 PM PDT 23 Oct 04 01:46:32 PM PDT 23 46157454 ps
T701 /workspace/coverage/default/45.edn_alert.1370499438 Oct 04 01:46:28 PM PDT 23 Oct 04 01:46:31 PM PDT 23 36069761 ps
T153 /workspace/coverage/default/7.edn_err.3651888242 Oct 04 01:49:43 PM PDT 23 Oct 04 01:49:44 PM PDT 23 19323107 ps
T702 /workspace/coverage/default/91.edn_err.1052952077 Oct 04 01:53:09 PM PDT 23 Oct 04 01:53:11 PM PDT 23 32907055 ps
T703 /workspace/coverage/default/17.edn_alert.1510047810 Oct 04 01:45:59 PM PDT 23 Oct 04 01:46:00 PM PDT 23 57140519 ps
T136 /workspace/coverage/default/0.edn_disable_auto_req_mode.2340001281 Oct 04 01:51:03 PM PDT 23 Oct 04 01:51:05 PM PDT 23 93961627 ps
T291 /workspace/coverage/default/27.edn_genbits.2811767886 Oct 04 01:44:42 PM PDT 23 Oct 04 01:44:43 PM PDT 23 38870554 ps
T704 /workspace/coverage/default/46.edn_disable.1179831073 Oct 04 01:48:02 PM PDT 23 Oct 04 01:48:03 PM PDT 23 31292441 ps
T705 /workspace/coverage/default/46.edn_smoke.1415585590 Oct 04 01:54:35 PM PDT 23 Oct 04 01:54:37 PM PDT 23 16196237 ps
T706 /workspace/coverage/default/88.edn_err.388258289 Oct 04 01:55:07 PM PDT 23 Oct 04 01:55:08 PM PDT 23 24197470 ps
T707 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1957400527 Oct 04 01:50:40 PM PDT 23 Oct 04 02:05:56 PM PDT 23 71829106989 ps
T708 /workspace/coverage/default/35.edn_stress_all.516338423 Oct 04 01:50:27 PM PDT 23 Oct 04 01:50:30 PM PDT 23 257980320 ps
T709 /workspace/coverage/default/10.edn_alert.1133400792 Oct 04 01:51:52 PM PDT 23 Oct 04 01:51:54 PM PDT 23 21078046 ps
T303 /workspace/coverage/default/27.edn_alert.4248509206 Oct 04 01:46:20 PM PDT 23 Oct 04 01:46:21 PM PDT 23 54227234 ps
T133 /workspace/coverage/default/49.edn_disable.3706289834 Oct 04 01:46:48 PM PDT 23 Oct 04 01:46:49 PM PDT 23 19749622 ps
T710 /workspace/coverage/default/32.edn_smoke.825417183 Oct 04 01:49:36 PM PDT 23 Oct 04 01:49:37 PM PDT 23 24907659 ps
T175 /workspace/coverage/default/80.edn_err.2307489079 Oct 04 01:50:41 PM PDT 23 Oct 04 01:50:42 PM PDT 23 24611176 ps
T711 /workspace/coverage/default/28.edn_smoke.1672400099 Oct 04 01:45:41 PM PDT 23 Oct 04 01:45:43 PM PDT 23 102914032 ps
T712 /workspace/coverage/default/98.edn_err.3127392471 Oct 04 01:46:43 PM PDT 23 Oct 04 01:46:45 PM PDT 23 18808402 ps
T713 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.437211864 Oct 04 01:51:17 PM PDT 23 Oct 04 02:05:24 PM PDT 23 38970195445 ps
T714 /workspace/coverage/default/22.edn_disable_auto_req_mode.3091865883 Oct 04 01:43:36 PM PDT 23 Oct 04 01:43:37 PM PDT 23 23817942 ps
T715 /workspace/coverage/default/21.edn_smoke.1500217222 Oct 04 01:48:03 PM PDT 23 Oct 04 01:48:05 PM PDT 23 14993365 ps
T716 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1849412866 Oct 04 01:46:34 PM PDT 23 Oct 04 02:04:42 PM PDT 23 44404011622 ps
T717 /workspace/coverage/default/32.edn_alert.4099305944 Oct 04 01:48:21 PM PDT 23 Oct 04 01:48:23 PM PDT 23 21120032 ps
T718 /workspace/coverage/default/21.edn_alert_test.2072560504 Oct 04 01:51:07 PM PDT 23 Oct 04 01:51:09 PM PDT 23 29399075 ps
T719 /workspace/coverage/default/44.edn_alert_test.1479094788 Oct 04 01:43:43 PM PDT 23 Oct 04 01:43:44 PM PDT 23 14370455 ps
T720 /workspace/coverage/default/4.edn_disable_auto_req_mode.1520064574 Oct 04 01:46:25 PM PDT 23 Oct 04 01:46:27 PM PDT 23 35279870 ps
T721 /workspace/coverage/default/3.edn_err.2218916215 Oct 04 01:52:20 PM PDT 23 Oct 04 01:52:23 PM PDT 23 29136303 ps
T722 /workspace/coverage/default/48.edn_smoke.134689542 Oct 04 01:49:13 PM PDT 23 Oct 04 01:49:15 PM PDT 23 25281994 ps
T723 /workspace/coverage/default/42.edn_disable_auto_req_mode.2841941796 Oct 04 01:49:56 PM PDT 23 Oct 04 01:49:58 PM PDT 23 283153906 ps
T724 /workspace/coverage/default/53.edn_err.2581393997 Oct 04 01:49:53 PM PDT 23 Oct 04 01:49:56 PM PDT 23 35489651 ps
T725 /workspace/coverage/default/27.edn_smoke.1133257241 Oct 04 01:51:28 PM PDT 23 Oct 04 01:51:30 PM PDT 23 27398984 ps
T726 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.257984780 Oct 04 01:50:39 PM PDT 23 Oct 04 01:55:28 PM PDT 23 17292755987 ps
T727 /workspace/coverage/default/2.edn_disable.4063586483 Oct 04 01:45:44 PM PDT 23 Oct 04 01:45:45 PM PDT 23 41380410 ps
T728 /workspace/coverage/default/37.edn_stress_all.1480109155 Oct 04 01:54:00 PM PDT 23 Oct 04 01:54:04 PM PDT 23 1041082290 ps
T729 /workspace/coverage/default/36.edn_genbits.854825635 Oct 04 01:45:57 PM PDT 23 Oct 04 01:45:59 PM PDT 23 32293484 ps

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1284945232
Short name T9
Test name
Test status
Simulation time 18280441 ps
CPU time 0.95 seconds
Started Oct 04 01:50:30 PM PDT 23
Finished Oct 04 01:50:32 PM PDT 23
Peak memory 214624 kb
Host smart-b57743e2-900a-4548-9c97-ec62ef04923c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284945232 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1284945232
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_stress_all.2552026863
Short name T43
Test name
Test status
Simulation time 371829656 ps
CPU time 4.27 seconds
Started Oct 04 01:50:12 PM PDT 23
Finished Oct 04 01:50:17 PM PDT 23
Peak memory 206264 kb
Host smart-cb5d8be9-3ce1-4532-9e42-b3e37e8af1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552026863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2552026863
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_genbits.1310875730
Short name T29
Test name
Test status
Simulation time 206278237 ps
CPU time 1.33 seconds
Started Oct 04 01:44:04 PM PDT 23
Finished Oct 04 01:44:06 PM PDT 23
Peak memory 205228 kb
Host smart-9f72ebc7-2218-491d-8cac-c1bef05074e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310875730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1310875730
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1769180574
Short name T1
Test name
Test status
Simulation time 167084374 ps
CPU time 3.17 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 233476 kb
Host smart-ebe66131-0233-4bb3-b68c-9c50cfdae175
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769180574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1769180574
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1462763879
Short name T21
Test name
Test status
Simulation time 34112191167 ps
CPU time 752.67 seconds
Started Oct 04 02:07:30 PM PDT 23
Finished Oct 04 02:20:03 PM PDT 23
Peak memory 215876 kb
Host smart-001113d3-35a7-41c3-81e1-7d6c09d60488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462763879 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1462763879
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_disable.618925624
Short name T60
Test name
Test status
Simulation time 53288641 ps
CPU time 0.82 seconds
Started Oct 04 01:44:01 PM PDT 23
Finished Oct 04 01:44:02 PM PDT 23
Peak memory 214556 kb
Host smart-cb4cc294-e3ca-4cd0-9fe4-83a4fefedb0a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618925624 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.618925624
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1910077520
Short name T55
Test name
Test status
Simulation time 257819001 ps
CPU time 4.25 seconds
Started Oct 04 01:43:17 PM PDT 23
Finished Oct 04 01:43:21 PM PDT 23
Peak memory 232100 kb
Host smart-21b27baa-688d-46ed-8332-43e5a0d61faf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910077520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1910077520
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/41.edn_intr.2658998818
Short name T46
Test name
Test status
Simulation time 27297387 ps
CPU time 0.93 seconds
Started Oct 04 01:51:19 PM PDT 23
Finished Oct 04 01:51:21 PM PDT 23
Peak memory 214604 kb
Host smart-878e1573-d181-4794-923d-31c917384985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658998818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2658998818
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/43.edn_alert.3696272251
Short name T25
Test name
Test status
Simulation time 28485939 ps
CPU time 0.99 seconds
Started Oct 04 01:51:42 PM PDT 23
Finished Oct 04 01:51:43 PM PDT 23
Peak memory 205168 kb
Host smart-af44aaf3-6625-47c0-9e3c-c8fe12e6dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696272251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3696272251
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1135315932
Short name T41
Test name
Test status
Simulation time 71527275 ps
CPU time 0.98 seconds
Started Oct 04 01:43:55 PM PDT 23
Finished Oct 04 01:43:56 PM PDT 23
Peak memory 206304 kb
Host smart-da996536-bc28-4868-b1b3-1f229926142e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135315932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1135315932
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_regwen.694721550
Short name T129
Test name
Test status
Simulation time 70614661 ps
CPU time 0.87 seconds
Started Oct 04 01:43:45 PM PDT 23
Finished Oct 04 01:43:46 PM PDT 23
Peak memory 204812 kb
Host smart-24f3caae-99ed-4361-947c-17604a17666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694721550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.694721550
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3829759477
Short name T76
Test name
Test status
Simulation time 30765289 ps
CPU time 1.08 seconds
Started Oct 04 01:45:39 PM PDT 23
Finished Oct 04 01:45:40 PM PDT 23
Peak memory 214632 kb
Host smart-a9c2e376-0f4c-4d6f-b3bb-b2b18241922e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829759477 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3829759477
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1554771664
Short name T128
Test name
Test status
Simulation time 91632974 ps
CPU time 0.93 seconds
Started Oct 04 01:50:46 PM PDT 23
Finished Oct 04 01:50:47 PM PDT 23
Peak memory 206600 kb
Host smart-8a812753-6a8d-4ad7-9d0e-01ac2758ef29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554771664 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1554771664
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/81.edn_err.2730505749
Short name T105
Test name
Test status
Simulation time 21404223 ps
CPU time 1.15 seconds
Started Oct 04 01:51:19 PM PDT 23
Finished Oct 04 01:51:21 PM PDT 23
Peak memory 228624 kb
Host smart-baa2d7f3-d3f7-41af-9db6-50e4bac5fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730505749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2730505749
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/19.edn_disable.3379309835
Short name T257
Test name
Test status
Simulation time 24423986 ps
CPU time 0.89 seconds
Started Oct 04 01:45:58 PM PDT 23
Finished Oct 04 01:46:00 PM PDT 23
Peak memory 214616 kb
Host smart-9e5fb5b9-93ce-4758-9916-6fbee1ee4900
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379309835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3379309835
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2622492416
Short name T197
Test name
Test status
Simulation time 130156631 ps
CPU time 2.95 seconds
Started Oct 04 03:03:51 PM PDT 23
Finished Oct 04 03:03:55 PM PDT 23
Peak memory 205880 kb
Host smart-5d1d670d-b57c-4f16-8abe-aa3357317f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622492416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2622492416
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.511706770
Short name T185
Test name
Test status
Simulation time 299984329334 ps
CPU time 1748.93 seconds
Started Oct 04 01:45:51 PM PDT 23
Finished Oct 04 02:15:00 PM PDT 23
Peak memory 219392 kb
Host smart-6a73f580-4627-4b98-9fa1-424e67bd8e75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511706770 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.511706770
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_disable.3870570018
Short name T68
Test name
Test status
Simulation time 47688892 ps
CPU time 0.91 seconds
Started Oct 04 01:43:49 PM PDT 23
Finished Oct 04 01:43:50 PM PDT 23
Peak memory 214344 kb
Host smart-68545fc7-e518-4ce0-b165-c73b6ba3cd04
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870570018 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3870570018
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.3431659110
Short name T96
Test name
Test status
Simulation time 37296988 ps
CPU time 0.86 seconds
Started Oct 04 01:46:01 PM PDT 23
Finished Oct 04 01:46:03 PM PDT 23
Peak memory 214576 kb
Host smart-db01e28e-29b7-411a-9420-493d9caef912
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431659110 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3431659110
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1634497638
Short name T199
Test name
Test status
Simulation time 37652774 ps
CPU time 1.51 seconds
Started Oct 04 03:00:28 PM PDT 23
Finished Oct 04 03:00:30 PM PDT 23
Peak memory 205868 kb
Host smart-36e31e68-55f6-4228-bae4-15e2cffb1383
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634497638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1634497638
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/21.edn_intr.1682985205
Short name T110
Test name
Test status
Simulation time 49634373 ps
CPU time 0.83 seconds
Started Oct 04 01:43:37 PM PDT 23
Finished Oct 04 01:43:38 PM PDT 23
Peak memory 214456 kb
Host smart-2b52473c-ccef-40ee-bb26-56609b6b7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682985205 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1682985205
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1910090574
Short name T692
Test name
Test status
Simulation time 27037265 ps
CPU time 1.04 seconds
Started Oct 04 01:47:49 PM PDT 23
Finished Oct 04 01:47:50 PM PDT 23
Peak memory 214696 kb
Host smart-5bf11f1d-9cba-4ae2-a193-c2b8f51b60c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910090574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1910090574
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_genbits.4280340659
Short name T12
Test name
Test status
Simulation time 30514196 ps
CPU time 1.33 seconds
Started Oct 04 01:49:45 PM PDT 23
Finished Oct 04 01:49:49 PM PDT 23
Peak memory 214500 kb
Host smart-0d10c983-0797-40eb-80de-3a0c7bba0f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280340659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4280340659
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.688106166
Short name T90
Test name
Test status
Simulation time 21304157 ps
CPU time 1.03 seconds
Started Oct 04 01:45:41 PM PDT 23
Finished Oct 04 01:45:42 PM PDT 23
Peak memory 214564 kb
Host smart-286f0b3b-730d-4d65-85ec-34a328215976
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688106166 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.688106166
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.174280882
Short name T30
Test name
Test status
Simulation time 16878572 ps
CPU time 0.98 seconds
Started Oct 04 01:43:09 PM PDT 23
Finished Oct 04 01:43:11 PM PDT 23
Peak memory 214648 kb
Host smart-2e30befc-8c8f-4c8c-ab33-81e4ce9f233b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174280882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.174280882
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2340001281
Short name T136
Test name
Test status
Simulation time 93961627 ps
CPU time 0.94 seconds
Started Oct 04 01:51:03 PM PDT 23
Finished Oct 04 01:51:05 PM PDT 23
Peak memory 206488 kb
Host smart-818172a2-6b22-44fc-9a0b-8e537ccfa37d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340001281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2340001281
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable.3740164516
Short name T74
Test name
Test status
Simulation time 18560056 ps
CPU time 0.86 seconds
Started Oct 04 01:49:14 PM PDT 23
Finished Oct 04 01:49:15 PM PDT 23
Peak memory 206360 kb
Host smart-d05d37b2-fece-4490-920d-bfb9a5cb1330
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740164516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3740164516
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.3080420662
Short name T265
Test name
Test status
Simulation time 19753789 ps
CPU time 0.85 seconds
Started Oct 04 01:44:44 PM PDT 23
Finished Oct 04 01:44:45 PM PDT 23
Peak memory 214444 kb
Host smart-abd6d9ab-108b-4fb8-9c96-2d667c70d032
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080420662 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3080420662
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/24.edn_intr.2512795925
Short name T37
Test name
Test status
Simulation time 19373436 ps
CPU time 1.15 seconds
Started Oct 04 01:52:02 PM PDT 23
Finished Oct 04 01:52:04 PM PDT 23
Peak memory 225656 kb
Host smart-250c8f27-e763-4323-8e0b-e45bd66ff4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512795925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2512795925
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.1978865642
Short name T178
Test name
Test status
Simulation time 13301885 ps
CPU time 0.85 seconds
Started Oct 04 01:44:03 PM PDT 23
Finished Oct 04 01:44:04 PM PDT 23
Peak memory 214428 kb
Host smart-33a66598-931c-414b-ac2b-cfbbc64f394d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978865642 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1978865642
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.4021429456
Short name T82
Test name
Test status
Simulation time 31960298 ps
CPU time 0.82 seconds
Started Oct 04 01:42:10 PM PDT 23
Finished Oct 04 01:42:11 PM PDT 23
Peak memory 214396 kb
Host smart-6cecf272-9d06-4d78-a9b4-43c8769e4d53
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021429456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4021429456
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.3980693094
Short name T511
Test name
Test status
Simulation time 16038146 ps
CPU time 0.85 seconds
Started Oct 04 01:44:49 PM PDT 23
Finished Oct 04 01:44:50 PM PDT 23
Peak memory 214344 kb
Host smart-3021afa8-9c38-4f5b-a373-7241489995fa
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980693094 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3980693094
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.966098812
Short name T159
Test name
Test status
Simulation time 83644832 ps
CPU time 1.01 seconds
Started Oct 04 01:48:06 PM PDT 23
Finished Oct 04 01:48:07 PM PDT 23
Peak memory 214680 kb
Host smart-3ea44e7c-77e6-467e-8a6c-211a5303efb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966098812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.966098812
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_alert.1265440289
Short name T73
Test name
Test status
Simulation time 31940369 ps
CPU time 0.95 seconds
Started Oct 04 01:53:21 PM PDT 23
Finished Oct 04 01:53:22 PM PDT 23
Peak memory 205116 kb
Host smart-0097ea55-3038-4deb-aef0-9f1ffec9913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265440289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1265440289
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert.545858079
Short name T665
Test name
Test status
Simulation time 18763361 ps
CPU time 0.96 seconds
Started Oct 04 01:42:30 PM PDT 23
Finished Oct 04 01:42:31 PM PDT 23
Peak memory 205328 kb
Host smart-d52b4c44-19fc-4ba0-b2c7-433052c90456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545858079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.545858079
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.1638336112
Short name T91
Test name
Test status
Simulation time 55164962 ps
CPU time 0.92 seconds
Started Oct 04 01:42:08 PM PDT 23
Finished Oct 04 01:42:10 PM PDT 23
Peak memory 206128 kb
Host smart-e8ff15b6-1b34-4408-b813-c06ba3d9a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638336112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1638336112
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.776764281
Short name T20
Test name
Test status
Simulation time 61693018767 ps
CPU time 364.59 seconds
Started Oct 04 01:48:55 PM PDT 23
Finished Oct 04 01:55:00 PM PDT 23
Peak memory 214844 kb
Host smart-1f26e79a-cda4-4d15-9589-5472c8fbb538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776764281 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.776764281
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3496857807
Short name T314
Test name
Test status
Simulation time 82868504 ps
CPU time 0.81 seconds
Started Oct 04 01:53:14 PM PDT 23
Finished Oct 04 01:53:16 PM PDT 23
Peak memory 204592 kb
Host smart-2ea3737b-62c2-4580-b38e-0c8594d5ce3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496857807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3496857807
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_regwen.840392987
Short name T308
Test name
Test status
Simulation time 12592518 ps
CPU time 0.92 seconds
Started Oct 04 01:49:49 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 204800 kb
Host smart-7671875b-5c0b-4be2-9742-eca4cf29ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840392987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.840392987
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_stress_all.2466971452
Short name T117
Test name
Test status
Simulation time 255379648 ps
CPU time 1.92 seconds
Started Oct 04 01:52:42 PM PDT 23
Finished Oct 04 01:52:44 PM PDT 23
Peak memory 205728 kb
Host smart-94f613ae-1903-4c24-96f5-8749d5f64c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466971452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2466971452
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all.967054530
Short name T578
Test name
Test status
Simulation time 173214348 ps
CPU time 1.47 seconds
Started Oct 04 01:52:42 PM PDT 23
Finished Oct 04 01:52:44 PM PDT 23
Peak memory 205220 kb
Host smart-6e889500-9a01-4c3e-9876-4f9a8088902d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967054530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.967054530
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_genbits.2856734819
Short name T24
Test name
Test status
Simulation time 18476402 ps
CPU time 1.01 seconds
Started Oct 04 01:54:48 PM PDT 23
Finished Oct 04 01:54:49 PM PDT 23
Peak memory 205620 kb
Host smart-90cb70b0-d78f-432c-8e1b-6a4442c6bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856734819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2856734819
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_genbits.3352308265
Short name T286
Test name
Test status
Simulation time 16626424 ps
CPU time 0.98 seconds
Started Oct 04 01:48:54 PM PDT 23
Finished Oct 04 01:48:56 PM PDT 23
Peak memory 204880 kb
Host smart-314c0e7a-7dcb-4b85-8586-c9bc795541bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352308265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3352308265
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4025874075
Short name T275
Test name
Test status
Simulation time 237144787209 ps
CPU time 1337.69 seconds
Started Oct 04 01:46:03 PM PDT 23
Finished Oct 04 02:08:22 PM PDT 23
Peak memory 217876 kb
Host smart-5ddeee0c-79d5-41a1-8298-3adbaf21ecba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025874075 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4025874075
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.edn_regwen.2545600509
Short name T305
Test name
Test status
Simulation time 14206011 ps
CPU time 0.88 seconds
Started Oct 04 01:53:39 PM PDT 23
Finished Oct 04 01:53:41 PM PDT 23
Peak memory 204960 kb
Host smart-8de23304-317b-4d94-a93b-435bf671ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545600509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2545600509
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_genbits.2454872239
Short name T288
Test name
Test status
Simulation time 18291354 ps
CPU time 1.05 seconds
Started Oct 04 01:49:49 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 204880 kb
Host smart-650ec1ec-0038-4cdb-84cd-5469c208c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454872239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2454872239
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_err.140631214
Short name T7
Test name
Test status
Simulation time 43852609 ps
CPU time 1.18 seconds
Started Oct 04 01:53:57 PM PDT 23
Finished Oct 04 01:53:59 PM PDT 23
Peak memory 214576 kb
Host smart-a70ef13e-f0c1-468a-963c-de8aa88a575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140631214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.140631214
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2281863274
Short name T285
Test name
Test status
Simulation time 97792776 ps
CPU time 2.29 seconds
Started Oct 04 03:03:56 PM PDT 23
Finished Oct 04 03:03:59 PM PDT 23
Peak memory 205836 kb
Host smart-eaa422a6-021f-4869-8eef-daa2eafa283b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281863274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2281863274
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.1328344986
Short name T300
Test name
Test status
Simulation time 66875139 ps
CPU time 0.85 seconds
Started Oct 04 01:50:37 PM PDT 23
Finished Oct 04 01:50:38 PM PDT 23
Peak memory 205048 kb
Host smart-d6019af0-a9bf-4d78-ab67-cd871c5346ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328344986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1328344986
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_alert.963676462
Short name T312
Test name
Test status
Simulation time 19076563 ps
CPU time 1 seconds
Started Oct 04 01:45:49 PM PDT 23
Finished Oct 04 01:45:50 PM PDT 23
Peak memory 205184 kb
Host smart-98b323c2-003f-43d6-9996-284b8c8c23c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963676462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.963676462
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.2213319342
Short name T299
Test name
Test status
Simulation time 13492028 ps
CPU time 0.86 seconds
Started Oct 04 01:53:36 PM PDT 23
Finished Oct 04 01:53:37 PM PDT 23
Peak memory 204872 kb
Host smart-0e11af34-5c31-4f4a-b6b6-b9187d65ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213319342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2213319342
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_err.2766318701
Short name T47
Test name
Test status
Simulation time 27240758 ps
CPU time 1 seconds
Started Oct 04 01:53:11 PM PDT 23
Finished Oct 04 01:53:12 PM PDT 23
Peak memory 221836 kb
Host smart-05ed1baf-9279-4115-88c1-493682eaf222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766318701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2766318701
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/27.edn_alert.4248509206
Short name T303
Test name
Test status
Simulation time 54227234 ps
CPU time 1.02 seconds
Started Oct 04 01:46:20 PM PDT 23
Finished Oct 04 01:46:21 PM PDT 23
Peak memory 206132 kb
Host smart-cab4724c-1d6a-4acb-b018-9bc6c792ae1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248509206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4248509206
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/37.edn_genbits.2643905858
Short name T32
Test name
Test status
Simulation time 28091411 ps
CPU time 0.9 seconds
Started Oct 04 01:49:43 PM PDT 23
Finished Oct 04 01:49:44 PM PDT 23
Peak memory 204912 kb
Host smart-aed33320-4a16-40d8-b3d0-b6b9ae12ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643905858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2643905858
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_genbits.747965242
Short name T279
Test name
Test status
Simulation time 17707588 ps
CPU time 1.18 seconds
Started Oct 04 01:53:00 PM PDT 23
Finished Oct 04 01:53:02 PM PDT 23
Peak memory 205276 kb
Host smart-fad622c8-d753-4a84-a486-875900ecb834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747965242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.747965242
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.180697650
Short name T239
Test name
Test status
Simulation time 24799870 ps
CPU time 0.85 seconds
Started Oct 04 03:03:52 PM PDT 23
Finished Oct 04 03:03:53 PM PDT 23
Peak memory 205864 kb
Host smart-409b7faf-25af-4cd1-b586-e49eda444fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180697650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.180697650
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.edn_intr.3246794766
Short name T107
Test name
Test status
Simulation time 51195955 ps
CPU time 0.81 seconds
Started Oct 04 01:45:53 PM PDT 23
Finished Oct 04 01:45:55 PM PDT 23
Peak memory 214540 kb
Host smart-c1a98cc4-bde0-4a68-843d-3803b7698419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246794766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3246794766
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/1.edn_intr.2857117379
Short name T339
Test name
Test status
Simulation time 21078543 ps
CPU time 0.96 seconds
Started Oct 04 01:41:17 PM PDT 23
Finished Oct 04 01:41:19 PM PDT 23
Peak memory 214860 kb
Host smart-bcb099dc-25ad-4846-a9b0-380845204a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857117379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2857117379
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4260122827
Short name T621
Test name
Test status
Simulation time 90112079 ps
CPU time 1.08 seconds
Started Oct 04 01:53:58 PM PDT 23
Finished Oct 04 01:54:00 PM PDT 23
Peak memory 214780 kb
Host smart-17ea9441-fa79-474b-96e3-5f543999976a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260122827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4260122827
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.833181342
Short name T132
Test name
Test status
Simulation time 16622080 ps
CPU time 0.93 seconds
Started Oct 04 01:44:05 PM PDT 23
Finished Oct 04 01:44:07 PM PDT 23
Peak memory 214552 kb
Host smart-74217909-4583-4a9f-a6db-d9d761518ecc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833181342 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.833181342
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/29.edn_genbits.3834353337
Short name T123
Test name
Test status
Simulation time 26007574 ps
CPU time 1.24 seconds
Started Oct 04 01:53:57 PM PDT 23
Finished Oct 04 01:53:59 PM PDT 23
Peak memory 214420 kb
Host smart-e9f51975-1e96-4f1e-93e0-a53f5df82c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834353337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3834353337
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_genbits.2429743151
Short name T10
Test name
Test status
Simulation time 179559262 ps
CPU time 1.66 seconds
Started Oct 04 01:45:42 PM PDT 23
Finished Oct 04 01:45:44 PM PDT 23
Peak memory 214308 kb
Host smart-47c36b96-8e3f-4596-ae66-3757857c633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429743151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2429743151
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2338802537
Short name T213
Test name
Test status
Simulation time 180504778 ps
CPU time 4.74 seconds
Started Oct 04 03:00:22 PM PDT 23
Finished Oct 04 03:00:27 PM PDT 23
Peak memory 205732 kb
Host smart-088eb246-0662-445e-968f-6022a83015dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338802537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2338802537
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1593390136
Short name T196
Test name
Test status
Simulation time 27186508 ps
CPU time 0.88 seconds
Started Oct 04 03:00:22 PM PDT 23
Finished Oct 04 03:00:23 PM PDT 23
Peak memory 205812 kb
Host smart-77c9b94f-294f-4ad2-8d69-df6b3325a825
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593390136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1593390136
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3234362965
Short name T393
Test name
Test status
Simulation time 77191859 ps
CPU time 1.38 seconds
Started Oct 04 03:00:35 PM PDT 23
Finished Oct 04 03:00:37 PM PDT 23
Peak memory 214044 kb
Host smart-5925680b-a53c-4689-93b5-9d1467836107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234362965 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3234362965
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2177639119
Short name T421
Test name
Test status
Simulation time 45104006 ps
CPU time 0.86 seconds
Started Oct 04 03:03:48 PM PDT 23
Finished Oct 04 03:03:50 PM PDT 23
Peak memory 205816 kb
Host smart-4124e857-434b-4d9e-8b31-cd494b27ab28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177639119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2177639119
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3906609921
Short name T205
Test name
Test status
Simulation time 28924850 ps
CPU time 0.84 seconds
Started Oct 04 03:00:37 PM PDT 23
Finished Oct 04 03:00:38 PM PDT 23
Peak memory 205600 kb
Host smart-149f89db-bd89-4188-92d6-26f62b2483bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906609921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3906609921
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1720156709
Short name T408
Test name
Test status
Simulation time 94116949 ps
CPU time 1.09 seconds
Started Oct 04 03:00:49 PM PDT 23
Finished Oct 04 03:00:51 PM PDT 23
Peak memory 205928 kb
Host smart-7ca449bb-9ffc-419b-8801-02ce74ed8a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720156709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1720156709
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1296291203
Short name T382
Test name
Test status
Simulation time 41201196 ps
CPU time 1.57 seconds
Started Oct 04 03:00:56 PM PDT 23
Finished Oct 04 03:00:58 PM PDT 23
Peak memory 214040 kb
Host smart-ca2dc831-506e-4737-837b-3ef6d2e47ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296291203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1296291203
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3915273936
Short name T378
Test name
Test status
Simulation time 111364465 ps
CPU time 1.45 seconds
Started Oct 04 03:00:55 PM PDT 23
Finished Oct 04 03:00:56 PM PDT 23
Peak memory 205896 kb
Host smart-e28df683-b6f2-4784-a6be-ed0c278b1533
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915273936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3915273936
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3788404664
Short name T422
Test name
Test status
Simulation time 183171624 ps
CPU time 5.01 seconds
Started Oct 04 03:00:43 PM PDT 23
Finished Oct 04 03:00:49 PM PDT 23
Peak memory 205944 kb
Host smart-77231fe2-adf7-4f0e-b2cc-55580401421c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788404664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3788404664
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4135715017
Short name T229
Test name
Test status
Simulation time 32292449 ps
CPU time 0.87 seconds
Started Oct 04 03:01:22 PM PDT 23
Finished Oct 04 03:01:24 PM PDT 23
Peak memory 205832 kb
Host smart-e89d92c9-7695-4a9d-8dc5-2aa6998174be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135715017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4135715017
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.71467263
Short name T194
Test name
Test status
Simulation time 29653995 ps
CPU time 1.24 seconds
Started Oct 04 03:01:09 PM PDT 23
Finished Oct 04 03:01:11 PM PDT 23
Peak memory 214092 kb
Host smart-feddad28-ec10-4fe7-9cef-18eae77f1e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71467263 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.71467263
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.112736721
Short name T211
Test name
Test status
Simulation time 15375401 ps
CPU time 0.83 seconds
Started Oct 04 03:00:50 PM PDT 23
Finished Oct 04 03:00:51 PM PDT 23
Peak memory 205868 kb
Host smart-a41c0d16-9397-45f5-8f75-a7563f720a24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112736721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.112736721
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.4154897887
Short name T452
Test name
Test status
Simulation time 24463302 ps
CPU time 0.76 seconds
Started Oct 04 03:06:47 PM PDT 23
Finished Oct 04 03:06:49 PM PDT 23
Peak memory 205548 kb
Host smart-458852fb-ffce-4d1d-a624-80b2416cb25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154897887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4154897887
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1394021520
Short name T396
Test name
Test status
Simulation time 118396260 ps
CPU time 1.11 seconds
Started Oct 04 03:01:32 PM PDT 23
Finished Oct 04 03:01:33 PM PDT 23
Peak memory 205724 kb
Host smart-f5670eb7-b83b-4dc4-aa4b-c25ec99b1bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394021520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1394021520
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1145166442
Short name T417
Test name
Test status
Simulation time 82902134 ps
CPU time 3.02 seconds
Started Oct 04 03:03:52 PM PDT 23
Finished Oct 04 03:03:55 PM PDT 23
Peak memory 214272 kb
Host smart-9948fd56-def1-46ac-8911-5dacce216b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145166442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1145166442
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2650384007
Short name T434
Test name
Test status
Simulation time 95332373 ps
CPU time 1.85 seconds
Started Oct 04 03:00:54 PM PDT 23
Finished Oct 04 03:00:56 PM PDT 23
Peak memory 205868 kb
Host smart-45d21dc8-1af8-4dfc-b5b6-1c3d791a06dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650384007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2650384007
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.248629157
Short name T427
Test name
Test status
Simulation time 16893585 ps
CPU time 0.88 seconds
Started Oct 04 03:02:01 PM PDT 23
Finished Oct 04 03:02:03 PM PDT 23
Peak memory 205760 kb
Host smart-ea413fea-8d38-4db1-91ee-c0f6f1f955c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248629157 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.248629157
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3208042406
Short name T431
Test name
Test status
Simulation time 67823567 ps
CPU time 0.79 seconds
Started Oct 04 03:01:45 PM PDT 23
Finished Oct 04 03:01:46 PM PDT 23
Peak memory 205592 kb
Host smart-d7eaeadd-2c6a-4647-9240-8890922ee0c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208042406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3208042406
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.941113344
Short name T390
Test name
Test status
Simulation time 39783311 ps
CPU time 0.77 seconds
Started Oct 04 03:02:14 PM PDT 23
Finished Oct 04 03:02:17 PM PDT 23
Peak memory 205552 kb
Host smart-3f0cbbeb-c5b3-4778-82fd-84dc6d1fc245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941113344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.941113344
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4023261947
Short name T426
Test name
Test status
Simulation time 127850740 ps
CPU time 1.24 seconds
Started Oct 04 03:02:24 PM PDT 23
Finished Oct 04 03:02:26 PM PDT 23
Peak memory 205812 kb
Host smart-94b96177-0c18-4477-aa51-02c367b9173c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023261947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4023261947
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3224321295
Short name T192
Test name
Test status
Simulation time 1222101171 ps
CPU time 4.25 seconds
Started Oct 04 03:01:28 PM PDT 23
Finished Oct 04 03:01:32 PM PDT 23
Peak memory 213968 kb
Host smart-551f7edd-ff35-44c1-9123-9cecdf99ca95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224321295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3224321295
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3189903549
Short name T435
Test name
Test status
Simulation time 173499647 ps
CPU time 2.05 seconds
Started Oct 04 03:01:08 PM PDT 23
Finished Oct 04 03:01:10 PM PDT 23
Peak memory 205832 kb
Host smart-325b886f-fd03-472e-941e-27c59754c079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189903549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3189903549
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2374945739
Short name T415
Test name
Test status
Simulation time 23080418 ps
CPU time 1.18 seconds
Started Oct 04 03:04:55 PM PDT 23
Finished Oct 04 03:04:56 PM PDT 23
Peak memory 214100 kb
Host smart-a9a97c1d-a102-4e7b-89e6-ab5fafde7024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374945739 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2374945739
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3645519449
Short name T223
Test name
Test status
Simulation time 18836244 ps
CPU time 0.81 seconds
Started Oct 04 03:06:39 PM PDT 23
Finished Oct 04 03:06:40 PM PDT 23
Peak memory 205824 kb
Host smart-f4c2ebfa-4b75-4b43-ac38-c0fd8e3f039c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645519449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3645519449
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2327091526
Short name T449
Test name
Test status
Simulation time 18330958 ps
CPU time 0.78 seconds
Started Oct 04 03:13:13 PM PDT 23
Finished Oct 04 03:13:14 PM PDT 23
Peak memory 205568 kb
Host smart-ee830f83-d69d-4cbf-95f2-01d26d2860e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327091526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2327091526
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2117979446
Short name T349
Test name
Test status
Simulation time 537693490 ps
CPU time 2.53 seconds
Started Oct 04 03:01:18 PM PDT 23
Finished Oct 04 03:01:21 PM PDT 23
Peak memory 213996 kb
Host smart-ab876fe8-476f-47aa-843a-6cc0c955f32c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117979446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2117979446
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1255782360
Short name T283
Test name
Test status
Simulation time 272645449 ps
CPU time 1.48 seconds
Started Oct 04 03:02:14 PM PDT 23
Finished Oct 04 03:02:18 PM PDT 23
Peak memory 205788 kb
Host smart-2ce6a103-4a42-441a-ac0c-8c00405a76eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255782360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1255782360
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.337665630
Short name T373
Test name
Test status
Simulation time 100440735 ps
CPU time 1.3 seconds
Started Oct 04 03:02:17 PM PDT 23
Finished Oct 04 03:02:19 PM PDT 23
Peak memory 214076 kb
Host smart-cd286e57-87dd-4c6f-8589-11d1be163b48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337665630 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.337665630
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1755544901
Short name T219
Test name
Test status
Simulation time 10734551 ps
CPU time 0.84 seconds
Started Oct 04 03:05:26 PM PDT 23
Finished Oct 04 03:05:27 PM PDT 23
Peak memory 205656 kb
Host smart-f3b02c9f-c6d3-4e6b-a960-672703779bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755544901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1755544901
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1813313678
Short name T440
Test name
Test status
Simulation time 47723382 ps
CPU time 0.88 seconds
Started Oct 04 03:04:29 PM PDT 23
Finished Oct 04 03:04:30 PM PDT 23
Peak memory 205740 kb
Host smart-334b876c-9795-4344-b996-21b31b116d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813313678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1813313678
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2450833852
Short name T377
Test name
Test status
Simulation time 94411147 ps
CPU time 1.08 seconds
Started Oct 04 03:04:39 PM PDT 23
Finished Oct 04 03:04:40 PM PDT 23
Peak memory 205932 kb
Host smart-b8269d0e-e0e4-4952-8be1-6d833060f894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450833852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2450833852
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1834703835
Short name T392
Test name
Test status
Simulation time 59032191 ps
CPU time 2.08 seconds
Started Oct 04 03:00:23 PM PDT 23
Finished Oct 04 03:00:26 PM PDT 23
Peak memory 214100 kb
Host smart-5b0f2469-4a34-478f-ba59-e3f57e9fa260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834703835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1834703835
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3875966064
Short name T271
Test name
Test status
Simulation time 83773070 ps
CPU time 1.69 seconds
Started Oct 04 03:06:39 PM PDT 23
Finished Oct 04 03:06:41 PM PDT 23
Peak memory 205916 kb
Host smart-6e0b4095-93ea-40c0-afb0-730fe50af25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875966064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3875966064
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4203728743
Short name T451
Test name
Test status
Simulation time 91263900 ps
CPU time 1.26 seconds
Started Oct 04 03:08:06 PM PDT 23
Finished Oct 04 03:08:08 PM PDT 23
Peak memory 214196 kb
Host smart-537e9324-e957-489d-a195-1a961ba2c81b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203728743 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4203728743
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1130736910
Short name T221
Test name
Test status
Simulation time 56618500 ps
CPU time 0.93 seconds
Started Oct 04 03:04:50 PM PDT 23
Finished Oct 04 03:04:51 PM PDT 23
Peak memory 205868 kb
Host smart-b25d64f7-465d-4ab2-b9ea-94a68dacc045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130736910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1130736910
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4101180295
Short name T450
Test name
Test status
Simulation time 12351835 ps
CPU time 0.81 seconds
Started Oct 04 03:04:54 PM PDT 23
Finished Oct 04 03:04:55 PM PDT 23
Peak memory 205764 kb
Host smart-37072dc4-66a5-4f84-9399-d27e58b87312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101180295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4101180295
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3545678817
Short name T437
Test name
Test status
Simulation time 130730787 ps
CPU time 1.28 seconds
Started Oct 04 03:08:26 PM PDT 23
Finished Oct 04 03:08:28 PM PDT 23
Peak memory 205736 kb
Host smart-9f44026f-37e9-4799-a5ee-a16265eacc42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545678817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3545678817
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.927060935
Short name T370
Test name
Test status
Simulation time 36667522 ps
CPU time 1.84 seconds
Started Oct 04 03:07:15 PM PDT 23
Finished Oct 04 03:07:18 PM PDT 23
Peak memory 214192 kb
Host smart-752f91a3-acd0-4b99-9b98-60f46f242b45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927060935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.927060935
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1276175476
Short name T357
Test name
Test status
Simulation time 17133627 ps
CPU time 1.19 seconds
Started Oct 04 03:01:25 PM PDT 23
Finished Oct 04 03:01:27 PM PDT 23
Peak memory 214156 kb
Host smart-a0414de2-1e67-4e4c-8242-fc081b1c93e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276175476 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1276175476
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1022185724
Short name T242
Test name
Test status
Simulation time 43686396 ps
CPU time 0.82 seconds
Started Oct 04 03:04:30 PM PDT 23
Finished Oct 04 03:04:31 PM PDT 23
Peak memory 205724 kb
Host smart-57122093-e459-4073-9f79-85b405611769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022185724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1022185724
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.504666138
Short name T354
Test name
Test status
Simulation time 55462719 ps
CPU time 0.81 seconds
Started Oct 04 03:06:38 PM PDT 23
Finished Oct 04 03:06:40 PM PDT 23
Peak memory 205708 kb
Host smart-1ec21745-6e2a-4884-b91a-202fa583b9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504666138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.504666138
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1754133786
Short name T384
Test name
Test status
Simulation time 20786809 ps
CPU time 1.04 seconds
Started Oct 04 03:01:00 PM PDT 23
Finished Oct 04 03:01:01 PM PDT 23
Peak memory 205884 kb
Host smart-f12a7288-9a32-4bda-aaa3-92c0c106447f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754133786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1754133786
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2112472189
Short name T416
Test name
Test status
Simulation time 332040274 ps
CPU time 1.72 seconds
Started Oct 04 03:07:01 PM PDT 23
Finished Oct 04 03:07:04 PM PDT 23
Peak memory 213932 kb
Host smart-869baa9f-396f-4e6d-ba1b-b45ccc2019a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112472189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2112472189
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2492063595
Short name T284
Test name
Test status
Simulation time 114866617 ps
CPU time 1.44 seconds
Started Oct 04 03:08:40 PM PDT 23
Finished Oct 04 03:08:42 PM PDT 23
Peak memory 205844 kb
Host smart-b901b4a7-38ae-471a-ba10-07e38aa8d472
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492063595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2492063595
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1733744557
Short name T236
Test name
Test status
Simulation time 47206697 ps
CPU time 1.68 seconds
Started Oct 04 03:06:24 PM PDT 23
Finished Oct 04 03:06:26 PM PDT 23
Peak memory 214196 kb
Host smart-15cd80cd-d641-44ef-862f-5ecf18320462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733744557 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1733744557
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1773191533
Short name T444
Test name
Test status
Simulation time 43835195 ps
CPU time 0.8 seconds
Started Oct 04 03:02:11 PM PDT 23
Finished Oct 04 03:02:12 PM PDT 23
Peak memory 205644 kb
Host smart-d423110f-7b12-4d62-b890-8bd2c78aabb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773191533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1773191533
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2943433372
Short name T367
Test name
Test status
Simulation time 17283893 ps
CPU time 0.76 seconds
Started Oct 04 03:01:19 PM PDT 23
Finished Oct 04 03:01:20 PM PDT 23
Peak memory 205516 kb
Host smart-454e3ef1-5371-4901-90d6-b0ea69265dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943433372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2943433372
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4079858647
Short name T428
Test name
Test status
Simulation time 125368074 ps
CPU time 0.95 seconds
Started Oct 04 03:06:22 PM PDT 23
Finished Oct 04 03:06:24 PM PDT 23
Peak memory 205820 kb
Host smart-cbac0f2c-8620-44b4-9b3c-368f165ef536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079858647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4079858647
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1230456803
Short name T394
Test name
Test status
Simulation time 287043897 ps
CPU time 1.58 seconds
Started Oct 04 03:04:42 PM PDT 23
Finished Oct 04 03:04:44 PM PDT 23
Peak memory 214148 kb
Host smart-af89ed16-3030-40f6-8fed-cd6f935c9921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230456803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1230456803
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1057518287
Short name T195
Test name
Test status
Simulation time 182556223 ps
CPU time 1.55 seconds
Started Oct 04 03:06:14 PM PDT 23
Finished Oct 04 03:06:16 PM PDT 23
Peak memory 205764 kb
Host smart-29e12a3d-d223-4cab-8244-6213ccac5c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057518287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1057518287
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1894339504
Short name T351
Test name
Test status
Simulation time 26100780 ps
CPU time 1.22 seconds
Started Oct 04 03:02:21 PM PDT 23
Finished Oct 04 03:02:23 PM PDT 23
Peak memory 214148 kb
Host smart-d3b2b966-0e7c-4786-8b91-1c438c8b7123
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894339504 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1894339504
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1705947987
Short name T201
Test name
Test status
Simulation time 17690989 ps
CPU time 0.95 seconds
Started Oct 04 03:01:02 PM PDT 23
Finished Oct 04 03:01:03 PM PDT 23
Peak memory 205832 kb
Host smart-ca461ea9-1df5-4765-9855-3185187d3e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705947987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1705947987
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2059522094
Short name T405
Test name
Test status
Simulation time 13032172 ps
CPU time 0.82 seconds
Started Oct 04 03:03:44 PM PDT 23
Finished Oct 04 03:03:45 PM PDT 23
Peak memory 205604 kb
Host smart-f4a0493f-7f8a-4254-b3df-b7b017d1e7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059522094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2059522094
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2774292119
Short name T231
Test name
Test status
Simulation time 42750545 ps
CPU time 1.04 seconds
Started Oct 04 03:01:48 PM PDT 23
Finished Oct 04 03:01:50 PM PDT 23
Peak memory 205776 kb
Host smart-e9c33a18-a7b0-4b52-a3d1-9e6089ab96a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774292119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2774292119
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3126361186
Short name T419
Test name
Test status
Simulation time 65105565 ps
CPU time 1.49 seconds
Started Oct 04 03:06:43 PM PDT 23
Finished Oct 04 03:06:45 PM PDT 23
Peak memory 214008 kb
Host smart-290c168b-bf7f-41f0-b7bf-45e15ec50ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126361186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3126361186
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3970786789
Short name T217
Test name
Test status
Simulation time 108299839 ps
CPU time 1.62 seconds
Started Oct 04 03:00:44 PM PDT 23
Finished Oct 04 03:00:47 PM PDT 23
Peak memory 205812 kb
Host smart-dfb22bcb-e262-4b37-a852-a75d6209c12d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970786789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3970786789
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3203258901
Short name T433
Test name
Test status
Simulation time 28428371 ps
CPU time 1.41 seconds
Started Oct 04 03:02:03 PM PDT 23
Finished Oct 04 03:02:05 PM PDT 23
Peak memory 214156 kb
Host smart-62e34bd1-1fac-4335-b881-9fcc97df4478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203258901 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3203258901
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3036002283
Short name T379
Test name
Test status
Simulation time 26988441 ps
CPU time 0.89 seconds
Started Oct 04 03:01:56 PM PDT 23
Finished Oct 04 03:01:57 PM PDT 23
Peak memory 205736 kb
Host smart-b7135b97-f30a-4548-a762-fbeafb925a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036002283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3036002283
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1517608391
Short name T358
Test name
Test status
Simulation time 23500965 ps
CPU time 0.88 seconds
Started Oct 04 03:01:55 PM PDT 23
Finished Oct 04 03:01:56 PM PDT 23
Peak memory 205816 kb
Host smart-63ec3f30-fc50-43ca-8f0b-8441f84e4d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517608391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1517608391
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.4194259351
Short name T241
Test name
Test status
Simulation time 31415516 ps
CPU time 1.43 seconds
Started Oct 04 03:02:42 PM PDT 23
Finished Oct 04 03:02:44 PM PDT 23
Peak memory 205924 kb
Host smart-ffa40c62-2531-463c-b5c0-80cfeccdbd7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194259351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.4194259351
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1393552726
Short name T438
Test name
Test status
Simulation time 187746330 ps
CPU time 3.16 seconds
Started Oct 04 03:02:29 PM PDT 23
Finished Oct 04 03:02:33 PM PDT 23
Peak memory 213988 kb
Host smart-b1a2e22e-8ca5-44dd-9716-b7c4598b9245
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393552726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1393552726
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2193074463
Short name T389
Test name
Test status
Simulation time 291869069 ps
CPU time 1.43 seconds
Started Oct 04 03:02:08 PM PDT 23
Finished Oct 04 03:02:10 PM PDT 23
Peak memory 205860 kb
Host smart-23a42998-a601-491b-9dae-0ec571f5ddd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193074463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2193074463
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3677532241
Short name T225
Test name
Test status
Simulation time 39166641 ps
CPU time 1.36 seconds
Started Oct 04 03:02:08 PM PDT 23
Finished Oct 04 03:02:10 PM PDT 23
Peak memory 217016 kb
Host smart-f505b481-ce6f-4f4d-b5fb-b600276b875d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677532241 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3677532241
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2489277840
Short name T230
Test name
Test status
Simulation time 25075541 ps
CPU time 0.85 seconds
Started Oct 04 03:02:55 PM PDT 23
Finished Oct 04 03:02:56 PM PDT 23
Peak memory 205764 kb
Host smart-0490651c-7233-47d5-95f3-3e5d24d33b07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489277840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2489277840
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3401567029
Short name T409
Test name
Test status
Simulation time 23287772 ps
CPU time 0.82 seconds
Started Oct 04 03:01:03 PM PDT 23
Finished Oct 04 03:01:04 PM PDT 23
Peak memory 205788 kb
Host smart-e4c35eea-9550-4e3e-8549-4cb30c87f91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401567029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3401567029
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.213755494
Short name T198
Test name
Test status
Simulation time 34378056 ps
CPU time 1.32 seconds
Started Oct 04 03:01:07 PM PDT 23
Finished Oct 04 03:01:08 PM PDT 23
Peak memory 205960 kb
Host smart-0a6fef48-cad9-47b3-8842-3badedd70d19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213755494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.213755494
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.164332329
Short name T418
Test name
Test status
Simulation time 42271853 ps
CPU time 1.87 seconds
Started Oct 04 03:01:21 PM PDT 23
Finished Oct 04 03:01:23 PM PDT 23
Peak memory 214128 kb
Host smart-a6f806d5-e96b-4f7d-89f8-8d74cb4afc36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164332329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.164332329
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3926319756
Short name T376
Test name
Test status
Simulation time 40621945 ps
CPU time 1.46 seconds
Started Oct 04 03:02:31 PM PDT 23
Finished Oct 04 03:02:33 PM PDT 23
Peak memory 205892 kb
Host smart-d310e5ac-3540-458a-9988-cf04f9887d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926319756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3926319756
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.321416982
Short name T191
Test name
Test status
Simulation time 19303763 ps
CPU time 1.11 seconds
Started Oct 04 03:01:04 PM PDT 23
Finished Oct 04 03:01:05 PM PDT 23
Peak memory 214124 kb
Host smart-162f2acd-8af7-4fa2-8121-b65bdd8b3f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321416982 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.321416982
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.151798306
Short name T454
Test name
Test status
Simulation time 80424620 ps
CPU time 0.78 seconds
Started Oct 04 03:01:27 PM PDT 23
Finished Oct 04 03:01:28 PM PDT 23
Peak memory 205700 kb
Host smart-9dbe9021-1874-47d0-b858-af2a60cb41dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151798306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.151798306
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2443961444
Short name T352
Test name
Test status
Simulation time 39765373 ps
CPU time 0.79 seconds
Started Oct 04 03:01:45 PM PDT 23
Finished Oct 04 03:01:46 PM PDT 23
Peak memory 205544 kb
Host smart-e765fb4a-2718-4718-b026-13da7882dad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443961444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2443961444
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2409067510
Short name T243
Test name
Test status
Simulation time 39718213 ps
CPU time 0.83 seconds
Started Oct 04 03:01:42 PM PDT 23
Finished Oct 04 03:01:44 PM PDT 23
Peak memory 205668 kb
Host smart-518661f7-828e-4af1-b531-d0a3ed0a8a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409067510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2409067510
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2227241081
Short name T190
Test name
Test status
Simulation time 261914825 ps
CPU time 4.23 seconds
Started Oct 04 03:01:03 PM PDT 23
Finished Oct 04 03:01:08 PM PDT 23
Peak memory 214124 kb
Host smart-0518cd95-250e-4b8e-978b-7d7259d65185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227241081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2227241081
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3134123606
Short name T206
Test name
Test status
Simulation time 104220305 ps
CPU time 1.63 seconds
Started Oct 04 03:01:02 PM PDT 23
Finished Oct 04 03:01:04 PM PDT 23
Peak memory 205828 kb
Host smart-94922294-b99e-4bba-83f6-e3b45d58f45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134123606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3134123606
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2264994305
Short name T398
Test name
Test status
Simulation time 39053329 ps
CPU time 1.08 seconds
Started Oct 04 03:00:52 PM PDT 23
Finished Oct 04 03:00:54 PM PDT 23
Peak memory 205848 kb
Host smart-0dac36c6-fee8-49c9-830e-ea6a7ae3ef7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264994305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2264994305
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1010846388
Short name T202
Test name
Test status
Simulation time 268292476 ps
CPU time 5.87 seconds
Started Oct 04 03:01:28 PM PDT 23
Finished Oct 04 03:01:34 PM PDT 23
Peak memory 205828 kb
Host smart-b98c2bb8-4484-4628-8a92-c81fca47eb52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010846388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1010846388
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1283346573
Short name T375
Test name
Test status
Simulation time 27139494 ps
CPU time 0.88 seconds
Started Oct 04 03:00:51 PM PDT 23
Finished Oct 04 03:00:53 PM PDT 23
Peak memory 205676 kb
Host smart-14084b1e-5806-43d7-bb0a-f5d94b9d1af9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283346573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1283346573
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3808510085
Short name T383
Test name
Test status
Simulation time 277513601 ps
CPU time 1.02 seconds
Started Oct 04 03:00:52 PM PDT 23
Finished Oct 04 03:00:53 PM PDT 23
Peak memory 214052 kb
Host smart-b3160aaa-9afc-431c-aceb-1bd05b5dff8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808510085 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3808510085
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.166586309
Short name T244
Test name
Test status
Simulation time 17009477 ps
CPU time 0.79 seconds
Started Oct 04 03:00:43 PM PDT 23
Finished Oct 04 03:00:45 PM PDT 23
Peak memory 205676 kb
Host smart-60b9e3ae-df0b-4773-a167-fd48aab74a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166586309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.166586309
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1285685041
Short name T228
Test name
Test status
Simulation time 27117007 ps
CPU time 0.89 seconds
Started Oct 04 03:01:04 PM PDT 23
Finished Oct 04 03:01:05 PM PDT 23
Peak memory 205740 kb
Host smart-0ee6379c-9b25-4a50-a999-b035b3bd327b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285685041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1285685041
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.387195411
Short name T401
Test name
Test status
Simulation time 28526211 ps
CPU time 1.23 seconds
Started Oct 04 03:00:39 PM PDT 23
Finished Oct 04 03:00:41 PM PDT 23
Peak memory 205892 kb
Host smart-ec1fdad5-1db5-4845-a8db-c47c5b2e6b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387195411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.387195411
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1152355360
Short name T347
Test name
Test status
Simulation time 34110957 ps
CPU time 2.09 seconds
Started Oct 04 03:01:11 PM PDT 23
Finished Oct 04 03:01:14 PM PDT 23
Peak memory 213968 kb
Host smart-659b7103-5ff9-4a84-8a40-b2e79b95bd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152355360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1152355360
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.527967144
Short name T204
Test name
Test status
Simulation time 55011335 ps
CPU time 1.62 seconds
Started Oct 04 03:00:45 PM PDT 23
Finished Oct 04 03:00:47 PM PDT 23
Peak memory 205652 kb
Host smart-6a654158-7edb-447e-bf7c-c4a4f7513817
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527967144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.527967144
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.719491706
Short name T232
Test name
Test status
Simulation time 13108940 ps
CPU time 0.84 seconds
Started Oct 04 03:01:28 PM PDT 23
Finished Oct 04 03:01:29 PM PDT 23
Peak memory 205756 kb
Host smart-de2360da-4ee0-4063-8c08-954196943ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719491706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.719491706
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.21797592
Short name T216
Test name
Test status
Simulation time 28482711 ps
CPU time 0.84 seconds
Started Oct 04 03:02:14 PM PDT 23
Finished Oct 04 03:02:17 PM PDT 23
Peak memory 205776 kb
Host smart-80769231-e931-43e3-99d5-5beeee219320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.21797592
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.630967978
Short name T350
Test name
Test status
Simulation time 12109766 ps
CPU time 0.82 seconds
Started Oct 04 03:02:18 PM PDT 23
Finished Oct 04 03:02:19 PM PDT 23
Peak memory 205736 kb
Host smart-cc10a16b-9c32-47d4-82f0-71579df9d1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630967978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.630967978
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3088963079
Short name T360
Test name
Test status
Simulation time 16655218 ps
CPU time 0.74 seconds
Started Oct 04 03:02:27 PM PDT 23
Finished Oct 04 03:02:31 PM PDT 23
Peak memory 205496 kb
Host smart-3d27d6dc-adaa-46e2-bcc6-dae0bd1a384b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088963079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3088963079
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2766235330
Short name T400
Test name
Test status
Simulation time 15559088 ps
CPU time 0.77 seconds
Started Oct 04 03:01:41 PM PDT 23
Finished Oct 04 03:01:43 PM PDT 23
Peak memory 205528 kb
Host smart-151d8adc-7db9-48b1-9c24-b708653c5894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766235330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2766235330
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2659438593
Short name T397
Test name
Test status
Simulation time 23057200 ps
CPU time 0.82 seconds
Started Oct 04 03:02:12 PM PDT 23
Finished Oct 04 03:02:13 PM PDT 23
Peak memory 205744 kb
Host smart-9a21a362-8073-496c-bcbc-405534e09a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659438593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2659438593
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.438522407
Short name T403
Test name
Test status
Simulation time 16988153 ps
CPU time 0.88 seconds
Started Oct 04 03:02:29 PM PDT 23
Finished Oct 04 03:02:31 PM PDT 23
Peak memory 205612 kb
Host smart-32ffbafa-a643-4617-a2b3-a1d58b9c8516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438522407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.438522407
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2923791876
Short name T361
Test name
Test status
Simulation time 63087502 ps
CPU time 0.84 seconds
Started Oct 04 03:02:40 PM PDT 23
Finished Oct 04 03:02:41 PM PDT 23
Peak memory 205700 kb
Host smart-6515c85d-5d9d-4c69-b9cf-310cb31f8804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923791876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2923791876
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1349309084
Short name T356
Test name
Test status
Simulation time 18111187 ps
CPU time 0.86 seconds
Started Oct 04 03:01:56 PM PDT 23
Finished Oct 04 03:01:57 PM PDT 23
Peak memory 205660 kb
Host smart-be513e3b-f372-479f-ba47-3860e1e76997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349309084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1349309084
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2992281235
Short name T388
Test name
Test status
Simulation time 20304438 ps
CPU time 0.8 seconds
Started Oct 04 03:02:00 PM PDT 23
Finished Oct 04 03:02:01 PM PDT 23
Peak memory 205632 kb
Host smart-328967e7-a696-4072-998a-58bb699949a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992281235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2992281235
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1852318124
Short name T348
Test name
Test status
Simulation time 132508749 ps
CPU time 1.23 seconds
Started Oct 04 03:00:55 PM PDT 23
Finished Oct 04 03:00:57 PM PDT 23
Peak memory 205984 kb
Host smart-ba73caad-5279-43c6-a04e-3dd38918ba50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852318124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1852318124
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.668482911
Short name T237
Test name
Test status
Simulation time 94533056 ps
CPU time 2.91 seconds
Started Oct 04 03:01:33 PM PDT 23
Finished Oct 04 03:01:36 PM PDT 23
Peak memory 205936 kb
Host smart-d69e23b6-a65d-4cec-8831-2c3c88ffd3ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668482911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.668482911
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2933426455
Short name T402
Test name
Test status
Simulation time 20061176 ps
CPU time 0.98 seconds
Started Oct 04 03:00:44 PM PDT 23
Finished Oct 04 03:00:46 PM PDT 23
Peak memory 205760 kb
Host smart-161e04ef-9175-49b4-960c-74c1a0e56133
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933426455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2933426455
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4193978624
Short name T235
Test name
Test status
Simulation time 26337093 ps
CPU time 0.94 seconds
Started Oct 04 03:00:44 PM PDT 23
Finished Oct 04 03:00:46 PM PDT 23
Peak memory 205812 kb
Host smart-262a6694-322d-4f17-acb2-85c94708cdc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193978624 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4193978624
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2405388351
Short name T212
Test name
Test status
Simulation time 23179647 ps
CPU time 0.87 seconds
Started Oct 04 03:00:55 PM PDT 23
Finished Oct 04 03:00:56 PM PDT 23
Peak memory 205756 kb
Host smart-4abc278d-9837-4e24-8a3f-711f3f5fb698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405388351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2405388351
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3376369307
Short name T455
Test name
Test status
Simulation time 74258796 ps
CPU time 0.84 seconds
Started Oct 04 03:00:51 PM PDT 23
Finished Oct 04 03:00:53 PM PDT 23
Peak memory 205608 kb
Host smart-097e0d6b-cd4b-4ac5-9e6b-dc9053c65f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376369307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3376369307
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1991877494
Short name T423
Test name
Test status
Simulation time 15653952 ps
CPU time 0.9 seconds
Started Oct 04 03:01:23 PM PDT 23
Finished Oct 04 03:01:24 PM PDT 23
Peak memory 205812 kb
Host smart-290c8d97-1fdc-4039-b49d-64afc061c986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991877494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1991877494
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3451153320
Short name T411
Test name
Test status
Simulation time 212361036 ps
CPU time 2.09 seconds
Started Oct 04 03:01:10 PM PDT 23
Finished Oct 04 03:01:12 PM PDT 23
Peak memory 214032 kb
Host smart-d91b9e9c-334c-4322-ae67-967eca4ec0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451153320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3451153320
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1730748920
Short name T412
Test name
Test status
Simulation time 48554112 ps
CPU time 1.6 seconds
Started Oct 04 03:01:21 PM PDT 23
Finished Oct 04 03:01:23 PM PDT 23
Peak memory 205844 kb
Host smart-154f8724-b206-44ee-939a-64be8b6e1b03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730748920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1730748920
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1816504060
Short name T404
Test name
Test status
Simulation time 20440382 ps
CPU time 0.81 seconds
Started Oct 04 03:01:30 PM PDT 23
Finished Oct 04 03:01:31 PM PDT 23
Peak memory 205496 kb
Host smart-4c1b11fc-2088-4a6b-bf3b-754274ab3551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816504060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1816504060
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2563769116
Short name T353
Test name
Test status
Simulation time 14703986 ps
CPU time 0.84 seconds
Started Oct 04 03:01:47 PM PDT 23
Finished Oct 04 03:01:48 PM PDT 23
Peak memory 205696 kb
Host smart-68602490-346a-45bc-9ff9-838d11266015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563769116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2563769116
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2106292308
Short name T215
Test name
Test status
Simulation time 18034947 ps
CPU time 0.93 seconds
Started Oct 04 03:02:08 PM PDT 23
Finished Oct 04 03:02:10 PM PDT 23
Peak memory 205604 kb
Host smart-3dbad7ce-e1f0-44f4-a00b-5c716f14c0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106292308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2106292308
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2593603314
Short name T407
Test name
Test status
Simulation time 32421665 ps
CPU time 0.75 seconds
Started Oct 04 03:02:34 PM PDT 23
Finished Oct 04 03:02:36 PM PDT 23
Peak memory 205520 kb
Host smart-e184fcb1-fc63-4623-86ed-ebd560bf79e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593603314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2593603314
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2776892812
Short name T447
Test name
Test status
Simulation time 84225193 ps
CPU time 0.78 seconds
Started Oct 04 03:02:37 PM PDT 23
Finished Oct 04 03:02:38 PM PDT 23
Peak memory 205568 kb
Host smart-f4a4b507-041c-4187-b6df-ed62f5e6149d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776892812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2776892812
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3208867411
Short name T445
Test name
Test status
Simulation time 35154453 ps
CPU time 0.75 seconds
Started Oct 04 03:01:49 PM PDT 23
Finished Oct 04 03:01:50 PM PDT 23
Peak memory 205484 kb
Host smart-908406d5-68cb-4bdd-ab6c-3276b6b50bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208867411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3208867411
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3958079356
Short name T448
Test name
Test status
Simulation time 114911951 ps
CPU time 0.77 seconds
Started Oct 04 03:02:13 PM PDT 23
Finished Oct 04 03:02:14 PM PDT 23
Peak memory 205572 kb
Host smart-b9d9acf4-3427-4e3f-b924-8f4b82bac4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958079356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3958079356
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2218922586
Short name T420
Test name
Test status
Simulation time 22792424 ps
CPU time 0.82 seconds
Started Oct 04 03:02:39 PM PDT 23
Finished Oct 04 03:02:40 PM PDT 23
Peak memory 205796 kb
Host smart-6ca604e6-cb6d-489c-8f1c-db1c94b22c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218922586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2218922586
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1700984198
Short name T414
Test name
Test status
Simulation time 46693089 ps
CPU time 0.86 seconds
Started Oct 04 03:02:07 PM PDT 23
Finished Oct 04 03:02:08 PM PDT 23
Peak memory 205764 kb
Host smart-c83e5279-01d6-4a8c-b899-6b21fffb0e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700984198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1700984198
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2186453910
Short name T233
Test name
Test status
Simulation time 24832328 ps
CPU time 0.89 seconds
Started Oct 04 03:01:24 PM PDT 23
Finished Oct 04 03:01:26 PM PDT 23
Peak memory 205656 kb
Host smart-9db4a984-8180-420a-b6c1-0b8e2507dd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186453910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2186453910
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1361190720
Short name T222
Test name
Test status
Simulation time 14117654 ps
CPU time 0.98 seconds
Started Oct 04 03:00:23 PM PDT 23
Finished Oct 04 03:00:25 PM PDT 23
Peak memory 205816 kb
Host smart-630668e9-c717-4628-8057-da367e92924d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361190720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1361190720
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3488164294
Short name T203
Test name
Test status
Simulation time 207550520 ps
CPU time 3.41 seconds
Started Oct 04 03:01:22 PM PDT 23
Finished Oct 04 03:01:26 PM PDT 23
Peak memory 205740 kb
Host smart-574d81ca-7b08-45d0-92b2-23ca5295df78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488164294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3488164294
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3957147467
Short name T443
Test name
Test status
Simulation time 104585060 ps
CPU time 0.85 seconds
Started Oct 04 03:01:19 PM PDT 23
Finished Oct 04 03:01:20 PM PDT 23
Peak memory 205880 kb
Host smart-24aa810d-00bc-4380-8446-ab0441d50cc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957147467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3957147467
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3202499330
Short name T432
Test name
Test status
Simulation time 16625037 ps
CPU time 0.95 seconds
Started Oct 04 03:00:50 PM PDT 23
Finished Oct 04 03:00:51 PM PDT 23
Peak memory 205920 kb
Host smart-54dded40-4185-4c5b-b872-fb57250914e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202499330 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3202499330
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3956963414
Short name T355
Test name
Test status
Simulation time 25109797 ps
CPU time 0.87 seconds
Started Oct 04 03:00:21 PM PDT 23
Finished Oct 04 03:00:22 PM PDT 23
Peak memory 205832 kb
Host smart-ea44cff6-f242-4e24-b740-c67482bf98e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956963414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3956963414
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1279808090
Short name T365
Test name
Test status
Simulation time 28356250 ps
CPU time 0.83 seconds
Started Oct 04 03:01:40 PM PDT 23
Finished Oct 04 03:01:41 PM PDT 23
Peak memory 205628 kb
Host smart-9ce61155-2025-4e4d-81d2-5fc6890a6259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279808090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1279808090
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1937986279
Short name T193
Test name
Test status
Simulation time 70973867 ps
CPU time 1.36 seconds
Started Oct 04 03:01:57 PM PDT 23
Finished Oct 04 03:01:58 PM PDT 23
Peak memory 205764 kb
Host smart-cbd0697d-d1cd-40e6-b916-af51286cda09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937986279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1937986279
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4221461299
Short name T395
Test name
Test status
Simulation time 44243533 ps
CPU time 1.98 seconds
Started Oct 04 03:01:18 PM PDT 23
Finished Oct 04 03:01:21 PM PDT 23
Peak memory 214076 kb
Host smart-45c7b90e-0d46-427b-a6ab-88b598dbb9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221461299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4221461299
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4184663332
Short name T453
Test name
Test status
Simulation time 67165581 ps
CPU time 1.56 seconds
Started Oct 04 03:00:50 PM PDT 23
Finished Oct 04 03:00:52 PM PDT 23
Peak memory 205852 kb
Host smart-ecbaff11-e699-4756-9cd3-2bed91cd3130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184663332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4184663332
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3513884076
Short name T363
Test name
Test status
Simulation time 26720276 ps
CPU time 0.77 seconds
Started Oct 04 03:02:01 PM PDT 23
Finished Oct 04 03:02:02 PM PDT 23
Peak memory 205708 kb
Host smart-2ed53af9-b5ca-4d91-a3f5-c694314d5690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513884076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3513884076
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2907571385
Short name T385
Test name
Test status
Simulation time 13002024 ps
CPU time 0.8 seconds
Started Oct 04 03:01:50 PM PDT 23
Finished Oct 04 03:01:52 PM PDT 23
Peak memory 205556 kb
Host smart-7996eaa2-55bf-4885-a035-a82916463782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907571385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2907571385
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1545003018
Short name T371
Test name
Test status
Simulation time 16534115 ps
CPU time 0.87 seconds
Started Oct 04 03:02:00 PM PDT 23
Finished Oct 04 03:02:02 PM PDT 23
Peak memory 205748 kb
Host smart-02408d86-d407-4977-9e60-88d51549b5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545003018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1545003018
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.882513402
Short name T364
Test name
Test status
Simulation time 13598099 ps
CPU time 0.84 seconds
Started Oct 04 03:02:08 PM PDT 23
Finished Oct 04 03:02:09 PM PDT 23
Peak memory 205672 kb
Host smart-5128e792-414a-476d-aa38-0d30a4067120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882513402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.882513402
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3249819196
Short name T372
Test name
Test status
Simulation time 13366334 ps
CPU time 0.86 seconds
Started Oct 04 03:02:05 PM PDT 23
Finished Oct 04 03:02:07 PM PDT 23
Peak memory 205524 kb
Host smart-366c0c71-d3d6-414e-a3ff-038e4930ba3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249819196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3249819196
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.693907764
Short name T399
Test name
Test status
Simulation time 19706224 ps
CPU time 0.78 seconds
Started Oct 04 03:02:26 PM PDT 23
Finished Oct 04 03:02:27 PM PDT 23
Peak memory 205616 kb
Host smart-ced669f8-7d9c-4461-8f30-d4eb1d662b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693907764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.693907764
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3122447713
Short name T425
Test name
Test status
Simulation time 25202165 ps
CPU time 0.82 seconds
Started Oct 04 03:02:31 PM PDT 23
Finished Oct 04 03:02:32 PM PDT 23
Peak memory 205660 kb
Host smart-a131eaa6-29e1-46d6-b4cd-54d568d36f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122447713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3122447713
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1214793065
Short name T424
Test name
Test status
Simulation time 19380179 ps
CPU time 0.86 seconds
Started Oct 04 03:01:43 PM PDT 23
Finished Oct 04 03:01:44 PM PDT 23
Peak memory 205584 kb
Host smart-0b58d15b-7fd2-4be1-b8d1-7320b8ab48d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214793065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1214793065
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3771983396
Short name T238
Test name
Test status
Simulation time 18549244 ps
CPU time 0.87 seconds
Started Oct 04 03:01:33 PM PDT 23
Finished Oct 04 03:01:34 PM PDT 23
Peak memory 205608 kb
Host smart-95043dfd-5b48-4da2-82fe-027bc14af913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771983396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3771983396
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2434141987
Short name T406
Test name
Test status
Simulation time 22191476 ps
CPU time 0.84 seconds
Started Oct 04 03:02:34 PM PDT 23
Finished Oct 04 03:02:35 PM PDT 23
Peak memory 205820 kb
Host smart-483b66f3-4789-4e4c-ae07-4d277634bc21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434141987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2434141987
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.36318740
Short name T374
Test name
Test status
Simulation time 80398226 ps
CPU time 2.01 seconds
Started Oct 04 03:01:39 PM PDT 23
Finished Oct 04 03:01:41 PM PDT 23
Peak memory 213996 kb
Host smart-17b861de-8ccc-4171-8d8c-18de1740b14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318740 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.36318740
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1948889412
Short name T226
Test name
Test status
Simulation time 90691518 ps
CPU time 0.81 seconds
Started Oct 04 03:00:40 PM PDT 23
Finished Oct 04 03:00:41 PM PDT 23
Peak memory 205672 kb
Host smart-e22a91e9-e316-496f-b6eb-0483fab3f539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948889412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1948889412
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1263215448
Short name T362
Test name
Test status
Simulation time 12305125 ps
CPU time 0.79 seconds
Started Oct 04 03:01:15 PM PDT 23
Finished Oct 04 03:01:17 PM PDT 23
Peak memory 205384 kb
Host smart-5b10e6bb-ad44-4177-b62e-8d406ab58f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263215448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1263215448
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.472548897
Short name T240
Test name
Test status
Simulation time 23309747 ps
CPU time 1.03 seconds
Started Oct 04 03:01:25 PM PDT 23
Finished Oct 04 03:01:26 PM PDT 23
Peak memory 205776 kb
Host smart-749e2277-e766-4ba0-a941-6c181f2e62a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472548897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.472548897
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3763159767
Short name T359
Test name
Test status
Simulation time 47706351 ps
CPU time 1.64 seconds
Started Oct 04 03:00:52 PM PDT 23
Finished Oct 04 03:00:54 PM PDT 23
Peak memory 213988 kb
Host smart-7c11a485-2fb4-4cab-846e-62817d161d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763159767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3763159767
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1104730439
Short name T446
Test name
Test status
Simulation time 69183960 ps
CPU time 2.07 seconds
Started Oct 04 03:02:00 PM PDT 23
Finished Oct 04 03:02:03 PM PDT 23
Peak memory 205800 kb
Host smart-40d7e77d-c8a3-41d3-87c0-303edc8456ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104730439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1104730439
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1522485087
Short name T441
Test name
Test status
Simulation time 69576204 ps
CPU time 1.1 seconds
Started Oct 04 03:00:57 PM PDT 23
Finished Oct 04 03:00:58 PM PDT 23
Peak memory 213996 kb
Host smart-242b0cab-0701-4153-bffa-d6290bf3c3cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522485087 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1522485087
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2349576997
Short name T220
Test name
Test status
Simulation time 32336766 ps
CPU time 0.86 seconds
Started Oct 04 03:01:38 PM PDT 23
Finished Oct 04 03:01:40 PM PDT 23
Peak memory 205672 kb
Host smart-044bf465-ca87-4e6d-9e24-7ccafc5d8b22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349576997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2349576997
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3323736061
Short name T366
Test name
Test status
Simulation time 27125972 ps
CPU time 0.85 seconds
Started Oct 04 03:01:08 PM PDT 23
Finished Oct 04 03:01:09 PM PDT 23
Peak memory 205704 kb
Host smart-84b939dd-10bc-4e15-83e7-527141e6884c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323736061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3323736061
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.949691338
Short name T189
Test name
Test status
Simulation time 103481963 ps
CPU time 1.06 seconds
Started Oct 04 03:00:25 PM PDT 23
Finished Oct 04 03:00:28 PM PDT 23
Peak memory 205836 kb
Host smart-2ed8da08-0f29-4c2e-a81f-874f4079aea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949691338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.949691338
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.4090003608
Short name T429
Test name
Test status
Simulation time 176279982 ps
CPU time 3.1 seconds
Started Oct 04 03:01:12 PM PDT 23
Finished Oct 04 03:01:16 PM PDT 23
Peak memory 213988 kb
Host smart-7f187f13-8d77-4f06-b867-ed1284530fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090003608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.4090003608
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1117566903
Short name T436
Test name
Test status
Simulation time 174785880 ps
CPU time 1.47 seconds
Started Oct 04 03:02:16 PM PDT 23
Finished Oct 04 03:02:18 PM PDT 23
Peak memory 205684 kb
Host smart-f05b6197-1da1-4329-89ac-6559ee149ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117566903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1117566903
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1711719753
Short name T381
Test name
Test status
Simulation time 38478844 ps
CPU time 1.13 seconds
Started Oct 04 03:01:39 PM PDT 23
Finished Oct 04 03:01:41 PM PDT 23
Peak memory 213924 kb
Host smart-a525c5bd-d107-4fd9-9116-81e67dc6f4cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711719753 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1711719753
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3851503330
Short name T224
Test name
Test status
Simulation time 13828740 ps
CPU time 0.82 seconds
Started Oct 04 03:05:23 PM PDT 23
Finished Oct 04 03:05:25 PM PDT 23
Peak memory 205432 kb
Host smart-97dab780-73da-4b0e-997a-e64eb91fca1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851503330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3851503330
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.9130581
Short name T442
Test name
Test status
Simulation time 18260335 ps
CPU time 0.79 seconds
Started Oct 04 03:02:11 PM PDT 23
Finished Oct 04 03:02:12 PM PDT 23
Peak memory 205648 kb
Host smart-a53e1d07-9656-4a7f-b527-1b6366a84958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9130581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.9130581
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1560839519
Short name T413
Test name
Test status
Simulation time 27387775 ps
CPU time 1.02 seconds
Started Oct 04 03:01:38 PM PDT 23
Finished Oct 04 03:01:40 PM PDT 23
Peak memory 205660 kb
Host smart-6eee1906-d2a5-44fc-be36-4dc33947b350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560839519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1560839519
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2476127831
Short name T391
Test name
Test status
Simulation time 95254176 ps
CPU time 3.47 seconds
Started Oct 04 03:00:44 PM PDT 23
Finished Oct 04 03:00:48 PM PDT 23
Peak memory 217080 kb
Host smart-055f0189-b0d9-4717-b5df-fd3c89c1b147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476127831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2476127831
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1708278203
Short name T282
Test name
Test status
Simulation time 89728311 ps
CPU time 2.35 seconds
Started Oct 04 03:02:20 PM PDT 23
Finished Oct 04 03:02:23 PM PDT 23
Peak memory 205892 kb
Host smart-0e699f3e-c3ad-4e27-a76c-a8de2edf1d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708278203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1708278203
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1490056005
Short name T386
Test name
Test status
Simulation time 13895337 ps
CPU time 1.01 seconds
Started Oct 04 03:07:29 PM PDT 23
Finished Oct 04 03:07:30 PM PDT 23
Peak memory 205924 kb
Host smart-0026022b-feb9-4b2d-92a2-d3c4eff43095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490056005 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1490056005
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2024469143
Short name T387
Test name
Test status
Simulation time 13122203 ps
CPU time 0.86 seconds
Started Oct 04 03:04:42 PM PDT 23
Finished Oct 04 03:04:44 PM PDT 23
Peak memory 205844 kb
Host smart-2018711e-0695-42af-806a-b41b8199b1a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024469143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2024469143
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3872719453
Short name T234
Test name
Test status
Simulation time 13921141 ps
CPU time 0.86 seconds
Started Oct 04 03:06:46 PM PDT 23
Finished Oct 04 03:06:48 PM PDT 23
Peak memory 205728 kb
Host smart-0eb5a569-bb7e-4fad-99ec-533cf8b3e197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872719453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3872719453
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.651998959
Short name T227
Test name
Test status
Simulation time 18516905 ps
CPU time 0.96 seconds
Started Oct 04 03:01:05 PM PDT 23
Finished Oct 04 03:01:06 PM PDT 23
Peak memory 205848 kb
Host smart-c725a434-5dd6-4f17-a21a-a77ddb996603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651998959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.651998959
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.364561626
Short name T439
Test name
Test status
Simulation time 474272319 ps
CPU time 2.64 seconds
Started Oct 04 03:02:13 PM PDT 23
Finished Oct 04 03:02:16 PM PDT 23
Peak memory 213992 kb
Host smart-b70e298d-cf39-42ae-9faa-5709a18e043d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364561626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.364561626
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2717501839
Short name T380
Test name
Test status
Simulation time 334819087 ps
CPU time 2.44 seconds
Started Oct 04 03:07:28 PM PDT 23
Finished Oct 04 03:07:31 PM PDT 23
Peak memory 205840 kb
Host smart-5c4e7a15-e01c-4568-8f3d-b6b18adc0008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717501839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2717501839
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2591566116
Short name T430
Test name
Test status
Simulation time 46337953 ps
CPU time 1.49 seconds
Started Oct 04 03:01:16 PM PDT 23
Finished Oct 04 03:01:18 PM PDT 23
Peak memory 214000 kb
Host smart-ad71137b-6b9b-4208-82a9-16510c3c348f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591566116 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2591566116
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2560044467
Short name T368
Test name
Test status
Simulation time 14900230 ps
CPU time 0.95 seconds
Started Oct 04 03:01:04 PM PDT 23
Finished Oct 04 03:01:05 PM PDT 23
Peak memory 205756 kb
Host smart-756767cc-0403-43f7-80e8-424200629f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560044467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2560044467
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4291314731
Short name T369
Test name
Test status
Simulation time 51622042 ps
CPU time 0.86 seconds
Started Oct 04 03:08:45 PM PDT 23
Finished Oct 04 03:08:46 PM PDT 23
Peak memory 205712 kb
Host smart-29c48b40-0175-43cf-860e-a2ce6b4ef486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291314731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4291314731
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2632075740
Short name T410
Test name
Test status
Simulation time 13795503 ps
CPU time 0.95 seconds
Started Oct 04 03:02:10 PM PDT 23
Finished Oct 04 03:02:11 PM PDT 23
Peak memory 205696 kb
Host smart-0b19cce7-6c5f-4781-9a75-9ba067e695ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632075740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2632075740
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3276022668
Short name T218
Test name
Test status
Simulation time 132555412 ps
CPU time 2.37 seconds
Started Oct 04 03:06:22 PM PDT 23
Finished Oct 04 03:06:25 PM PDT 23
Peak memory 214032 kb
Host smart-16dc6efc-fc60-4301-959c-9bed185c9681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276022668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3276022668
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1164147405
Short name T214
Test name
Test status
Simulation time 54638656 ps
CPU time 1.64 seconds
Started Oct 04 03:07:25 PM PDT 23
Finished Oct 04 03:07:27 PM PDT 23
Peak memory 205844 kb
Host smart-20661034-daba-4d5b-b5a8-6d537eb699f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164147405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1164147405
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2870292248
Short name T623
Test name
Test status
Simulation time 51042073 ps
CPU time 1.05 seconds
Started Oct 04 01:49:08 PM PDT 23
Finished Oct 04 01:49:10 PM PDT 23
Peak memory 205228 kb
Host smart-627d5463-31f3-4d9b-8e3d-9cdfb4e4e851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870292248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2870292248
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.3662067682
Short name T165
Test name
Test status
Simulation time 19352747 ps
CPU time 0.99 seconds
Started Oct 04 01:42:55 PM PDT 23
Finished Oct 04 01:42:56 PM PDT 23
Peak memory 215700 kb
Host smart-3a31ae46-2014-47c0-b608-9ebe02e621f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662067682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3662067682
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3341677938
Short name T39
Test name
Test status
Simulation time 71440977 ps
CPU time 1.1 seconds
Started Oct 04 01:52:43 PM PDT 23
Finished Oct 04 01:52:46 PM PDT 23
Peak memory 205232 kb
Host smart-f13507d1-d152-44e6-beaf-930c448d31b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341677938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3341677938
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1620766269
Short name T469
Test name
Test status
Simulation time 18363332 ps
CPU time 1.07 seconds
Started Oct 04 01:52:29 PM PDT 23
Finished Oct 04 01:52:31 PM PDT 23
Peak memory 214592 kb
Host smart-d189553a-9ab9-4946-a76a-00acff4273fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620766269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1620766269
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3096882834
Short name T19
Test name
Test status
Simulation time 2363350234 ps
CPU time 6.78 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 233324 kb
Host smart-127092ec-94a5-48c1-8d37-4c35252f5bfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096882834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3096882834
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3728068648
Short name T72
Test name
Test status
Simulation time 26441829 ps
CPU time 0.9 seconds
Started Oct 04 01:52:27 PM PDT 23
Finished Oct 04 01:52:28 PM PDT 23
Peak memory 205096 kb
Host smart-8486de95-44b0-4d0b-8570-e5119abb5bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728068648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3728068648
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.342742390
Short name T587
Test name
Test status
Simulation time 535942486 ps
CPU time 3.71 seconds
Started Oct 04 01:50:48 PM PDT 23
Finished Oct 04 01:50:52 PM PDT 23
Peak memory 206136 kb
Host smart-5643c8ea-fcd8-48b6-b12f-71bf43a9eb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342742390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.342742390
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2845882737
Short name T181
Test name
Test status
Simulation time 113937751966 ps
CPU time 735.87 seconds
Started Oct 04 01:51:15 PM PDT 23
Finished Oct 04 02:03:32 PM PDT 23
Peak memory 215040 kb
Host smart-96603a3e-a291-472f-8b8d-f028cb375870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845882737 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2845882737
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.510636024
Short name T528
Test name
Test status
Simulation time 36925666 ps
CPU time 0.81 seconds
Started Oct 04 01:50:55 PM PDT 23
Finished Oct 04 01:50:56 PM PDT 23
Peak memory 204276 kb
Host smart-ab38b1fb-c3de-4cf0-b104-48fd8c67827d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510636024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.510636024
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1141482387
Short name T256
Test name
Test status
Simulation time 48781984 ps
CPU time 0.83 seconds
Started Oct 04 01:52:16 PM PDT 23
Finished Oct 04 01:52:17 PM PDT 23
Peak memory 214536 kb
Host smart-a7614d04-c337-4d19-affa-be8ead1441e1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141482387 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1141482387
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1637755180
Short name T84
Test name
Test status
Simulation time 48214552 ps
CPU time 1.05 seconds
Started Oct 04 01:43:21 PM PDT 23
Finished Oct 04 01:43:22 PM PDT 23
Peak memory 214624 kb
Host smart-f9c0a68b-2633-4468-aeea-f050f6190769
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637755180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1637755180
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2822832224
Short name T5
Test name
Test status
Simulation time 20217150 ps
CPU time 1.03 seconds
Started Oct 04 01:41:27 PM PDT 23
Finished Oct 04 01:41:29 PM PDT 23
Peak memory 214500 kb
Host smart-342b350d-e263-4dbe-b050-959a1d81fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822832224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2822832224
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1426478906
Short name T290
Test name
Test status
Simulation time 20636444 ps
CPU time 1 seconds
Started Oct 04 01:41:15 PM PDT 23
Finished Oct 04 01:41:17 PM PDT 23
Peak memory 205032 kb
Host smart-fb0fe568-40a5-43bf-bc5c-c7b5e7e2a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426478906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1426478906
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_smoke.2067962090
Short name T475
Test name
Test status
Simulation time 13212591 ps
CPU time 0.89 seconds
Started Oct 04 01:42:30 PM PDT 23
Finished Oct 04 01:42:32 PM PDT 23
Peak memory 204984 kb
Host smart-9036b5fb-c040-440c-aaf2-d97f4a014076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067962090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2067962090
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.931209191
Short name T549
Test name
Test status
Simulation time 165013367 ps
CPU time 3.19 seconds
Started Oct 04 01:42:38 PM PDT 23
Finished Oct 04 01:42:42 PM PDT 23
Peak memory 206068 kb
Host smart-260e997d-0c05-4899-b3c6-f9f96968eacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931209191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.931209191
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1062164472
Short name T333
Test name
Test status
Simulation time 522592209037 ps
CPU time 3047.7 seconds
Started Oct 04 01:42:40 PM PDT 23
Finished Oct 04 02:33:28 PM PDT 23
Peak memory 229872 kb
Host smart-08520c55-4796-47d5-98f1-2505ee88c678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062164472 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1062164472
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1133400792
Short name T709
Test name
Test status
Simulation time 21078046 ps
CPU time 1.01 seconds
Started Oct 04 01:51:52 PM PDT 23
Finished Oct 04 01:51:54 PM PDT 23
Peak memory 205336 kb
Host smart-7facf2d9-3154-455a-b35c-3033706d856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133400792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1133400792
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.90893263
Short name T88
Test name
Test status
Simulation time 18247880 ps
CPU time 0.82 seconds
Started Oct 04 01:42:41 PM PDT 23
Finished Oct 04 01:42:44 PM PDT 23
Peak memory 214480 kb
Host smart-17fdb931-65bd-481b-be04-ab2681ee9dd4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90893263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.90893263
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3058364924
Short name T684
Test name
Test status
Simulation time 42238049 ps
CPU time 1.05 seconds
Started Oct 04 02:14:08 PM PDT 23
Finished Oct 04 02:14:09 PM PDT 23
Peak memory 214684 kb
Host smart-b14c5ee9-acea-4e48-9a86-af1f1bd6d914
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058364924 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3058364924
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1231871404
Short name T633
Test name
Test status
Simulation time 29133307 ps
CPU time 0.87 seconds
Started Oct 04 01:45:26 PM PDT 23
Finished Oct 04 01:45:28 PM PDT 23
Peak memory 215680 kb
Host smart-1b2b0aed-606d-458a-b018-1237375f546b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231871404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1231871404
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3578236466
Short name T289
Test name
Test status
Simulation time 33385232 ps
CPU time 1.04 seconds
Started Oct 04 01:54:27 PM PDT 23
Finished Oct 04 01:54:29 PM PDT 23
Peak memory 205288 kb
Host smart-4da773f3-1be5-49be-8163-16101fd2d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578236466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3578236466
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1385573145
Short name T627
Test name
Test status
Simulation time 23433987 ps
CPU time 0.86 seconds
Started Oct 04 01:45:35 PM PDT 23
Finished Oct 04 01:45:36 PM PDT 23
Peak memory 214508 kb
Host smart-27f15e64-4ae7-473f-b782-c1b680e51b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385573145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1385573145
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1928625317
Short name T653
Test name
Test status
Simulation time 12338224 ps
CPU time 0.85 seconds
Started Oct 04 01:48:07 PM PDT 23
Finished Oct 04 01:48:09 PM PDT 23
Peak memory 203504 kb
Host smart-095264b0-235a-416b-bd14-d4589af94b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928625317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1928625317
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.957911061
Short name T489
Test name
Test status
Simulation time 278965372 ps
CPU time 3.29 seconds
Started Oct 04 01:43:15 PM PDT 23
Finished Oct 04 01:43:19 PM PDT 23
Peak memory 205616 kb
Host smart-b4ce2bba-f447-4650-a6a0-2a55ca6387e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957911061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.957911061
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3598384651
Short name T539
Test name
Test status
Simulation time 97249219832 ps
CPU time 1091.97 seconds
Started Oct 04 01:42:59 PM PDT 23
Finished Oct 04 02:01:11 PM PDT 23
Peak memory 215900 kb
Host smart-9802a0ff-d9f7-43ea-b744-dc7c509a15e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598384651 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3598384651
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.3334802725
Short name T567
Test name
Test status
Simulation time 53472679 ps
CPU time 0.91 seconds
Started Oct 04 01:49:49 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 205192 kb
Host smart-f7f39254-05c3-45c1-8ba3-324adf25c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334802725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3334802725
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3402170316
Short name T474
Test name
Test status
Simulation time 13167840 ps
CPU time 0.87 seconds
Started Oct 04 01:50:19 PM PDT 23
Finished Oct 04 01:50:21 PM PDT 23
Peak memory 204616 kb
Host smart-c1c19980-5cf5-4207-a048-02585489c215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402170316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3402170316
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1848913375
Short name T631
Test name
Test status
Simulation time 53543462 ps
CPU time 0.99 seconds
Started Oct 04 01:41:55 PM PDT 23
Finished Oct 04 01:41:57 PM PDT 23
Peak memory 214632 kb
Host smart-fac68de8-5799-4644-8caa-3427f52c88bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848913375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1848913375
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1860367189
Short name T169
Test name
Test status
Simulation time 18456358 ps
CPU time 1.07 seconds
Started Oct 04 01:53:11 PM PDT 23
Finished Oct 04 01:53:13 PM PDT 23
Peak memory 221552 kb
Host smart-db3349df-5fb8-4155-b99c-3e4b9a5119ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860367189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1860367189
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.532979185
Short name T573
Test name
Test status
Simulation time 226640794 ps
CPU time 1.08 seconds
Started Oct 04 01:49:50 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 214444 kb
Host smart-4883ae17-fc6d-45fa-80c1-09ffef074e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532979185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.532979185
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1741284210
Short name T26
Test name
Test status
Simulation time 18549104 ps
CPU time 1.04 seconds
Started Oct 04 01:47:05 PM PDT 23
Finished Oct 04 01:47:07 PM PDT 23
Peak memory 214476 kb
Host smart-26001abf-f43c-4052-9adb-df98cbf67e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741284210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1741284210
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4228771855
Short name T659
Test name
Test status
Simulation time 22421117 ps
CPU time 0.91 seconds
Started Oct 04 01:45:24 PM PDT 23
Finished Oct 04 01:45:26 PM PDT 23
Peak memory 204936 kb
Host smart-15c9e052-a4a1-429b-9fd4-d45fc6ddd526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228771855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4228771855
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2142380953
Short name T188
Test name
Test status
Simulation time 401326720015 ps
CPU time 1980.2 seconds
Started Oct 04 01:44:00 PM PDT 23
Finished Oct 04 02:17:01 PM PDT 23
Peak memory 220248 kb
Host smart-dfe0df7c-eae9-455f-a59a-e9c36e697a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142380953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2142380953
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.2747284228
Short name T306
Test name
Test status
Simulation time 28020029 ps
CPU time 0.92 seconds
Started Oct 04 01:48:15 PM PDT 23
Finished Oct 04 01:48:17 PM PDT 23
Peak memory 206144 kb
Host smart-ce77f01d-f794-403a-884d-50c2b93094c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747284228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2747284228
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2372202136
Short name T482
Test name
Test status
Simulation time 30551411 ps
CPU time 0.88 seconds
Started Oct 04 01:41:54 PM PDT 23
Finished Oct 04 01:41:55 PM PDT 23
Peak memory 205556 kb
Host smart-3b9bf578-a229-493d-a5df-91dae39e6db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372202136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2372202136
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.2773076063
Short name T173
Test name
Test status
Simulation time 32699470 ps
CPU time 0.93 seconds
Started Oct 04 01:53:34 PM PDT 23
Finished Oct 04 01:53:36 PM PDT 23
Peak memory 221332 kb
Host smart-bd1ba531-078a-4605-9f50-36cb4a4f2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773076063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2773076063
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1363174450
Short name T292
Test name
Test status
Simulation time 56585303 ps
CPU time 0.96 seconds
Started Oct 04 01:53:04 PM PDT 23
Finished Oct 04 01:53:06 PM PDT 23
Peak memory 205216 kb
Host smart-69e75d40-726f-4469-bfc4-14393e9e2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363174450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1363174450
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3046024583
Short name T586
Test name
Test status
Simulation time 19717186 ps
CPU time 1.06 seconds
Started Oct 04 01:50:33 PM PDT 23
Finished Oct 04 01:50:35 PM PDT 23
Peak memory 221324 kb
Host smart-5b506c15-6b63-499a-82e0-7980bb62e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046024583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3046024583
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1334609840
Short name T592
Test name
Test status
Simulation time 14034171 ps
CPU time 0.91 seconds
Started Oct 04 01:53:25 PM PDT 23
Finished Oct 04 01:53:26 PM PDT 23
Peak memory 204680 kb
Host smart-2f6743c6-2454-4904-ab6a-4bbc723e10f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334609840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1334609840
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2979230245
Short name T654
Test name
Test status
Simulation time 122790272 ps
CPU time 1.98 seconds
Started Oct 04 01:46:18 PM PDT 23
Finished Oct 04 01:46:21 PM PDT 23
Peak memory 205772 kb
Host smart-6e684557-3047-4d02-9cfb-4c1d144aa77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979230245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2979230245
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3964770167
Short name T466
Test name
Test status
Simulation time 300879268408 ps
CPU time 1187.73 seconds
Started Oct 04 01:44:19 PM PDT 23
Finished Oct 04 02:04:07 PM PDT 23
Peak memory 218264 kb
Host smart-62d99b70-8963-4644-95b4-961acff7ecb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964770167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3964770167
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.2336094179
Short name T666
Test name
Test status
Simulation time 20003547 ps
CPU time 1.1 seconds
Started Oct 04 01:45:56 PM PDT 23
Finished Oct 04 01:45:57 PM PDT 23
Peak memory 206056 kb
Host smart-97ff5b2a-467e-4b55-90da-ec0037586a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336094179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2336094179
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.531431859
Short name T644
Test name
Test status
Simulation time 21803464 ps
CPU time 0.83 seconds
Started Oct 04 01:48:17 PM PDT 23
Finished Oct 04 01:48:19 PM PDT 23
Peak memory 205148 kb
Host smart-86e506b8-d495-4734-842f-4d4e197ac227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531431859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.531431859
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1651626827
Short name T262
Test name
Test status
Simulation time 11113130 ps
CPU time 0.89 seconds
Started Oct 04 01:47:02 PM PDT 23
Finished Oct 04 01:47:03 PM PDT 23
Peak memory 214416 kb
Host smart-a2229ad5-8ab6-4542-86fa-11d0a9a03e91
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651626827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1651626827
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.1868779553
Short name T547
Test name
Test status
Simulation time 23401477 ps
CPU time 0.81 seconds
Started Oct 04 01:49:46 PM PDT 23
Finished Oct 04 01:49:49 PM PDT 23
Peak memory 214348 kb
Host smart-0de38ffe-b1b1-4531-95fc-2e0683c0d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868779553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1868779553
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.405893560
Short name T124
Test name
Test status
Simulation time 31737406 ps
CPU time 0.98 seconds
Started Oct 04 01:51:39 PM PDT 23
Finished Oct 04 01:51:40 PM PDT 23
Peak memory 214480 kb
Host smart-959390eb-7cbc-41d0-84ad-ee8bdb880838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405893560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.405893560
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1675391150
Short name T51
Test name
Test status
Simulation time 32567316 ps
CPU time 0.93 seconds
Started Oct 04 01:47:57 PM PDT 23
Finished Oct 04 01:47:58 PM PDT 23
Peak memory 221648 kb
Host smart-a7be2789-5920-4758-88cc-1e5cbd6ab324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675391150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1675391150
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1823840035
Short name T639
Test name
Test status
Simulation time 14503013 ps
CPU time 0.9 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:49 PM PDT 23
Peak memory 204772 kb
Host smart-398f633c-893a-4b44-8fc6-4f8d97fe9a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823840035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1823840035
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4017809604
Short name T486
Test name
Test status
Simulation time 62399466513 ps
CPU time 1323.92 seconds
Started Oct 04 01:46:03 PM PDT 23
Finished Oct 04 02:08:08 PM PDT 23
Peak memory 215924 kb
Host smart-ac7159c0-b418-425a-b2ab-662c5a6f493e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017809604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4017809604
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.edn_alert_test.169423266
Short name T641
Test name
Test status
Simulation time 135722005 ps
CPU time 0.86 seconds
Started Oct 04 01:49:49 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 204600 kb
Host smart-c14a42c4-eb94-41bf-9799-214667543488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169423266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.169423266
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.461080380
Short name T557
Test name
Test status
Simulation time 51832336 ps
CPU time 0.84 seconds
Started Oct 04 01:45:47 PM PDT 23
Finished Oct 04 01:45:48 PM PDT 23
Peak memory 214452 kb
Host smart-ca2c54a0-e508-469d-bb29-58eaf205d5f9
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461080380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.461080380
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2753657255
Short name T70
Test name
Test status
Simulation time 18948123 ps
CPU time 0.97 seconds
Started Oct 04 01:43:13 PM PDT 23
Finished Oct 04 01:43:14 PM PDT 23
Peak memory 214620 kb
Host smart-9acc3041-0230-4e0a-a7d0-6a8a23995726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753657255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2753657255
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2876473270
Short name T116
Test name
Test status
Simulation time 20757337 ps
CPU time 1.04 seconds
Started Oct 04 01:44:03 PM PDT 23
Finished Oct 04 01:44:05 PM PDT 23
Peak memory 215800 kb
Host smart-2eaab873-bb47-4fd7-a936-a15b919f4fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876473270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2876473270
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.822240039
Short name T612
Test name
Test status
Simulation time 109518590 ps
CPU time 0.87 seconds
Started Oct 04 01:42:03 PM PDT 23
Finished Oct 04 01:42:05 PM PDT 23
Peak memory 205032 kb
Host smart-541a216a-17e0-4a69-88a0-b9fbe45b91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822240039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.822240039
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4176207372
Short name T537
Test name
Test status
Simulation time 32897794 ps
CPU time 0.87 seconds
Started Oct 04 01:51:55 PM PDT 23
Finished Oct 04 01:51:57 PM PDT 23
Peak memory 214596 kb
Host smart-042a33da-e42c-4409-b573-ec6e5972bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176207372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4176207372
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3569634929
Short name T643
Test name
Test status
Simulation time 15668820 ps
CPU time 0.92 seconds
Started Oct 04 01:42:00 PM PDT 23
Finished Oct 04 01:42:02 PM PDT 23
Peak memory 204760 kb
Host smart-970b50d6-06dc-4419-8ea7-568a8280832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569634929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3569634929
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2643762581
Short name T616
Test name
Test status
Simulation time 927421731 ps
CPU time 2.46 seconds
Started Oct 04 01:51:55 PM PDT 23
Finished Oct 04 01:51:58 PM PDT 23
Peak memory 206180 kb
Host smart-0b0d5726-1ff3-4262-8701-ab6a4c313494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643762581 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2643762581
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_alert.3125111478
Short name T92
Test name
Test status
Simulation time 19446049 ps
CPU time 0.99 seconds
Started Oct 04 01:50:51 PM PDT 23
Finished Oct 04 01:50:53 PM PDT 23
Peak memory 205336 kb
Host smart-b69d63ea-78dc-4da4-9fa8-4cf55167da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125111478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3125111478
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4079373760
Short name T680
Test name
Test status
Simulation time 30352716 ps
CPU time 1.06 seconds
Started Oct 04 01:42:04 PM PDT 23
Finished Oct 04 01:42:05 PM PDT 23
Peak memory 204676 kb
Host smart-27c00665-8780-451a-8846-07a2ab1d67ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079373760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4079373760
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1799760728
Short name T576
Test name
Test status
Simulation time 50129500 ps
CPU time 1 seconds
Started Oct 04 01:45:12 PM PDT 23
Finished Oct 04 01:45:14 PM PDT 23
Peak memory 214524 kb
Host smart-ef894ca5-4f80-4e92-b424-d65944c8287e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799760728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1799760728
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2607994367
Short name T260
Test name
Test status
Simulation time 32757909 ps
CPU time 1.02 seconds
Started Oct 04 01:51:15 PM PDT 23
Finished Oct 04 01:51:17 PM PDT 23
Peak memory 228868 kb
Host smart-df6493f3-85cc-4005-84a1-6ec0845bc2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607994367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2607994367
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3034527011
Short name T608
Test name
Test status
Simulation time 207101082 ps
CPU time 1.03 seconds
Started Oct 04 01:53:29 PM PDT 23
Finished Oct 04 01:53:31 PM PDT 23
Peak memory 205228 kb
Host smart-04ca68e7-a23e-482e-8232-793edf02a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034527011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3034527011
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.590574529
Short name T681
Test name
Test status
Simulation time 17741261 ps
CPU time 0.97 seconds
Started Oct 04 01:51:37 PM PDT 23
Finished Oct 04 01:51:38 PM PDT 23
Peak memory 214764 kb
Host smart-30db513b-895e-4e47-bfb3-f5d349b51444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590574529 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.590574529
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3561988638
Short name T329
Test name
Test status
Simulation time 94061563 ps
CPU time 0.85 seconds
Started Oct 04 01:53:11 PM PDT 23
Finished Oct 04 01:53:12 PM PDT 23
Peak memory 204976 kb
Host smart-3e684e8d-5160-4386-a55e-9277f6ad6d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561988638 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3561988638
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.757721783
Short name T320
Test name
Test status
Simulation time 193348392 ps
CPU time 1.8 seconds
Started Oct 04 01:43:10 PM PDT 23
Finished Oct 04 01:43:12 PM PDT 23
Peak memory 205740 kb
Host smart-27011416-e072-460d-9e2b-3ee59e9e06de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757721783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.757721783
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2766537428
Short name T581
Test name
Test status
Simulation time 161396229360 ps
CPU time 367.61 seconds
Started Oct 04 01:42:06 PM PDT 23
Finished Oct 04 01:48:14 PM PDT 23
Peak memory 214888 kb
Host smart-551c27b0-c3c7-4f7f-953e-47b1843c0992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766537428 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2766537428
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.3496789276
Short name T83
Test name
Test status
Simulation time 56669675 ps
CPU time 0.94 seconds
Started Oct 04 01:46:01 PM PDT 23
Finished Oct 04 01:46:03 PM PDT 23
Peak memory 205356 kb
Host smart-adf82336-cd82-4db3-a472-051df1f680bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496789276 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3496789276
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2648316653
Short name T332
Test name
Test status
Simulation time 31135213 ps
CPU time 0.88 seconds
Started Oct 04 01:49:53 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 204612 kb
Host smart-f7173738-a35c-49fc-aaa2-ce3f1cd7a309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648316653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2648316653
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3869127131
Short name T80
Test name
Test status
Simulation time 31181181 ps
CPU time 0.86 seconds
Started Oct 04 01:51:57 PM PDT 23
Finished Oct 04 01:51:59 PM PDT 23
Peak memory 214512 kb
Host smart-35901665-ea86-4d0b-b861-a60bfd26bf66
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869127131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3869127131
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1865708765
Short name T154
Test name
Test status
Simulation time 114067210 ps
CPU time 1.08 seconds
Started Oct 04 01:42:10 PM PDT 23
Finished Oct 04 01:42:12 PM PDT 23
Peak memory 214548 kb
Host smart-a6c76069-4da7-4b61-b68a-98bfe5242dca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865708765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1865708765
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1207543099
Short name T157
Test name
Test status
Simulation time 19086735 ps
CPU time 1.32 seconds
Started Oct 04 01:42:19 PM PDT 23
Finished Oct 04 01:42:21 PM PDT 23
Peak memory 215520 kb
Host smart-a687da6e-8860-4f7b-a38d-8010613140ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207543099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1207543099
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2375822284
Short name T579
Test name
Test status
Simulation time 87398562 ps
CPU time 1.18 seconds
Started Oct 04 01:52:53 PM PDT 23
Finished Oct 04 01:52:55 PM PDT 23
Peak memory 205048 kb
Host smart-97cd65f5-42d8-4f66-a4b2-44e9dfd65b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375822284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2375822284
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.71002765
Short name T584
Test name
Test status
Simulation time 34920611 ps
CPU time 0.98 seconds
Started Oct 04 01:53:23 PM PDT 23
Finished Oct 04 01:53:24 PM PDT 23
Peak memory 214548 kb
Host smart-716bafea-b367-4879-9164-18c8172c83cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71002765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.71002765
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3149958230
Short name T346
Test name
Test status
Simulation time 33753827 ps
CPU time 0.83 seconds
Started Oct 04 01:42:10 PM PDT 23
Finished Oct 04 01:42:12 PM PDT 23
Peak memory 204660 kb
Host smart-97b6046f-e566-46be-b011-16b62dbceb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149958230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3149958230
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2735817822
Short name T527
Test name
Test status
Simulation time 367583816 ps
CPU time 4.02 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 01:50:36 PM PDT 23
Peak memory 205952 kb
Host smart-d80a842b-d248-4fd5-bb51-8f7de1eca257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735817822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2735817822
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1957400527
Short name T707
Test name
Test status
Simulation time 71829106989 ps
CPU time 914.69 seconds
Started Oct 04 01:50:40 PM PDT 23
Finished Oct 04 02:05:56 PM PDT 23
Peak memory 216112 kb
Host smart-c1b11631-e336-48ba-89ed-6637eabfb9d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957400527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1957400527
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.1510047810
Short name T703
Test name
Test status
Simulation time 57140519 ps
CPU time 0.92 seconds
Started Oct 04 01:45:59 PM PDT 23
Finished Oct 04 01:46:00 PM PDT 23
Peak memory 206092 kb
Host smart-d4140d23-8657-4c6f-b54e-2604e047c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510047810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1510047810
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1594445157
Short name T120
Test name
Test status
Simulation time 89247914 ps
CPU time 0.88 seconds
Started Oct 04 01:44:51 PM PDT 23
Finished Oct 04 01:44:54 PM PDT 23
Peak memory 204572 kb
Host smart-2870a3db-d30e-4330-804a-d3fa4fd30f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594445157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1594445157
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3609018250
Short name T582
Test name
Test status
Simulation time 12404658 ps
CPU time 0.88 seconds
Started Oct 04 01:45:29 PM PDT 23
Finished Oct 04 01:45:30 PM PDT 23
Peak memory 214512 kb
Host smart-25724949-9523-4851-82e1-83c195d2c862
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609018250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3609018250
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.400705531
Short name T610
Test name
Test status
Simulation time 55666050 ps
CPU time 1.11 seconds
Started Oct 04 01:43:25 PM PDT 23
Finished Oct 04 01:43:27 PM PDT 23
Peak memory 214584 kb
Host smart-8c960ae0-467e-4c12-9ef1-c1c66b963e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400705531 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.400705531
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.4093615472
Short name T247
Test name
Test status
Simulation time 68893194 ps
CPU time 1 seconds
Started Oct 04 01:42:09 PM PDT 23
Finished Oct 04 01:42:10 PM PDT 23
Peak memory 216792 kb
Host smart-075ae8c7-b222-434b-9b37-143b05ebcdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093615472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4093615472
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1243363190
Short name T626
Test name
Test status
Simulation time 116543928 ps
CPU time 0.9 seconds
Started Oct 04 01:55:22 PM PDT 23
Finished Oct 04 01:55:25 PM PDT 23
Peak memory 205080 kb
Host smart-1c5b89dd-656e-49c4-bf18-08eb92cf348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243363190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1243363190
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.996869257
Short name T104
Test name
Test status
Simulation time 52353863 ps
CPU time 0.82 seconds
Started Oct 04 01:52:28 PM PDT 23
Finished Oct 04 01:52:29 PM PDT 23
Peak memory 214668 kb
Host smart-deacf5e6-2ac4-4251-b07c-0c8acfab5093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996869257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.996869257
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.764108136
Short name T669
Test name
Test status
Simulation time 58036625 ps
CPU time 0.88 seconds
Started Oct 04 01:43:13 PM PDT 23
Finished Oct 04 01:43:14 PM PDT 23
Peak memory 204776 kb
Host smart-b5374c62-8c03-4f8d-9c60-637784c36e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764108136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.764108136
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.323127420
Short name T464
Test name
Test status
Simulation time 417644381 ps
CPU time 4.36 seconds
Started Oct 04 01:42:11 PM PDT 23
Finished Oct 04 01:42:16 PM PDT 23
Peak memory 205636 kb
Host smart-fc0568b9-23b3-46cc-9b0a-d8c9ec079b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323127420 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.323127420
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3614620093
Short name T463
Test name
Test status
Simulation time 122041993267 ps
CPU time 1258.18 seconds
Started Oct 04 01:53:01 PM PDT 23
Finished Oct 04 02:14:00 PM PDT 23
Peak memory 217296 kb
Host smart-8db70a43-45fb-4385-953a-1fb5acd8d891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614620093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3614620093
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_alert.698402980
Short name T268
Test name
Test status
Simulation time 20605638 ps
CPU time 1.02 seconds
Started Oct 04 01:53:24 PM PDT 23
Finished Oct 04 01:53:25 PM PDT 23
Peak memory 205292 kb
Host smart-1f57901d-dae0-4298-9ed9-a735a3619db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698402980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.698402980
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4191445958
Short name T634
Test name
Test status
Simulation time 33082451 ps
CPU time 0.85 seconds
Started Oct 04 01:52:51 PM PDT 23
Finished Oct 04 01:52:53 PM PDT 23
Peak memory 204604 kb
Host smart-5a188318-b23f-40ce-b289-7a6b28a1af3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191445958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4191445958
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3169515656
Short name T673
Test name
Test status
Simulation time 44912814 ps
CPU time 1.04 seconds
Started Oct 04 01:45:26 PM PDT 23
Finished Oct 04 01:45:27 PM PDT 23
Peak memory 214548 kb
Host smart-cd6799ed-b2eb-4c11-a551-94c239bc195b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169515656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3169515656
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1514422180
Short name T602
Test name
Test status
Simulation time 38050528 ps
CPU time 1.01 seconds
Started Oct 04 01:47:03 PM PDT 23
Finished Oct 04 01:47:04 PM PDT 23
Peak memory 214344 kb
Host smart-0913ac2a-1f2b-4472-88e6-e62e58883b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514422180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1514422180
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4294231844
Short name T102
Test name
Test status
Simulation time 76590056 ps
CPU time 1.08 seconds
Started Oct 04 01:53:24 PM PDT 23
Finished Oct 04 01:53:26 PM PDT 23
Peak memory 205632 kb
Host smart-c8ae3acd-017e-45ca-8c36-815a385f06c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294231844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4294231844
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.763496628
Short name T36
Test name
Test status
Simulation time 21041568 ps
CPU time 1.03 seconds
Started Oct 04 01:46:09 PM PDT 23
Finished Oct 04 01:46:10 PM PDT 23
Peak memory 214500 kb
Host smart-5a122c2a-62d8-4616-81c8-246ca45c9046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763496628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.763496628
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3701720206
Short name T590
Test name
Test status
Simulation time 24585961 ps
CPU time 0.91 seconds
Started Oct 04 01:50:38 PM PDT 23
Finished Oct 04 01:50:39 PM PDT 23
Peak memory 204912 kb
Host smart-f316c5be-4342-49cc-ad63-b810e7bb0410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701720206 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3701720206
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1946431919
Short name T542
Test name
Test status
Simulation time 1087364293 ps
CPU time 3.51 seconds
Started Oct 04 01:50:43 PM PDT 23
Finished Oct 04 01:50:47 PM PDT 23
Peak memory 205844 kb
Host smart-4ef4a8fd-db74-49aa-a09f-aa0cf5424cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946431919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1946431919
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3828115469
Short name T186
Test name
Test status
Simulation time 67383694443 ps
CPU time 1427.38 seconds
Started Oct 04 01:52:12 PM PDT 23
Finished Oct 04 02:16:00 PM PDT 23
Peak memory 217028 kb
Host smart-bb299e39-c443-44a5-aad7-c8a90a34b0ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828115469 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3828115469
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.89692581
Short name T572
Test name
Test status
Simulation time 33623727 ps
CPU time 0.96 seconds
Started Oct 04 01:48:21 PM PDT 23
Finished Oct 04 01:48:23 PM PDT 23
Peak memory 206264 kb
Host smart-ced6325d-4fd5-46e1-b0e1-62af14c1b17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89692581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.89692581
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.963265075
Short name T577
Test name
Test status
Simulation time 150942724 ps
CPU time 1.05 seconds
Started Oct 04 01:49:38 PM PDT 23
Finished Oct 04 01:49:40 PM PDT 23
Peak memory 204704 kb
Host smart-be947a33-f47f-4dfc-8977-049f6e47bdf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963265075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.963265075
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.4123776396
Short name T155
Test name
Test status
Simulation time 37555322 ps
CPU time 0.92 seconds
Started Oct 04 01:52:39 PM PDT 23
Finished Oct 04 01:52:40 PM PDT 23
Peak memory 214732 kb
Host smart-c4971b60-4c16-4989-a78f-b93f17a27004
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123776396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.4123776396
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.979698109
Short name T172
Test name
Test status
Simulation time 27763585 ps
CPU time 0.91 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:48 PM PDT 23
Peak memory 221168 kb
Host smart-a9973b33-7dad-4b1d-8e15-ec77a504059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979698109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.979698109
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.1408767217
Short name T526
Test name
Test status
Simulation time 27874077 ps
CPU time 0.89 seconds
Started Oct 04 01:54:23 PM PDT 23
Finished Oct 04 01:54:25 PM PDT 23
Peak memory 214800 kb
Host smart-66eeebe3-c0ce-4a82-981e-39554433a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408767217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1408767217
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3608664738
Short name T563
Test name
Test status
Simulation time 46232664 ps
CPU time 0.81 seconds
Started Oct 04 01:47:58 PM PDT 23
Finished Oct 04 01:48:00 PM PDT 23
Peak memory 204628 kb
Host smart-55cae0e0-049f-4693-a003-601434c32f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608664738 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3608664738
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1040263643
Short name T328
Test name
Test status
Simulation time 291603262 ps
CPU time 3.75 seconds
Started Oct 04 01:51:45 PM PDT 23
Finished Oct 04 01:51:50 PM PDT 23
Peak memory 205884 kb
Host smart-da20a537-a830-4f20-b578-f1591cece6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040263643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1040263643
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_alert_test.1745310589
Short name T518
Test name
Test status
Simulation time 20086146 ps
CPU time 0.86 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 01:50:32 PM PDT 23
Peak memory 205248 kb
Host smart-9bd28c6c-2e9d-4d20-9242-96d1ac4cafa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745310589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1745310589
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4063586483
Short name T727
Test name
Test status
Simulation time 41380410 ps
CPU time 0.86 seconds
Started Oct 04 01:45:44 PM PDT 23
Finished Oct 04 01:45:45 PM PDT 23
Peak memory 214404 kb
Host smart-3b9c51b7-7867-4447-906d-b59e17441f83
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063586483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4063586483
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1067611238
Short name T8
Test name
Test status
Simulation time 131815683 ps
CPU time 1.13 seconds
Started Oct 04 01:48:20 PM PDT 23
Finished Oct 04 01:48:22 PM PDT 23
Peak memory 214704 kb
Host smart-cf7b6826-7ae4-4865-8a49-9dc371c755ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067611238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1067611238
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3164470857
Short name T570
Test name
Test status
Simulation time 22097822 ps
CPU time 1.04 seconds
Started Oct 04 01:50:14 PM PDT 23
Finished Oct 04 01:50:15 PM PDT 23
Peak memory 214496 kb
Host smart-00771afc-7de2-48f6-914d-82a66c3882e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164470857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3164470857
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1704835124
Short name T323
Test name
Test status
Simulation time 49315094 ps
CPU time 0.91 seconds
Started Oct 04 01:45:45 PM PDT 23
Finished Oct 04 01:45:46 PM PDT 23
Peak memory 205636 kb
Host smart-1b72e462-8627-4e13-ad3c-e2d5f4eedf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704835124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1704835124
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1234688707
Short name T515
Test name
Test status
Simulation time 31349593 ps
CPU time 0.82 seconds
Started Oct 04 01:51:29 PM PDT 23
Finished Oct 04 01:51:31 PM PDT 23
Peak memory 214596 kb
Host smart-3156403c-2505-471b-a118-642ae88bfe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234688707 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1234688707
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2613342316
Short name T18
Test name
Test status
Simulation time 355398777 ps
CPU time 6.02 seconds
Started Oct 04 01:50:39 PM PDT 23
Finished Oct 04 01:50:45 PM PDT 23
Peak memory 234220 kb
Host smart-733fe615-73db-409d-b14a-f1939efc955e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613342316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2613342316
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2497140417
Short name T341
Test name
Test status
Simulation time 103159320 ps
CPU time 0.81 seconds
Started Oct 04 01:46:38 PM PDT 23
Finished Oct 04 01:46:40 PM PDT 23
Peak memory 204960 kb
Host smart-9426f552-8587-4dc2-b73a-67c6810ba287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497140417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2497140417
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3453036607
Short name T646
Test name
Test status
Simulation time 80079183 ps
CPU time 2.02 seconds
Started Oct 04 01:51:10 PM PDT 23
Finished Oct 04 01:51:12 PM PDT 23
Peak memory 205732 kb
Host smart-bd542bd4-2b57-4f73-8340-3468c130ff18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453036607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3453036607
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.139336589
Short name T538
Test name
Test status
Simulation time 101930022878 ps
CPU time 417.13 seconds
Started Oct 04 01:47:56 PM PDT 23
Finished Oct 04 01:54:54 PM PDT 23
Peak memory 215620 kb
Host smart-8134d2f2-5cc6-46e9-b0db-0bdd42321972
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139336589 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.139336589
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2984800989
Short name T16
Test name
Test status
Simulation time 20883011 ps
CPU time 0.99 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:48 PM PDT 23
Peak memory 205084 kb
Host smart-9da752df-8247-4af9-80a5-17a6efebb3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984800989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2984800989
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3530746663
Short name T121
Test name
Test status
Simulation time 53535590 ps
CPU time 0.9 seconds
Started Oct 04 01:46:02 PM PDT 23
Finished Oct 04 01:46:04 PM PDT 23
Peak memory 205304 kb
Host smart-742403c4-d79f-491b-8c77-7c2b26f13bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530746663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3530746663
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4093016428
Short name T59
Test name
Test status
Simulation time 33543913 ps
CPU time 0.82 seconds
Started Oct 04 01:51:50 PM PDT 23
Finished Oct 04 01:51:52 PM PDT 23
Peak memory 214576 kb
Host smart-b0272b2b-9229-4b60-bfc4-89f900aff3ea
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093016428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4093016428
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.2745722023
Short name T698
Test name
Test status
Simulation time 26527992 ps
CPU time 1 seconds
Started Oct 04 01:51:13 PM PDT 23
Finished Oct 04 01:51:15 PM PDT 23
Peak memory 221548 kb
Host smart-db203813-8f78-4098-87b2-5f4afc73ac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745722023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2745722023
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.397080281
Short name T499
Test name
Test status
Simulation time 41558904 ps
CPU time 0.8 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:49 PM PDT 23
Peak memory 214364 kb
Host smart-83fac18c-5895-4ba0-b202-e20075b7ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397080281 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.397080281
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.519554654
Short name T207
Test name
Test status
Simulation time 90110628 ps
CPU time 0.83 seconds
Started Oct 04 01:50:26 PM PDT 23
Finished Oct 04 01:50:27 PM PDT 23
Peak memory 204836 kb
Host smart-548bb449-73b4-4b5c-824f-504302a61745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519554654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.519554654
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1530118261
Short name T315
Test name
Test status
Simulation time 32154616 ps
CPU time 0.95 seconds
Started Oct 04 01:58:29 PM PDT 23
Finished Oct 04 01:58:30 PM PDT 23
Peak memory 204952 kb
Host smart-8b9a4051-7c3e-4217-8d37-538056a15e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530118261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1530118261
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3190021172
Short name T345
Test name
Test status
Simulation time 109588224064 ps
CPU time 1336.85 seconds
Started Oct 04 01:50:34 PM PDT 23
Finished Oct 04 02:12:52 PM PDT 23
Peak memory 219904 kb
Host smart-e2162a04-91f7-4a57-9181-8e53800b5cf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190021172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3190021172
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.2748761172
Short name T656
Test name
Test status
Simulation time 57296347 ps
CPU time 1 seconds
Started Oct 04 01:43:35 PM PDT 23
Finished Oct 04 01:43:37 PM PDT 23
Peak memory 206144 kb
Host smart-2f74ce91-b762-4003-b6b5-e2fe07fc1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748761172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2748761172
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2072560504
Short name T718
Test name
Test status
Simulation time 29399075 ps
CPU time 0.91 seconds
Started Oct 04 01:51:07 PM PDT 23
Finished Oct 04 01:51:09 PM PDT 23
Peak memory 204664 kb
Host smart-fc0d436c-9321-4830-9358-09e18cc9e2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072560504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2072560504
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3530337458
Short name T94
Test name
Test status
Simulation time 11421785 ps
CPU time 0.87 seconds
Started Oct 04 01:44:41 PM PDT 23
Finished Oct 04 01:44:42 PM PDT 23
Peak memory 214392 kb
Host smart-75b7bdc5-f2f6-438e-a993-405d14b2116b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530337458 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3530337458
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.2878385132
Short name T635
Test name
Test status
Simulation time 75316761 ps
CPU time 1.02 seconds
Started Oct 04 01:42:20 PM PDT 23
Finished Oct 04 01:42:22 PM PDT 23
Peak memory 221788 kb
Host smart-625e7229-3d0b-42b6-8c62-25aa71f4f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878385132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2878385132
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1979850342
Short name T671
Test name
Test status
Simulation time 28330478 ps
CPU time 0.92 seconds
Started Oct 04 01:51:35 PM PDT 23
Finished Oct 04 01:51:37 PM PDT 23
Peak memory 204828 kb
Host smart-5a180803-8052-4e5a-9891-bdce454e2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979850342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1979850342
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_smoke.1500217222
Short name T715
Test name
Test status
Simulation time 14993365 ps
CPU time 0.94 seconds
Started Oct 04 01:48:03 PM PDT 23
Finished Oct 04 01:48:05 PM PDT 23
Peak memory 204872 kb
Host smart-b6d533fe-1227-456e-b4d9-9064270bc12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500217222 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1500217222
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3994169048
Short name T569
Test name
Test status
Simulation time 609898726 ps
CPU time 3.37 seconds
Started Oct 04 01:47:56 PM PDT 23
Finished Oct 04 01:48:00 PM PDT 23
Peak memory 206192 kb
Host smart-7e90175d-48e4-4ff5-833c-72953d0ec8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994169048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3994169048
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2400311695
Short name T180
Test name
Test status
Simulation time 113268673756 ps
CPU time 2726.68 seconds
Started Oct 04 01:46:40 PM PDT 23
Finished Oct 04 02:32:08 PM PDT 23
Peak memory 227772 kb
Host smart-ce4a1873-4b36-4f2b-a360-bfc143a01cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400311695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2400311695
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.2980217079
Short name T558
Test name
Test status
Simulation time 33776358 ps
CPU time 1 seconds
Started Oct 04 01:53:15 PM PDT 23
Finished Oct 04 01:53:17 PM PDT 23
Peak memory 206188 kb
Host smart-281ef31e-f8b1-4783-b802-5035651c19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980217079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2980217079
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3288918472
Short name T336
Test name
Test status
Simulation time 22981653 ps
CPU time 0.82 seconds
Started Oct 04 01:49:35 PM PDT 23
Finished Oct 04 01:49:36 PM PDT 23
Peak memory 204632 kb
Host smart-316d63e8-2149-4a69-a07a-d06d3349d3dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288918472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3288918472
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3091865883
Short name T714
Test name
Test status
Simulation time 23817942 ps
CPU time 0.99 seconds
Started Oct 04 01:43:36 PM PDT 23
Finished Oct 04 01:43:37 PM PDT 23
Peak memory 214720 kb
Host smart-cd575930-40ad-48bb-bd84-ee128a733004
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091865883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3091865883
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2003494196
Short name T521
Test name
Test status
Simulation time 57289658 ps
CPU time 0.93 seconds
Started Oct 04 01:50:08 PM PDT 23
Finished Oct 04 01:50:09 PM PDT 23
Peak memory 215640 kb
Host smart-84ae6bdc-7444-4fee-ac05-e05d48c61099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003494196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2003494196
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_intr.4194676596
Short name T112
Test name
Test status
Simulation time 31780791 ps
CPU time 0.85 seconds
Started Oct 04 01:44:03 PM PDT 23
Finished Oct 04 01:44:05 PM PDT 23
Peak memory 214656 kb
Host smart-67308ef5-9572-4c85-9145-7009876d885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194676596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4194676596
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1131333621
Short name T477
Test name
Test status
Simulation time 50345161 ps
CPU time 0.84 seconds
Started Oct 04 01:51:03 PM PDT 23
Finished Oct 04 01:51:05 PM PDT 23
Peak memory 204780 kb
Host smart-b98a0ae1-1576-4110-8164-489001d19b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131333621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1131333621
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1754079846
Short name T200
Test name
Test status
Simulation time 56198891 ps
CPU time 1.16 seconds
Started Oct 04 01:45:56 PM PDT 23
Finished Oct 04 01:45:58 PM PDT 23
Peak memory 205260 kb
Host smart-ae918766-e87f-480b-9642-3c2c5c6cf668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754079846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1754079846
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.356094829
Short name T554
Test name
Test status
Simulation time 17730866478 ps
CPU time 444.91 seconds
Started Oct 04 01:43:37 PM PDT 23
Finished Oct 04 01:51:02 PM PDT 23
Peak memory 214512 kb
Host smart-8f15d6fb-4416-4d4f-b07a-3b07fe3b57b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356094829 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.356094829
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert.2356543215
Short name T624
Test name
Test status
Simulation time 25553516 ps
CPU time 0.96 seconds
Started Oct 04 01:49:53 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 205132 kb
Host smart-05f11a47-c48a-4ca4-85c6-ac906f5073f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356543215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2356543215
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2035819465
Short name T599
Test name
Test status
Simulation time 14431146 ps
CPU time 0.91 seconds
Started Oct 04 01:47:58 PM PDT 23
Finished Oct 04 01:48:00 PM PDT 23
Peak memory 205352 kb
Host smart-01608352-1aa9-455b-8252-27b826271374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035819465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2035819465
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_err.3498563724
Short name T597
Test name
Test status
Simulation time 32987479 ps
CPU time 0.83 seconds
Started Oct 04 01:44:00 PM PDT 23
Finished Oct 04 01:44:02 PM PDT 23
Peak memory 215520 kb
Host smart-2d13c123-91fe-46c3-bd6d-ecedf100fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498563724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3498563724
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.892672305
Short name T327
Test name
Test status
Simulation time 26432261 ps
CPU time 0.86 seconds
Started Oct 04 01:42:29 PM PDT 23
Finished Oct 04 01:42:31 PM PDT 23
Peak memory 205048 kb
Host smart-20818310-99f4-4503-a827-59c7870982c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892672305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.892672305
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3041358065
Short name T545
Test name
Test status
Simulation time 23529841 ps
CPU time 1.06 seconds
Started Oct 04 01:50:12 PM PDT 23
Finished Oct 04 01:50:14 PM PDT 23
Peak memory 225504 kb
Host smart-e850f536-86eb-49f8-84f5-83b2de7fb232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041358065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3041358065
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2900695693
Short name T326
Test name
Test status
Simulation time 38445204 ps
CPU time 0.83 seconds
Started Oct 04 01:53:14 PM PDT 23
Finished Oct 04 01:53:15 PM PDT 23
Peak memory 205000 kb
Host smart-d40553f8-0253-4eaf-a9e7-ed3bc8ea8170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900695693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2900695693
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.217283701
Short name T481
Test name
Test status
Simulation time 563772682 ps
CPU time 3.41 seconds
Started Oct 04 01:50:32 PM PDT 23
Finished Oct 04 01:50:37 PM PDT 23
Peak memory 206240 kb
Host smart-45cf718b-10ae-4ef1-9acf-79d083f6092f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217283701 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.217283701
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_alert.1799961412
Short name T535
Test name
Test status
Simulation time 18281548 ps
CPU time 0.95 seconds
Started Oct 04 01:47:52 PM PDT 23
Finished Oct 04 01:47:54 PM PDT 23
Peak memory 205236 kb
Host smart-bef92d64-f2fe-42e2-a7bc-50d56544fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799961412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1799961412
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3280116131
Short name T628
Test name
Test status
Simulation time 37170948 ps
CPU time 0.85 seconds
Started Oct 04 01:49:45 PM PDT 23
Finished Oct 04 01:49:48 PM PDT 23
Peak memory 204580 kb
Host smart-16aab07b-e231-4727-9f1b-a6f66481495c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280116131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3280116131
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.4123284097
Short name T125
Test name
Test status
Simulation time 12924268 ps
CPU time 0.86 seconds
Started Oct 04 01:44:06 PM PDT 23
Finished Oct 04 01:44:07 PM PDT 23
Peak memory 214556 kb
Host smart-8f6f4210-2560-4177-8ebd-bef977285aae
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123284097 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4123284097
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2807297614
Short name T149
Test name
Test status
Simulation time 135547392 ps
CPU time 1.09 seconds
Started Oct 04 01:50:09 PM PDT 23
Finished Oct 04 01:50:11 PM PDT 23
Peak memory 214604 kb
Host smart-d9c98cb6-ce4a-409a-a499-cf09f660345c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807297614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2807297614
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3191406684
Short name T509
Test name
Test status
Simulation time 19525228 ps
CPU time 1.16 seconds
Started Oct 04 01:51:04 PM PDT 23
Finished Oct 04 01:51:05 PM PDT 23
Peak memory 215664 kb
Host smart-2d579687-6441-43c4-b0a1-5999049e65ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191406684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3191406684
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2629241052
Short name T494
Test name
Test status
Simulation time 13534820 ps
CPU time 0.99 seconds
Started Oct 04 01:47:04 PM PDT 23
Finished Oct 04 01:47:05 PM PDT 23
Peak memory 205036 kb
Host smart-e1efe82b-e64b-4a6c-ac7c-f1dd5d7ec6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629241052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2629241052
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_smoke.3776313954
Short name T473
Test name
Test status
Simulation time 14591723 ps
CPU time 0.87 seconds
Started Oct 04 01:50:33 PM PDT 23
Finished Oct 04 01:50:35 PM PDT 23
Peak memory 204800 kb
Host smart-50ac7b4b-7883-4d12-b18e-24d5a46305f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776313954 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3776313954
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2124507649
Short name T695
Test name
Test status
Simulation time 90663825 ps
CPU time 2.25 seconds
Started Oct 04 01:42:29 PM PDT 23
Finished Oct 04 01:42:32 PM PDT 23
Peak memory 205792 kb
Host smart-65571aa7-6a06-4bc0-b4f7-6694d2546bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124507649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2124507649
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1564886203
Short name T277
Test name
Test status
Simulation time 49609880241 ps
CPU time 540.73 seconds
Started Oct 04 01:47:48 PM PDT 23
Finished Oct 04 01:56:49 PM PDT 23
Peak memory 215568 kb
Host smart-57fd3fbf-feba-49aa-af3c-278e6d0da4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564886203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1564886203
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert.1124700588
Short name T619
Test name
Test status
Simulation time 34643842 ps
CPU time 1 seconds
Started Oct 04 01:54:11 PM PDT 23
Finished Oct 04 01:54:12 PM PDT 23
Peak memory 206236 kb
Host smart-ed79a8bb-63c7-4454-90ce-6269c5b8945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124700588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1124700588
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2381937830
Short name T606
Test name
Test status
Simulation time 16435721 ps
CPU time 0.95 seconds
Started Oct 04 01:50:19 PM PDT 23
Finished Oct 04 01:50:21 PM PDT 23
Peak memory 204648 kb
Host smart-b91c7ae4-df6b-4b68-a03e-42797a285b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381937830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2381937830
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2768877243
Short name T135
Test name
Test status
Simulation time 19985794 ps
CPU time 0.86 seconds
Started Oct 04 01:47:27 PM PDT 23
Finished Oct 04 01:47:28 PM PDT 23
Peak memory 214516 kb
Host smart-a26e2c45-2a51-4be1-bddf-1ba7b66c798f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768877243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2768877243
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1461529542
Short name T566
Test name
Test status
Simulation time 26488926 ps
CPU time 0.99 seconds
Started Oct 04 01:44:10 PM PDT 23
Finished Oct 04 01:44:11 PM PDT 23
Peak memory 206580 kb
Host smart-6083ba35-968f-4fcb-b5e4-b154da75c5a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461529542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1461529542
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_genbits.4081964552
Short name T65
Test name
Test status
Simulation time 15355165 ps
CPU time 0.98 seconds
Started Oct 04 01:49:37 PM PDT 23
Finished Oct 04 01:49:38 PM PDT 23
Peak memory 204924 kb
Host smart-e56e8121-541f-49ce-8a65-7e5e54ca95bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081964552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.4081964552
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2327474821
Short name T106
Test name
Test status
Simulation time 19166327 ps
CPU time 1.05 seconds
Started Oct 04 01:44:04 PM PDT 23
Finished Oct 04 01:44:05 PM PDT 23
Peak memory 214760 kb
Host smart-f9b989b2-ce6d-4bc1-9b7f-f3d605df714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327474821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2327474821
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3702766462
Short name T58
Test name
Test status
Simulation time 46262639 ps
CPU time 0.89 seconds
Started Oct 04 01:49:22 PM PDT 23
Finished Oct 04 01:49:24 PM PDT 23
Peak memory 204820 kb
Host smart-ac41fab3-2b1b-4a4a-9e18-c3dace39a305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702766462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3702766462
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2922215792
Short name T614
Test name
Test status
Simulation time 120790366 ps
CPU time 2.51 seconds
Started Oct 04 01:49:50 PM PDT 23
Finished Oct 04 01:49:54 PM PDT 23
Peak memory 205760 kb
Host smart-fb6577e6-2ca8-4025-92d1-f99a8cb53e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922215792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2922215792
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.437211864
Short name T713
Test name
Test status
Simulation time 38970195445 ps
CPU time 846.33 seconds
Started Oct 04 01:51:17 PM PDT 23
Finished Oct 04 02:05:24 PM PDT 23
Peak memory 215676 kb
Host smart-0f49f867-e601-4882-aca8-49fcd01d5534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437211864 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.437211864
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.2093967053
Short name T613
Test name
Test status
Simulation time 45700259 ps
CPU time 0.94 seconds
Started Oct 04 01:45:14 PM PDT 23
Finished Oct 04 01:45:16 PM PDT 23
Peak memory 206044 kb
Host smart-15b7c295-59a5-4ba6-97a4-e3f9dd2e0c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093967053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2093967053
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3765059375
Short name T330
Test name
Test status
Simulation time 34848958 ps
CPU time 0.77 seconds
Started Oct 04 01:42:36 PM PDT 23
Finished Oct 04 01:42:37 PM PDT 23
Peak memory 204228 kb
Host smart-73f17071-a000-4ce2-99c5-958495a88702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765059375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3765059375
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1295389863
Short name T13
Test name
Test status
Simulation time 21932676 ps
CPU time 0.96 seconds
Started Oct 04 01:43:48 PM PDT 23
Finished Oct 04 01:43:50 PM PDT 23
Peak memory 214552 kb
Host smart-bece9855-381e-4099-b420-b2ec3b9282f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295389863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1295389863
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.1426576103
Short name T287
Test name
Test status
Simulation time 16037018 ps
CPU time 0.89 seconds
Started Oct 04 01:42:41 PM PDT 23
Finished Oct 04 01:42:42 PM PDT 23
Peak memory 205052 kb
Host smart-b667c91f-d862-4985-993a-e8c151b69966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426576103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1426576103
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.330952487
Short name T103
Test name
Test status
Simulation time 36042345 ps
CPU time 0.85 seconds
Started Oct 04 01:47:28 PM PDT 23
Finished Oct 04 01:47:30 PM PDT 23
Peak memory 214728 kb
Host smart-5be53622-2ead-4957-9cf7-de96a2bf8070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330952487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.330952487
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4142123380
Short name T57
Test name
Test status
Simulation time 35401800 ps
CPU time 0.82 seconds
Started Oct 04 01:52:21 PM PDT 23
Finished Oct 04 01:52:22 PM PDT 23
Peak memory 204716 kb
Host smart-1954974c-0080-4195-a21c-0e20007e2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142123380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4142123380
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.833457649
Short name T45
Test name
Test status
Simulation time 123654293 ps
CPU time 1.82 seconds
Started Oct 04 01:44:17 PM PDT 23
Finished Oct 04 01:44:19 PM PDT 23
Peak memory 205684 kb
Host smart-7d9a2b95-6be9-43d9-8fb2-16154c111f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833457649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.833457649
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1852280705
Short name T589
Test name
Test status
Simulation time 98881869857 ps
CPU time 961.32 seconds
Started Oct 04 01:49:48 PM PDT 23
Finished Oct 04 02:05:52 PM PDT 23
Peak memory 216432 kb
Host smart-c61454ee-1581-4eb3-8727-eaf4f180eb9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852280705 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1852280705
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert_test.2264029528
Short name T122
Test name
Test status
Simulation time 62493869 ps
CPU time 0.9 seconds
Started Oct 04 01:44:30 PM PDT 23
Finished Oct 04 01:44:31 PM PDT 23
Peak memory 204596 kb
Host smart-963643c2-40d0-43e4-a032-91a1c111f3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264029528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2264029528
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.4292198005
Short name T93
Test name
Test status
Simulation time 20472950 ps
CPU time 0.89 seconds
Started Oct 04 01:53:25 PM PDT 23
Finished Oct 04 01:53:26 PM PDT 23
Peak memory 214744 kb
Host smart-00a23ad7-3cb0-43af-89f9-36524bc9bc38
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292198005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4292198005
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2397012386
Short name T152
Test name
Test status
Simulation time 22930445 ps
CPU time 0.94 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:48 PM PDT 23
Peak memory 214364 kb
Host smart-3aae5f6b-ac3b-4095-88c7-1e8a02c2fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397012386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2397012386
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2811767886
Short name T291
Test name
Test status
Simulation time 38870554 ps
CPU time 0.88 seconds
Started Oct 04 01:44:42 PM PDT 23
Finished Oct 04 01:44:43 PM PDT 23
Peak memory 204988 kb
Host smart-958196f1-14e3-42c4-9613-973d9324f866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811767886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2811767886
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2701992099
Short name T111
Test name
Test status
Simulation time 21950152 ps
CPU time 0.93 seconds
Started Oct 04 01:49:39 PM PDT 23
Finished Oct 04 01:49:40 PM PDT 23
Peak memory 214936 kb
Host smart-82ea2601-b9f7-4a5e-b7a3-ba9f3e54baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701992099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2701992099
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1133257241
Short name T725
Test name
Test status
Simulation time 27398984 ps
CPU time 0.91 seconds
Started Oct 04 01:51:28 PM PDT 23
Finished Oct 04 01:51:30 PM PDT 23
Peak memory 204860 kb
Host smart-9891c846-877e-4787-baf5-5861676aec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133257241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1133257241
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1929497266
Short name T276
Test name
Test status
Simulation time 254285878 ps
CPU time 1.71 seconds
Started Oct 04 01:44:43 PM PDT 23
Finished Oct 04 01:44:46 PM PDT 23
Peak memory 205616 kb
Host smart-fe9e28a7-0ca8-40f7-80be-5f8ee7655dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929497266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1929497266
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.135387768
Short name T676
Test name
Test status
Simulation time 136152507860 ps
CPU time 887.41 seconds
Started Oct 04 01:53:41 PM PDT 23
Finished Oct 04 02:08:31 PM PDT 23
Peak memory 215592 kb
Host smart-7bfda2dc-2627-4b4c-bcc3-2c5237a8f88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135387768 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.135387768
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.3150313023
Short name T571
Test name
Test status
Simulation time 20624981 ps
CPU time 0.96 seconds
Started Oct 04 01:49:06 PM PDT 23
Finished Oct 04 01:49:07 PM PDT 23
Peak memory 206024 kb
Host smart-b84313cc-f9d6-4627-8199-68b7e6e53034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150313023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3150313023
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3083298027
Short name T560
Test name
Test status
Simulation time 39512930 ps
CPU time 0.8 seconds
Started Oct 04 01:49:10 PM PDT 23
Finished Oct 04 01:49:11 PM PDT 23
Peak memory 204500 kb
Host smart-54f4face-aba0-46c3-ab7c-1e5180016187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083298027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3083298027
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4188439391
Short name T89
Test name
Test status
Simulation time 34035827 ps
CPU time 0.92 seconds
Started Oct 04 01:49:04 PM PDT 23
Finished Oct 04 01:49:05 PM PDT 23
Peak memory 214388 kb
Host smart-a037dc37-ed16-4863-abbb-0943b7baf246
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188439391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4188439391
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1942328126
Short name T40
Test name
Test status
Simulation time 15965811 ps
CPU time 0.95 seconds
Started Oct 04 01:46:10 PM PDT 23
Finished Oct 04 01:46:12 PM PDT 23
Peak memory 214604 kb
Host smart-97540a4a-cef7-486e-9508-2aa2d91c6c85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942328126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1942328126
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3154489742
Short name T52
Test name
Test status
Simulation time 18342689 ps
CPU time 1.4 seconds
Started Oct 04 01:51:07 PM PDT 23
Finished Oct 04 01:51:09 PM PDT 23
Peak memory 222272 kb
Host smart-11cd9a12-66f2-481a-ac43-ba50386ed612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154489742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3154489742
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3004236476
Short name T11
Test name
Test status
Simulation time 24028388 ps
CPU time 1.11 seconds
Started Oct 04 01:53:25 PM PDT 23
Finished Oct 04 01:53:27 PM PDT 23
Peak memory 214440 kb
Host smart-a6d2d22d-5538-41a7-8579-1f0c17b3f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004236476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3004236476
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2249301458
Short name T546
Test name
Test status
Simulation time 22444754 ps
CPU time 1.06 seconds
Started Oct 04 01:54:02 PM PDT 23
Finished Oct 04 01:54:04 PM PDT 23
Peak memory 221588 kb
Host smart-a03f0730-7625-48ad-91a1-609964a2b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249301458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2249301458
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1672400099
Short name T711
Test name
Test status
Simulation time 102914032 ps
CPU time 0.84 seconds
Started Oct 04 01:45:41 PM PDT 23
Finished Oct 04 01:45:43 PM PDT 23
Peak memory 204736 kb
Host smart-bb1dd28c-cf36-4719-a846-4e8658a33a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672400099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1672400099
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2017854104
Short name T611
Test name
Test status
Simulation time 327885741 ps
CPU time 3.66 seconds
Started Oct 04 01:52:40 PM PDT 23
Finished Oct 04 01:52:44 PM PDT 23
Peak memory 206192 kb
Host smart-907979a5-0d6c-4111-9400-021649ed198d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017854104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2017854104
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3939649269
Short name T456
Test name
Test status
Simulation time 136786627965 ps
CPU time 1689.29 seconds
Started Oct 04 01:53:55 PM PDT 23
Finished Oct 04 02:22:05 PM PDT 23
Peak memory 222012 kb
Host smart-a7565a38-d94d-4321-9dd8-42858450224b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939649269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3939649269
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.1246407506
Short name T307
Test name
Test status
Simulation time 21326617 ps
CPU time 1.03 seconds
Started Oct 04 01:47:30 PM PDT 23
Finished Oct 04 01:47:31 PM PDT 23
Peak memory 205100 kb
Host smart-fa905da2-3e0b-40b9-88b4-4717eb136720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246407506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1246407506
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1620109360
Short name T632
Test name
Test status
Simulation time 18859851 ps
CPU time 0.82 seconds
Started Oct 04 01:53:57 PM PDT 23
Finished Oct 04 01:53:59 PM PDT 23
Peak memory 204356 kb
Host smart-9c867f18-8eab-49d8-a61e-08b9161590db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620109360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1620109360
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.83091535
Short name T170
Test name
Test status
Simulation time 22638214 ps
CPU time 0.8 seconds
Started Oct 04 01:47:31 PM PDT 23
Finished Oct 04 01:47:32 PM PDT 23
Peak memory 214376 kb
Host smart-f6e43ee2-7144-494e-b947-cca9ec9c6c65
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83091535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.83091535
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2760374062
Short name T160
Test name
Test status
Simulation time 48630903 ps
CPU time 1 seconds
Started Oct 04 01:47:58 PM PDT 23
Finished Oct 04 01:48:00 PM PDT 23
Peak memory 228712 kb
Host smart-4e2bf578-55d0-497a-8057-c3a1acee3457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760374062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2760374062
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.3891174127
Short name T552
Test name
Test status
Simulation time 34993180 ps
CPU time 0.85 seconds
Started Oct 04 01:45:37 PM PDT 23
Finished Oct 04 01:45:38 PM PDT 23
Peak memory 214340 kb
Host smart-744ba2aa-04bc-4100-a595-c3a0bd6fe898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891174127 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3891174127
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.196545447
Short name T523
Test name
Test status
Simulation time 52365011 ps
CPU time 0.8 seconds
Started Oct 04 01:42:51 PM PDT 23
Finished Oct 04 01:42:52 PM PDT 23
Peak memory 204904 kb
Host smart-ed727e82-839b-4ade-a1a1-2597cb4d72a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196545447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.196545447
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3502972830
Short name T691
Test name
Test status
Simulation time 141207960 ps
CPU time 3.26 seconds
Started Oct 04 01:54:23 PM PDT 23
Finished Oct 04 01:54:28 PM PDT 23
Peak memory 206068 kb
Host smart-2624de87-0bca-4e7d-be33-8e0e744b966a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502972830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3502972830
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.387888013
Short name T562
Test name
Test status
Simulation time 85728384427 ps
CPU time 603.97 seconds
Started Oct 04 01:53:17 PM PDT 23
Finished Oct 04 02:03:22 PM PDT 23
Peak memory 214688 kb
Host smart-70ed56bd-23ef-4c8c-8c9e-e88af5f4aed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387888013 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.387888013
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.691810886
Short name T531
Test name
Test status
Simulation time 54939190 ps
CPU time 0.98 seconds
Started Oct 04 01:54:15 PM PDT 23
Finished Oct 04 01:54:17 PM PDT 23
Peak memory 206144 kb
Host smart-b8fb2fae-3fe4-44ee-93d3-a3b43856d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691810886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.691810886
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4067046602
Short name T468
Test name
Test status
Simulation time 21318477 ps
CPU time 1.05 seconds
Started Oct 04 01:48:17 PM PDT 23
Finished Oct 04 01:48:19 PM PDT 23
Peak memory 204684 kb
Host smart-55a2872c-3782-46cf-ae28-2b8db1b4ac4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067046602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4067046602
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4166439955
Short name T601
Test name
Test status
Simulation time 64717668 ps
CPU time 0.82 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:50 PM PDT 23
Peak memory 214460 kb
Host smart-fb70df56-7454-467b-8fe5-b9533eeb5e4f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166439955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4166439955
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3932860355
Short name T603
Test name
Test status
Simulation time 41092591 ps
CPU time 0.97 seconds
Started Oct 04 01:51:59 PM PDT 23
Finished Oct 04 01:52:00 PM PDT 23
Peak memory 214664 kb
Host smart-5c3f4346-cbca-49f9-aefd-a61b663ae596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932860355 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3932860355
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2218916215
Short name T721
Test name
Test status
Simulation time 29136303 ps
CPU time 1.25 seconds
Started Oct 04 01:52:20 PM PDT 23
Finished Oct 04 01:52:23 PM PDT 23
Peak memory 217044 kb
Host smart-331cfbff-445c-4459-b88b-bd3fb6aa9569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218916215 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2218916215
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2413361753
Short name T693
Test name
Test status
Simulation time 23654380 ps
CPU time 1.15 seconds
Started Oct 04 01:51:54 PM PDT 23
Finished Oct 04 01:51:55 PM PDT 23
Peak memory 214336 kb
Host smart-2d4ceacb-bc7e-47bc-8bb5-dd719f8d40f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413361753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2413361753
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2006619531
Short name T687
Test name
Test status
Simulation time 58604224 ps
CPU time 0.83 seconds
Started Oct 04 01:53:05 PM PDT 23
Finished Oct 04 01:53:07 PM PDT 23
Peak memory 214392 kb
Host smart-a1073f9e-11d3-45db-8cef-64e1ff76dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006619531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2006619531
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3693902780
Short name T301
Test name
Test status
Simulation time 13354544 ps
CPU time 0.91 seconds
Started Oct 04 01:46:00 PM PDT 23
Finished Oct 04 01:46:02 PM PDT 23
Peak memory 204892 kb
Host smart-cd415c67-69f5-4e19-b401-592c6965b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693902780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3693902780
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2858465156
Short name T54
Test name
Test status
Simulation time 192009717 ps
CPU time 3.31 seconds
Started Oct 04 01:49:48 PM PDT 23
Finished Oct 04 01:49:53 PM PDT 23
Peak memory 231952 kb
Host smart-654cbf0e-ccf4-441d-ae5d-387cb910ec44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858465156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2858465156
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1621078771
Short name T683
Test name
Test status
Simulation time 18776812 ps
CPU time 0.83 seconds
Started Oct 04 01:43:59 PM PDT 23
Finished Oct 04 01:44:01 PM PDT 23
Peak memory 205176 kb
Host smart-9f441f94-2239-448e-a85d-7cf817fa9545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621078771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1621078771
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.923197838
Short name T651
Test name
Test status
Simulation time 319636750 ps
CPU time 3.74 seconds
Started Oct 04 01:48:05 PM PDT 23
Finished Oct 04 01:48:10 PM PDT 23
Peak memory 205908 kb
Host smart-25fe2e47-3676-4fab-8311-a155934eed00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923197838 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.923197838
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3037283894
Short name T182
Test name
Test status
Simulation time 32530007949 ps
CPU time 415.88 seconds
Started Oct 04 01:47:09 PM PDT 23
Finished Oct 04 01:54:05 PM PDT 23
Peak memory 215788 kb
Host smart-27eb7230-170b-4729-aab4-3792d39b2bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037283894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3037283894
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1796114977
Short name T636
Test name
Test status
Simulation time 20359961 ps
CPU time 1.01 seconds
Started Oct 04 01:53:56 PM PDT 23
Finished Oct 04 01:53:57 PM PDT 23
Peak memory 206188 kb
Host smart-b445da73-902d-4998-8e79-59aa5a3ec4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796114977 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1796114977
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1272942477
Short name T668
Test name
Test status
Simulation time 12671346 ps
CPU time 0.87 seconds
Started Oct 04 01:50:33 PM PDT 23
Finished Oct 04 01:50:36 PM PDT 23
Peak memory 205020 kb
Host smart-f4b48223-82ac-4c08-8d2e-42f5cc0fc141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272942477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1272942477
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1971226248
Short name T492
Test name
Test status
Simulation time 65412050 ps
CPU time 0.86 seconds
Started Oct 04 01:54:20 PM PDT 23
Finished Oct 04 01:54:22 PM PDT 23
Peak memory 214504 kb
Host smart-7ba66e1f-8532-4a65-9948-cccaea36f36a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971226248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1971226248
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.558007770
Short name T62
Test name
Test status
Simulation time 252112321 ps
CPU time 1.02 seconds
Started Oct 04 01:46:36 PM PDT 23
Finished Oct 04 01:46:38 PM PDT 23
Peak memory 214596 kb
Host smart-12f1d1ce-845a-474b-b137-f21bd2d3ac67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558007770 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.558007770
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2253477233
Short name T658
Test name
Test status
Simulation time 28892483 ps
CPU time 1.19 seconds
Started Oct 04 01:43:38 PM PDT 23
Finished Oct 04 01:43:40 PM PDT 23
Peak memory 216688 kb
Host smart-b3709a5a-3a1c-40ef-ad61-9b7a7d5ad55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253477233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2253477233
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3020799929
Short name T324
Test name
Test status
Simulation time 44570763 ps
CPU time 0.92 seconds
Started Oct 04 01:53:37 PM PDT 23
Finished Oct 04 01:53:38 PM PDT 23
Peak memory 204972 kb
Host smart-56f1763a-c1f7-4d16-88f7-950ed8dfe682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020799929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3020799929
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2366134924
Short name T318
Test name
Test status
Simulation time 25257552 ps
CPU time 0.91 seconds
Started Oct 04 01:49:43 PM PDT 23
Finished Oct 04 01:49:44 PM PDT 23
Peak memory 214404 kb
Host smart-1de9061a-50a3-4110-a6c0-6c61e896df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366134924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2366134924
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2439283475
Short name T690
Test name
Test status
Simulation time 15595181 ps
CPU time 0.89 seconds
Started Oct 04 01:54:57 PM PDT 23
Finished Oct 04 01:54:59 PM PDT 23
Peak memory 204944 kb
Host smart-67575ce3-6923-48f1-a34d-20a69456c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439283475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2439283475
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.821059575
Short name T540
Test name
Test status
Simulation time 97683900 ps
CPU time 1.53 seconds
Started Oct 04 01:52:42 PM PDT 23
Finished Oct 04 01:52:44 PM PDT 23
Peak memory 205484 kb
Host smart-56332285-0096-4e7b-a590-11e2080ac416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821059575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.821059575
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1849412866
Short name T716
Test name
Test status
Simulation time 44404011622 ps
CPU time 1088.24 seconds
Started Oct 04 01:46:34 PM PDT 23
Finished Oct 04 02:04:42 PM PDT 23
Peak memory 215344 kb
Host smart-cee5710c-895a-42b8-a2d0-10ec786e6ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849412866 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1849412866
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1363973703
Short name T86
Test name
Test status
Simulation time 17055975 ps
CPU time 0.97 seconds
Started Oct 04 01:44:22 PM PDT 23
Finished Oct 04 01:44:23 PM PDT 23
Peak memory 206104 kb
Host smart-d38f7815-fc9a-4d23-82bb-3c4a46468603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363973703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1363973703
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3772121973
Short name T457
Test name
Test status
Simulation time 14559527 ps
CPU time 0.91 seconds
Started Oct 04 01:46:02 PM PDT 23
Finished Oct 04 01:46:04 PM PDT 23
Peak memory 204764 kb
Host smart-7b9bcba2-df30-4d3b-b7fc-0b82b4bd607b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772121973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3772121973
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3135617149
Short name T503
Test name
Test status
Simulation time 12135011 ps
CPU time 0.88 seconds
Started Oct 04 01:46:46 PM PDT 23
Finished Oct 04 01:46:48 PM PDT 23
Peak memory 214512 kb
Host smart-1120e6f4-5dbb-4a87-92e6-8c6f6f4af56d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135617149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3135617149
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3619081965
Short name T524
Test name
Test status
Simulation time 109360334 ps
CPU time 1.13 seconds
Started Oct 04 01:51:51 PM PDT 23
Finished Oct 04 01:51:54 PM PDT 23
Peak memory 214616 kb
Host smart-eea7489d-d0ac-476c-90a1-02992c294fe4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619081965 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3619081965
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3186439442
Short name T50
Test name
Test status
Simulation time 106704026 ps
CPU time 1.1 seconds
Started Oct 04 01:44:10 PM PDT 23
Finished Oct 04 01:44:12 PM PDT 23
Peak memory 222228 kb
Host smart-55794986-6b12-40cc-bef7-2909a9b2860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186439442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3186439442
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.14405806
Short name T512
Test name
Test status
Simulation time 25213272 ps
CPU time 0.89 seconds
Started Oct 04 01:47:38 PM PDT 23
Finished Oct 04 01:47:40 PM PDT 23
Peak memory 204936 kb
Host smart-54730b66-4ca2-4c23-999e-ed45bfb1aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14405806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.14405806
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.249996292
Short name T600
Test name
Test status
Simulation time 23302741 ps
CPU time 0.92 seconds
Started Oct 04 01:53:11 PM PDT 23
Finished Oct 04 01:53:12 PM PDT 23
Peak memory 214616 kb
Host smart-be527203-626c-4871-b012-8225aa064d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249996292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.249996292
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3338197224
Short name T319
Test name
Test status
Simulation time 27341069 ps
CPU time 0.87 seconds
Started Oct 04 01:54:22 PM PDT 23
Finished Oct 04 01:54:24 PM PDT 23
Peak memory 204744 kb
Host smart-3ff870a1-27c4-49a4-9702-7920b5b977ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338197224 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3338197224
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4115692556
Short name T280
Test name
Test status
Simulation time 706090699 ps
CPU time 3.44 seconds
Started Oct 04 01:42:52 PM PDT 23
Finished Oct 04 01:42:56 PM PDT 23
Peak memory 205948 kb
Host smart-1c804b29-1ff8-4f76-a13d-b0d169f67942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115692556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4115692556
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2321885799
Short name T498
Test name
Test status
Simulation time 24481336735 ps
CPU time 496.64 seconds
Started Oct 04 01:49:36 PM PDT 23
Finished Oct 04 01:57:54 PM PDT 23
Peak memory 215644 kb
Host smart-4b07b6ed-4b4d-4a9d-b57c-e78bb01bfcf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321885799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2321885799
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.4099305944
Short name T717
Test name
Test status
Simulation time 21120032 ps
CPU time 0.99 seconds
Started Oct 04 01:48:21 PM PDT 23
Finished Oct 04 01:48:23 PM PDT 23
Peak memory 206216 kb
Host smart-ac3d930f-b64d-403e-aff5-e0879a205b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099305944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4099305944
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2335027415
Short name T555
Test name
Test status
Simulation time 54131695 ps
CPU time 0.89 seconds
Started Oct 04 01:55:07 PM PDT 23
Finished Oct 04 01:55:08 PM PDT 23
Peak memory 205272 kb
Host smart-60ecf743-bf61-4e82-adbb-c61da2b26068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335027415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2335027415
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3539260872
Short name T667
Test name
Test status
Simulation time 58414932 ps
CPU time 0.91 seconds
Started Oct 04 01:45:52 PM PDT 23
Finished Oct 04 01:45:53 PM PDT 23
Peak memory 214620 kb
Host smart-50c8fdf4-5ba1-4f27-804d-aafa7f5747ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539260872 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3539260872
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1954009662
Short name T266
Test name
Test status
Simulation time 22839813 ps
CPU time 1.14 seconds
Started Oct 04 01:53:48 PM PDT 23
Finished Oct 04 01:53:50 PM PDT 23
Peak memory 214572 kb
Host smart-fa90269d-6fb2-434d-b10d-17a23d9b1456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954009662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1954009662
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2933447431
Short name T79
Test name
Test status
Simulation time 40515258 ps
CPU time 1.1 seconds
Started Oct 04 01:45:52 PM PDT 23
Finished Oct 04 01:45:54 PM PDT 23
Peak memory 205340 kb
Host smart-0071078e-0d4f-47b0-a5fd-6dfc2ff9bb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933447431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2933447431
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1185239675
Short name T505
Test name
Test status
Simulation time 20723338 ps
CPU time 0.87 seconds
Started Oct 04 01:46:22 PM PDT 23
Finished Oct 04 01:46:24 PM PDT 23
Peak memory 214744 kb
Host smart-5ac98e7b-9341-4aa0-b3cd-b2543ac8dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185239675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1185239675
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.825417183
Short name T710
Test name
Test status
Simulation time 24907659 ps
CPU time 0.79 seconds
Started Oct 04 01:49:36 PM PDT 23
Finished Oct 04 01:49:37 PM PDT 23
Peak memory 204740 kb
Host smart-88299a9e-4206-46ac-bc2d-eaf414ab62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825417183 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.825417183
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.643562219
Short name T697
Test name
Test status
Simulation time 664749808 ps
CPU time 3.92 seconds
Started Oct 04 01:48:34 PM PDT 23
Finished Oct 04 01:48:38 PM PDT 23
Peak memory 205508 kb
Host smart-b2258d86-5992-454f-8c40-562d15c95fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643562219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.643562219
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2925193835
Short name T536
Test name
Test status
Simulation time 284137820908 ps
CPU time 986.99 seconds
Started Oct 04 01:46:01 PM PDT 23
Finished Oct 04 02:02:28 PM PDT 23
Peak memory 216396 kb
Host smart-d4ce548b-27b1-44b4-be78-fd4afd313165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925193835 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2925193835
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1118102465
Short name T605
Test name
Test status
Simulation time 35336547 ps
CPU time 0.9 seconds
Started Oct 04 01:50:33 PM PDT 23
Finished Oct 04 01:50:35 PM PDT 23
Peak memory 206172 kb
Host smart-11f57fb8-cd03-455b-b786-3b0e89aafeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118102465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1118102465
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1825356389
Short name T470
Test name
Test status
Simulation time 13175147 ps
CPU time 0.92 seconds
Started Oct 04 01:49:39 PM PDT 23
Finished Oct 04 01:49:40 PM PDT 23
Peak memory 204724 kb
Host smart-dc3ae849-edb8-4787-81ea-7e418d873b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825356389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1825356389
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1234073854
Short name T137
Test name
Test status
Simulation time 16210316 ps
CPU time 0.82 seconds
Started Oct 04 01:45:58 PM PDT 23
Finished Oct 04 01:46:00 PM PDT 23
Peak memory 214492 kb
Host smart-b64ae743-f40b-4f44-876a-3d859e5f350a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234073854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1234073854
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.452566652
Short name T127
Test name
Test status
Simulation time 41972164 ps
CPU time 1.02 seconds
Started Oct 04 01:52:36 PM PDT 23
Finished Oct 04 01:52:37 PM PDT 23
Peak memory 214672 kb
Host smart-79a162ed-b7fe-4950-a4ff-ae9831c30bd6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452566652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.452566652
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1614044337
Short name T675
Test name
Test status
Simulation time 162230010 ps
CPU time 1.11 seconds
Started Oct 04 01:43:59 PM PDT 23
Finished Oct 04 01:44:01 PM PDT 23
Peak memory 222044 kb
Host smart-c2bcb999-d577-42d0-83da-80d5cdd6cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614044337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1614044337
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.357599436
Short name T78
Test name
Test status
Simulation time 75130881 ps
CPU time 1.05 seconds
Started Oct 04 01:46:59 PM PDT 23
Finished Oct 04 01:47:00 PM PDT 23
Peak memory 205044 kb
Host smart-bab72b87-130a-4434-9fc9-a28ae85671bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357599436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.357599436
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2342182988
Short name T559
Test name
Test status
Simulation time 32738310 ps
CPU time 0.95 seconds
Started Oct 04 01:48:25 PM PDT 23
Finished Oct 04 01:48:27 PM PDT 23
Peak memory 221600 kb
Host smart-5d6105ac-ec20-4fdb-9e90-22071cd16218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342182988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2342182988
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.467114005
Short name T208
Test name
Test status
Simulation time 15958133 ps
CPU time 0.89 seconds
Started Oct 04 01:48:05 PM PDT 23
Finished Oct 04 01:48:07 PM PDT 23
Peak memory 205000 kb
Host smart-eb2d446d-0afe-4e4e-8cbd-fb7e579ac138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467114005 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.467114005
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2243615375
Short name T532
Test name
Test status
Simulation time 105652146 ps
CPU time 2.44 seconds
Started Oct 04 01:50:09 PM PDT 23
Finished Oct 04 01:50:12 PM PDT 23
Peak memory 205688 kb
Host smart-9709b471-00c1-4a4d-88be-c2f60c28dabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243615375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2243615375
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.3368873659
Short name T99
Test name
Test status
Simulation time 39862340 ps
CPU time 0.92 seconds
Started Oct 04 01:50:54 PM PDT 23
Finished Oct 04 01:50:56 PM PDT 23
Peak memory 205120 kb
Host smart-a6e6669b-97ac-4a62-a37b-d2f959ff5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368873659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3368873659
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1422332582
Short name T516
Test name
Test status
Simulation time 47324436 ps
CPU time 0.8 seconds
Started Oct 04 01:47:50 PM PDT 23
Finished Oct 04 01:47:51 PM PDT 23
Peak memory 204400 kb
Host smart-6c113439-ed2d-437c-8761-4ae466315164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422332582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1422332582
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.134688256
Short name T622
Test name
Test status
Simulation time 35616377 ps
CPU time 0.8 seconds
Started Oct 04 01:49:48 PM PDT 23
Finished Oct 04 01:49:51 PM PDT 23
Peak memory 214384 kb
Host smart-2a087b08-9d58-4e9f-95a7-7d6ef0a0de24
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134688256 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.134688256
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2107616239
Short name T63
Test name
Test status
Simulation time 31518998 ps
CPU time 0.99 seconds
Started Oct 04 01:45:47 PM PDT 23
Finished Oct 04 01:45:48 PM PDT 23
Peak memory 214660 kb
Host smart-6a94d9dc-f09a-445f-abd2-62a8e8137466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107616239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2107616239
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3896269761
Short name T53
Test name
Test status
Simulation time 30803745 ps
CPU time 1 seconds
Started Oct 04 01:48:06 PM PDT 23
Finished Oct 04 01:48:08 PM PDT 23
Peak memory 228940 kb
Host smart-e7accb7a-397f-4d86-b259-9c18098c2eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896269761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3896269761
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2439882573
Short name T101
Test name
Test status
Simulation time 68478584 ps
CPU time 1.29 seconds
Started Oct 04 01:45:00 PM PDT 23
Finished Oct 04 01:45:03 PM PDT 23
Peak memory 205180 kb
Host smart-7da252ed-c9ae-4bdb-863f-4bb52eef3439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439882573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2439882573
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.124591847
Short name T340
Test name
Test status
Simulation time 81381300 ps
CPU time 0.77 seconds
Started Oct 04 01:48:07 PM PDT 23
Finished Oct 04 01:48:09 PM PDT 23
Peak memory 214464 kb
Host smart-e53c8e7b-d5f4-495b-824b-d3d45126b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124591847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.124591847
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2624703241
Short name T652
Test name
Test status
Simulation time 15360801 ps
CPU time 0.9 seconds
Started Oct 04 01:42:55 PM PDT 23
Finished Oct 04 01:42:56 PM PDT 23
Peak memory 204844 kb
Host smart-6bc745b0-e3fd-4942-b90f-241ac405e215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624703241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2624703241
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1670746470
Short name T685
Test name
Test status
Simulation time 336760166 ps
CPU time 3.47 seconds
Started Oct 04 01:50:35 PM PDT 23
Finished Oct 04 01:50:39 PM PDT 23
Peak memory 205584 kb
Host smart-5ef8254b-0d80-4038-9423-3f2e892511af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670746470 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1670746470
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.394531239
Short name T561
Test name
Test status
Simulation time 26124728883 ps
CPU time 604.93 seconds
Started Oct 04 01:46:00 PM PDT 23
Finished Oct 04 01:56:06 PM PDT 23
Peak memory 215576 kb
Host smart-9a6150d5-a2ca-4036-a6a9-c23f5da88976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394531239 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.394531239
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3396733346
Short name T270
Test name
Test status
Simulation time 40102634 ps
CPU time 1.02 seconds
Started Oct 04 01:50:07 PM PDT 23
Finished Oct 04 01:50:09 PM PDT 23
Peak memory 205124 kb
Host smart-5c4d5c61-257d-4f84-b156-3f8da7ae8628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396733346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3396733346
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2825918787
Short name T317
Test name
Test status
Simulation time 46711375 ps
CPU time 0.86 seconds
Started Oct 04 01:48:22 PM PDT 23
Finished Oct 04 01:48:24 PM PDT 23
Peak memory 204620 kb
Host smart-6f917aa1-b306-4111-9bc9-c6fca184354f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825918787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2825918787
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2494956712
Short name T138
Test name
Test status
Simulation time 30899306 ps
CPU time 0.8 seconds
Started Oct 04 01:54:55 PM PDT 23
Finished Oct 04 01:54:56 PM PDT 23
Peak memory 214512 kb
Host smart-d4e8961b-8bbb-476d-8693-dc86702957b5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494956712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2494956712
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1951709065
Short name T297
Test name
Test status
Simulation time 45831272 ps
CPU time 0.94 seconds
Started Oct 04 01:43:04 PM PDT 23
Finished Oct 04 01:43:05 PM PDT 23
Peak memory 214616 kb
Host smart-c98e8232-40c3-41e7-af2b-060b19f68442
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951709065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1951709065
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.88212371
Short name T156
Test name
Test status
Simulation time 19106475 ps
CPU time 1.37 seconds
Started Oct 04 01:47:12 PM PDT 23
Finished Oct 04 01:47:13 PM PDT 23
Peak memory 215804 kb
Host smart-f58b49e2-804a-41bf-9964-dee76c95301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88212371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.88212371
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3961124453
Short name T293
Test name
Test status
Simulation time 27278501 ps
CPU time 0.93 seconds
Started Oct 04 01:43:03 PM PDT 23
Finished Oct 04 01:43:05 PM PDT 23
Peak memory 205504 kb
Host smart-676eca72-e1b3-4267-a023-279ffd97384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961124453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3961124453
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_smoke.2212740730
Short name T115
Test name
Test status
Simulation time 76493773 ps
CPU time 0.88 seconds
Started Oct 04 01:49:22 PM PDT 23
Finished Oct 04 01:49:24 PM PDT 23
Peak memory 204856 kb
Host smart-5140c68d-74af-4003-bf44-8672a29afe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212740730 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2212740730
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.516338423
Short name T708
Test name
Test status
Simulation time 257980320 ps
CPU time 2.44 seconds
Started Oct 04 01:50:27 PM PDT 23
Finished Oct 04 01:50:30 PM PDT 23
Peak memory 205800 kb
Host smart-bc1f2db9-debc-4f7f-96fc-dc3b247f3da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516338423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.516338423
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3668158093
Short name T550
Test name
Test status
Simulation time 136568018670 ps
CPU time 762.04 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 02:03:14 PM PDT 23
Peak memory 214820 kb
Host smart-bf83fe7a-530d-46c9-9dcc-6b51e79b49a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668158093 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3668158093
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3992582396
Short name T66
Test name
Test status
Simulation time 61790785 ps
CPU time 0.92 seconds
Started Oct 04 01:48:25 PM PDT 23
Finished Oct 04 01:48:27 PM PDT 23
Peak memory 205280 kb
Host smart-9e5995aa-2f2d-49b7-8850-c30e6f7df8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992582396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3992582396
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4171694973
Short name T462
Test name
Test status
Simulation time 55981359 ps
CPU time 0.89 seconds
Started Oct 04 01:46:16 PM PDT 23
Finished Oct 04 01:46:17 PM PDT 23
Peak memory 205456 kb
Host smart-217ac8e7-6188-4f5d-b0f5-86d9c5692229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171694973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4171694973
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1904308984
Short name T142
Test name
Test status
Simulation time 60297244 ps
CPU time 0.87 seconds
Started Oct 04 01:43:11 PM PDT 23
Finished Oct 04 01:43:13 PM PDT 23
Peak memory 214408 kb
Host smart-3f0fb5c6-4398-4705-966f-cdf6e1541593
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904308984 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1904308984
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2847725835
Short name T28
Test name
Test status
Simulation time 47448898 ps
CPU time 0.95 seconds
Started Oct 04 01:43:06 PM PDT 23
Finished Oct 04 01:43:07 PM PDT 23
Peak memory 214656 kb
Host smart-a773fe97-ad29-4080-afdb-12fd29d5d3dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847725835 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2847725835
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3455143593
Short name T472
Test name
Test status
Simulation time 23059032 ps
CPU time 0.92 seconds
Started Oct 04 01:48:12 PM PDT 23
Finished Oct 04 01:48:13 PM PDT 23
Peak memory 215692 kb
Host smart-7e0d0844-7559-4a45-bed2-00f31021d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455143593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3455143593
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.854825635
Short name T729
Test name
Test status
Simulation time 32293484 ps
CPU time 1.07 seconds
Started Oct 04 01:45:57 PM PDT 23
Finished Oct 04 01:45:59 PM PDT 23
Peak memory 204992 kb
Host smart-6936cdcd-bd32-4009-9ac6-58d69542651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854825635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.854825635
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.337484564
Short name T556
Test name
Test status
Simulation time 31160895 ps
CPU time 0.84 seconds
Started Oct 04 01:50:33 PM PDT 23
Finished Oct 04 01:50:34 PM PDT 23
Peak memory 214616 kb
Host smart-0a0daffa-57ee-4344-842e-e9980512aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337484564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.337484564
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2563776549
Short name T672
Test name
Test status
Simulation time 24263287 ps
CPU time 0.83 seconds
Started Oct 04 01:47:58 PM PDT 23
Finished Oct 04 01:48:00 PM PDT 23
Peak memory 204928 kb
Host smart-b74b0544-35ca-4653-9307-d1a086257d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563776549 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2563776549
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1932955457
Short name T278
Test name
Test status
Simulation time 95238471 ps
CPU time 2.61 seconds
Started Oct 04 01:47:58 PM PDT 23
Finished Oct 04 01:48:01 PM PDT 23
Peak memory 205600 kb
Host smart-33ddad16-6681-4cb4-94c4-465d811e31a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932955457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1932955457
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2669220401
Short name T517
Test name
Test status
Simulation time 81430320317 ps
CPU time 480.19 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 01:58:33 PM PDT 23
Peak memory 213452 kb
Host smart-84df2477-caed-4031-a030-bb3afcbfa40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669220401 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2669220401
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.700773349
Short name T67
Test name
Test status
Simulation time 21247449 ps
CPU time 1 seconds
Started Oct 04 01:48:57 PM PDT 23
Finished Oct 04 01:48:59 PM PDT 23
Peak memory 205208 kb
Host smart-bcb2fc8e-ca42-4ee0-aed5-34cd3c51543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700773349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.700773349
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2707995600
Short name T689
Test name
Test status
Simulation time 20182744 ps
CPU time 0.85 seconds
Started Oct 04 01:51:10 PM PDT 23
Finished Oct 04 01:51:12 PM PDT 23
Peak memory 204396 kb
Host smart-f2881de5-cacd-44d1-9bec-9619263e55ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707995600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2707995600
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1230309370
Short name T564
Test name
Test status
Simulation time 15419843 ps
CPU time 0.93 seconds
Started Oct 04 01:43:09 PM PDT 23
Finished Oct 04 01:43:10 PM PDT 23
Peak memory 214652 kb
Host smart-ccd2b552-354d-48ce-b532-3daf598da2e8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230309370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1230309370
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.4227082037
Short name T163
Test name
Test status
Simulation time 67919892 ps
CPU time 1.17 seconds
Started Oct 04 01:54:43 PM PDT 23
Finished Oct 04 01:54:45 PM PDT 23
Peak memory 222144 kb
Host smart-1aa60b4c-67ae-4443-b683-43b49f7e077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227082037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4227082037
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_intr.1617200220
Short name T15
Test name
Test status
Simulation time 22826948 ps
CPU time 1.07 seconds
Started Oct 04 01:48:25 PM PDT 23
Finished Oct 04 01:48:27 PM PDT 23
Peak memory 221524 kb
Host smart-b9cb44fc-2b9c-4d4a-8886-4cab7413b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617200220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1617200220
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1987185023
Short name T56
Test name
Test status
Simulation time 13097921 ps
CPU time 0.87 seconds
Started Oct 04 01:52:34 PM PDT 23
Finished Oct 04 01:52:36 PM PDT 23
Peak memory 204696 kb
Host smart-e136f8c7-fae0-41f7-8ec6-22ab28cd4eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987185023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1987185023
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1480109155
Short name T728
Test name
Test status
Simulation time 1041082290 ps
CPU time 3.07 seconds
Started Oct 04 01:54:00 PM PDT 23
Finished Oct 04 01:54:04 PM PDT 23
Peak memory 205904 kb
Host smart-323ac5c8-46a7-484d-94d7-623062efeef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480109155 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1480109155
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3667729679
Short name T533
Test name
Test status
Simulation time 91446501414 ps
CPU time 1034.4 seconds
Started Oct 04 01:45:52 PM PDT 23
Finished Oct 04 02:03:07 PM PDT 23
Peak memory 217628 kb
Host smart-aaef286a-a460-4aff-9820-5f58ac085110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667729679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3667729679
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1792898006
Short name T548
Test name
Test status
Simulation time 20665284 ps
CPU time 1.03 seconds
Started Oct 04 01:44:37 PM PDT 23
Finished Oct 04 01:44:39 PM PDT 23
Peak memory 206140 kb
Host smart-5eeb3201-343c-4462-998f-04cfc1f3da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792898006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1792898006
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3183458905
Short name T661
Test name
Test status
Simulation time 34782296 ps
CPU time 0.79 seconds
Started Oct 04 01:52:20 PM PDT 23
Finished Oct 04 01:52:21 PM PDT 23
Peak memory 204416 kb
Host smart-ae9f9131-ef5b-41a2-b425-c66df4f473d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183458905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3183458905
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1064548535
Short name T141
Test name
Test status
Simulation time 24137612 ps
CPU time 0.82 seconds
Started Oct 04 01:43:11 PM PDT 23
Finished Oct 04 01:43:13 PM PDT 23
Peak memory 214416 kb
Host smart-ca088f4d-40d0-4cd9-978d-ea87a57f802e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064548535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1064548535
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.984326457
Short name T97
Test name
Test status
Simulation time 42224802 ps
CPU time 0.99 seconds
Started Oct 04 01:53:11 PM PDT 23
Finished Oct 04 01:53:13 PM PDT 23
Peak memory 214768 kb
Host smart-18e17a63-762a-4b5f-ba10-f9c8ebea07f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984326457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.984326457
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3079494181
Short name T272
Test name
Test status
Simulation time 75648546 ps
CPU time 1.12 seconds
Started Oct 04 01:47:42 PM PDT 23
Finished Oct 04 01:47:43 PM PDT 23
Peak memory 230272 kb
Host smart-e9c76074-adf0-41ee-bc14-90342cc63371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079494181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3079494181
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1568050973
Short name T638
Test name
Test status
Simulation time 26109567 ps
CPU time 0.95 seconds
Started Oct 04 01:49:43 PM PDT 23
Finished Oct 04 01:49:45 PM PDT 23
Peak memory 204976 kb
Host smart-5e5e3c93-3b66-4152-86ab-801f5cee9212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568050973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1568050973
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3685829378
Short name T144
Test name
Test status
Simulation time 59561564 ps
CPU time 0.78 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:45 PM PDT 23
Peak memory 214724 kb
Host smart-73a9bd63-feee-4997-ba57-2caa63c7539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685829378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3685829378
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4180843090
Short name T187
Test name
Test status
Simulation time 21047284 ps
CPU time 0.82 seconds
Started Oct 04 01:47:43 PM PDT 23
Finished Oct 04 01:47:44 PM PDT 23
Peak memory 204908 kb
Host smart-35f94a3b-87d8-4d15-89a9-4223575782ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180843090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4180843090
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2540236418
Short name T510
Test name
Test status
Simulation time 42780647 ps
CPU time 1.33 seconds
Started Oct 04 01:48:06 PM PDT 23
Finished Oct 04 01:48:09 PM PDT 23
Peak memory 206184 kb
Host smart-b5ca4428-9808-4c7e-a181-f827fb1f5311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540236418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2540236418
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2164621566
Short name T250
Test name
Test status
Simulation time 574184591011 ps
CPU time 685.21 seconds
Started Oct 04 01:47:45 PM PDT 23
Finished Oct 04 01:59:11 PM PDT 23
Peak memory 214968 kb
Host smart-997df468-69f1-4a56-9287-f40dc0a31e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164621566 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2164621566
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2630564240
Short name T678
Test name
Test status
Simulation time 262792477 ps
CPU time 1.07 seconds
Started Oct 04 01:49:26 PM PDT 23
Finished Oct 04 01:49:27 PM PDT 23
Peak memory 205312 kb
Host smart-63281478-d1b0-4545-b8b8-b8272e7b1a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630564240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2630564240
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2320084096
Short name T593
Test name
Test status
Simulation time 27280251 ps
CPU time 0.92 seconds
Started Oct 04 01:43:21 PM PDT 23
Finished Oct 04 01:43:22 PM PDT 23
Peak memory 205264 kb
Host smart-d1c63461-d231-4559-a2dc-1cc35c34a604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320084096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2320084096
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3008919612
Short name T81
Test name
Test status
Simulation time 14227293 ps
CPU time 0.88 seconds
Started Oct 04 01:44:29 PM PDT 23
Finished Oct 04 01:44:30 PM PDT 23
Peak memory 214520 kb
Host smart-ba9e0c44-c44a-41bc-9769-5769da26e4db
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008919612 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3008919612
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1359940909
Short name T642
Test name
Test status
Simulation time 30799069 ps
CPU time 0.93 seconds
Started Oct 04 01:50:14 PM PDT 23
Finished Oct 04 01:50:16 PM PDT 23
Peak memory 214792 kb
Host smart-5f613d4a-0d75-4517-977c-e529c555a4f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359940909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1359940909
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1546883998
Short name T487
Test name
Test status
Simulation time 72875691 ps
CPU time 1.13 seconds
Started Oct 04 01:43:12 PM PDT 23
Finished Oct 04 01:43:14 PM PDT 23
Peak memory 222164 kb
Host smart-8edaf84e-3b58-4bf7-9f4a-18bef692cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546883998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1546883998
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3179742965
Short name T331
Test name
Test status
Simulation time 30180229 ps
CPU time 0.92 seconds
Started Oct 04 01:50:28 PM PDT 23
Finished Oct 04 01:50:29 PM PDT 23
Peak memory 205140 kb
Host smart-9522c4f4-0610-474a-b9f6-57711868d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179742965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3179742965
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.677440403
Short name T604
Test name
Test status
Simulation time 43076623 ps
CPU time 0.95 seconds
Started Oct 04 01:53:09 PM PDT 23
Finished Oct 04 01:53:10 PM PDT 23
Peak memory 221524 kb
Host smart-98602386-aba3-4736-baa2-c8e42820c7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677440403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.677440403
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.550329391
Short name T502
Test name
Test status
Simulation time 30801371 ps
CPU time 0.84 seconds
Started Oct 04 01:52:20 PM PDT 23
Finished Oct 04 01:52:22 PM PDT 23
Peak memory 204948 kb
Host smart-e3c381f7-070c-466d-8a96-93d83164a552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550329391 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.550329391
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.871274725
Short name T495
Test name
Test status
Simulation time 25454490 ps
CPU time 0.92 seconds
Started Oct 04 01:52:18 PM PDT 23
Finished Oct 04 01:52:20 PM PDT 23
Peak memory 204564 kb
Host smart-b0193451-8bce-418a-a61f-79043b4cd403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871274725 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.871274725
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3657022797
Short name T575
Test name
Test status
Simulation time 72378642224 ps
CPU time 1103.32 seconds
Started Oct 04 01:53:24 PM PDT 23
Finished Oct 04 02:11:48 PM PDT 23
Peak memory 216084 kb
Host smart-16ae06f0-d6a3-4ccf-b453-99f029446926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657022797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3657022797
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3167139906
Short name T309
Test name
Test status
Simulation time 21523657 ps
CPU time 0.95 seconds
Started Oct 04 01:51:54 PM PDT 23
Finished Oct 04 01:51:55 PM PDT 23
Peak memory 206216 kb
Host smart-67478e9f-1312-4b10-aeae-b0a69c4471cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167139906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3167139906
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2388304183
Short name T465
Test name
Test status
Simulation time 33552982 ps
CPU time 1.19 seconds
Started Oct 04 01:54:11 PM PDT 23
Finished Oct 04 01:54:12 PM PDT 23
Peak memory 205256 kb
Host smart-5df9656c-24a0-4119-ae2c-247969a20dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388304183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2388304183
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1407980647
Short name T650
Test name
Test status
Simulation time 21874905 ps
CPU time 0.85 seconds
Started Oct 04 01:42:59 PM PDT 23
Finished Oct 04 01:43:00 PM PDT 23
Peak memory 214368 kb
Host smart-e19ed341-01bc-416d-8da5-6b620f445be7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407980647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1407980647
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1520064574
Short name T720
Test name
Test status
Simulation time 35279870 ps
CPU time 0.98 seconds
Started Oct 04 01:46:25 PM PDT 23
Finished Oct 04 01:46:27 PM PDT 23
Peak memory 214756 kb
Host smart-619304c0-b3b2-4293-afaa-f13ceae81691
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520064574 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1520064574
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1941729113
Short name T637
Test name
Test status
Simulation time 31651558 ps
CPU time 0.86 seconds
Started Oct 04 01:41:27 PM PDT 23
Finished Oct 04 01:41:28 PM PDT 23
Peak memory 214396 kb
Host smart-b1b46a8a-7d63-4c7f-84c3-c00017e227ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941729113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1941729113
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1001069143
Short name T35
Test name
Test status
Simulation time 56751906 ps
CPU time 0.94 seconds
Started Oct 04 01:42:17 PM PDT 23
Finished Oct 04 01:42:19 PM PDT 23
Peak memory 204896 kb
Host smart-d486fb1f-9876-4793-b750-55545412baf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001069143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1001069143
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1430118380
Short name T490
Test name
Test status
Simulation time 41525885 ps
CPU time 0.96 seconds
Started Oct 04 01:48:37 PM PDT 23
Finished Oct 04 01:48:39 PM PDT 23
Peak memory 221460 kb
Host smart-b07c2fc4-d4d1-48b5-9046-d0f878c71b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430118380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1430118380
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_smoke.816505950
Short name T688
Test name
Test status
Simulation time 18186279 ps
CPU time 0.85 seconds
Started Oct 04 01:54:23 PM PDT 23
Finished Oct 04 01:54:25 PM PDT 23
Peak memory 204776 kb
Host smart-d6a57816-b6d3-4d25-af04-278f1db2f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816505950 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.816505950
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.604884689
Short name T568
Test name
Test status
Simulation time 779005087 ps
CPU time 2.99 seconds
Started Oct 04 01:42:20 PM PDT 23
Finished Oct 04 01:42:24 PM PDT 23
Peak memory 205472 kb
Host smart-5915a856-2bb0-4a46-920a-9f07e85c8857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604884689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.604884689
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2248482409
Short name T484
Test name
Test status
Simulation time 1749431029413 ps
CPU time 2867.29 seconds
Started Oct 04 01:41:26 PM PDT 23
Finished Oct 04 02:29:14 PM PDT 23
Peak memory 219632 kb
Host smart-70c52556-be47-4227-91ad-86452ec8f25b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248482409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2248482409
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3071147252
Short name T553
Test name
Test status
Simulation time 20768083 ps
CPU time 0.95 seconds
Started Oct 04 01:46:26 PM PDT 23
Finished Oct 04 01:46:27 PM PDT 23
Peak memory 206052 kb
Host smart-3c7de0f2-64bf-42ba-a58c-1434005dc911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071147252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3071147252
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3831431103
Short name T316
Test name
Test status
Simulation time 44925717 ps
CPU time 0.83 seconds
Started Oct 04 01:50:03 PM PDT 23
Finished Oct 04 01:50:05 PM PDT 23
Peak memory 205160 kb
Host smart-d41877cb-0b29-48b8-941b-f4b27d59e985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831431103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3831431103
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1090191755
Short name T75
Test name
Test status
Simulation time 15686942 ps
CPU time 0.84 seconds
Started Oct 04 01:52:22 PM PDT 23
Finished Oct 04 01:52:23 PM PDT 23
Peak memory 214388 kb
Host smart-aeb0f8ae-d470-464e-a376-02ea929636c7
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090191755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1090191755
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2430901157
Short name T294
Test name
Test status
Simulation time 23666534 ps
CPU time 0.95 seconds
Started Oct 04 01:45:50 PM PDT 23
Finished Oct 04 01:45:51 PM PDT 23
Peak memory 214700 kb
Host smart-09b554b9-4fc7-4b5f-8831-82b4feed7c35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430901157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2430901157
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2893758711
Short name T252
Test name
Test status
Simulation time 29330770 ps
CPU time 1.2 seconds
Started Oct 04 01:46:03 PM PDT 23
Finished Oct 04 01:46:05 PM PDT 23
Peak memory 216912 kb
Host smart-e521696d-584f-489c-8e3f-c71ad46f6926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893758711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2893758711
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1831255561
Short name T281
Test name
Test status
Simulation time 59200860 ps
CPU time 0.98 seconds
Started Oct 04 01:53:47 PM PDT 23
Finished Oct 04 01:53:50 PM PDT 23
Peak memory 205592 kb
Host smart-88eb73be-d050-4cb7-8fb3-448e5101ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831255561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1831255561
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3391864536
Short name T585
Test name
Test status
Simulation time 22722223 ps
CPU time 0.92 seconds
Started Oct 04 01:50:35 PM PDT 23
Finished Oct 04 01:50:37 PM PDT 23
Peak memory 214828 kb
Host smart-2cf91619-2337-4d7f-a5de-6591d8113d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391864536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3391864536
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1599277622
Short name T313
Test name
Test status
Simulation time 22162003 ps
CPU time 0.82 seconds
Started Oct 04 01:48:56 PM PDT 23
Finished Oct 04 01:48:57 PM PDT 23
Peak memory 204748 kb
Host smart-87fb21b9-a65c-47ed-9de7-189fc4d19b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599277622 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1599277622
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2624443415
Short name T507
Test name
Test status
Simulation time 187843197 ps
CPU time 2.51 seconds
Started Oct 04 01:54:08 PM PDT 23
Finished Oct 04 01:54:11 PM PDT 23
Peak memory 205920 kb
Host smart-d327cea7-4185-4e7d-bc73-f0cbd866fe81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624443415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2624443415
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2080805197
Short name T513
Test name
Test status
Simulation time 58796686906 ps
CPU time 375.02 seconds
Started Oct 04 01:54:08 PM PDT 23
Finished Oct 04 02:00:24 PM PDT 23
Peak memory 215796 kb
Host smart-4651ecaf-3861-407a-8c96-5ff16e79f572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080805197 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2080805197
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.794874244
Short name T17
Test name
Test status
Simulation time 30090780 ps
CPU time 0.92 seconds
Started Oct 04 01:51:00 PM PDT 23
Finished Oct 04 01:51:02 PM PDT 23
Peak memory 205212 kb
Host smart-4a287301-dd75-41f8-8708-1ce03ce5bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794874244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.794874244
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3151878531
Short name T670
Test name
Test status
Simulation time 16223971 ps
CPU time 0.89 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:49 PM PDT 23
Peak memory 204592 kb
Host smart-b7eada5f-e7fe-4b1c-9a67-f5d5a4db532a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151878531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3151878531
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.737073292
Short name T139
Test name
Test status
Simulation time 78203965 ps
CPU time 0.83 seconds
Started Oct 04 01:52:43 PM PDT 23
Finished Oct 04 01:52:45 PM PDT 23
Peak memory 214588 kb
Host smart-08239e3f-d128-46f5-8958-59e472c43c6b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737073292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.737073292
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3690781444
Short name T77
Test name
Test status
Simulation time 221998178 ps
CPU time 0.96 seconds
Started Oct 04 01:49:38 PM PDT 23
Finished Oct 04 01:49:39 PM PDT 23
Peak memory 214612 kb
Host smart-5d8b89da-cc03-47c6-b01f-b97129d8d8c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690781444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3690781444
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.344236439
Short name T682
Test name
Test status
Simulation time 18021779 ps
CPU time 1.32 seconds
Started Oct 04 01:49:30 PM PDT 23
Finished Oct 04 01:49:31 PM PDT 23
Peak memory 215604 kb
Host smart-f573a8ed-15e8-4c20-ac6f-dc5efb97afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344236439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.344236439
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2933734274
Short name T61
Test name
Test status
Simulation time 34341391 ps
CPU time 0.86 seconds
Started Oct 04 01:48:23 PM PDT 23
Finished Oct 04 01:48:24 PM PDT 23
Peak memory 205108 kb
Host smart-d1c44c35-d68f-4e0c-b78f-b3f16a815846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933734274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2933734274
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_smoke.2376656568
Short name T485
Test name
Test status
Simulation time 16854891 ps
CPU time 0.89 seconds
Started Oct 04 01:48:25 PM PDT 23
Finished Oct 04 01:48:26 PM PDT 23
Peak memory 204736 kb
Host smart-a68d88ba-e617-4c26-87af-aad5ba49bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376656568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2376656568
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.531977653
Short name T630
Test name
Test status
Simulation time 41653218 ps
CPU time 1.37 seconds
Started Oct 04 01:47:59 PM PDT 23
Finished Oct 04 01:48:01 PM PDT 23
Peak memory 205364 kb
Host smart-299f5141-445b-46b6-acdd-70d994615b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531977653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.531977653
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.165064929
Short name T337
Test name
Test status
Simulation time 100792900417 ps
CPU time 2285.67 seconds
Started Oct 04 01:48:50 PM PDT 23
Finished Oct 04 02:26:56 PM PDT 23
Peak memory 220612 kb
Host smart-0dfbd404-c7ce-404d-bcc8-c8146112bad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165064929 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.165064929
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3582678240
Short name T3
Test name
Test status
Simulation time 19487529 ps
CPU time 0.97 seconds
Started Oct 04 01:51:31 PM PDT 23
Finished Oct 04 01:51:33 PM PDT 23
Peak memory 206276 kb
Host smart-c438f36a-5f4e-420b-a0fd-01550d410697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582678240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3582678240
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3544270389
Short name T501
Test name
Test status
Simulation time 17573553 ps
CPU time 0.93 seconds
Started Oct 04 01:46:48 PM PDT 23
Finished Oct 04 01:46:50 PM PDT 23
Peak memory 204644 kb
Host smart-8b1c6feb-4c6f-4de1-85a5-925fcbf8564e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544270389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3544270389
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2695030985
Short name T179
Test name
Test status
Simulation time 47395498 ps
CPU time 0.89 seconds
Started Oct 04 01:49:37 PM PDT 23
Finished Oct 04 01:49:38 PM PDT 23
Peak memory 214500 kb
Host smart-49c42dbb-9a35-4485-b221-25249f887e08
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695030985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2695030985
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2841941796
Short name T723
Test name
Test status
Simulation time 283153906 ps
CPU time 0.97 seconds
Started Oct 04 01:49:56 PM PDT 23
Finished Oct 04 01:49:58 PM PDT 23
Peak memory 214628 kb
Host smart-81f92dd8-743f-45af-a2ed-943887387243
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841941796 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2841941796
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1562499789
Short name T210
Test name
Test status
Simulation time 19658733 ps
CPU time 1.31 seconds
Started Oct 04 01:43:28 PM PDT 23
Finished Oct 04 01:43:30 PM PDT 23
Peak memory 215568 kb
Host smart-bac1404b-6586-46b2-8386-effd434a2cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562499789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1562499789
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.924099986
Short name T609
Test name
Test status
Simulation time 13598325 ps
CPU time 0.92 seconds
Started Oct 04 01:48:05 PM PDT 23
Finished Oct 04 01:48:07 PM PDT 23
Peak memory 205008 kb
Host smart-a3f00e5a-0b04-4875-be99-23d31282d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924099986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.924099986
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.785039230
Short name T109
Test name
Test status
Simulation time 20579810 ps
CPU time 1.15 seconds
Started Oct 04 01:46:10 PM PDT 23
Finished Oct 04 01:46:12 PM PDT 23
Peak memory 225572 kb
Host smart-d9691d10-25d1-416d-933d-9536140d7f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785039230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.785039230
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.605180789
Short name T338
Test name
Test status
Simulation time 23226243 ps
CPU time 0.87 seconds
Started Oct 04 01:46:01 PM PDT 23
Finished Oct 04 01:46:03 PM PDT 23
Peak memory 204932 kb
Host smart-7d19ae5c-97c2-4215-8469-d7f8b7214ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605180789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.605180789
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.257984780
Short name T726
Test name
Test status
Simulation time 17292755987 ps
CPU time 287.59 seconds
Started Oct 04 01:50:39 PM PDT 23
Finished Oct 04 01:55:28 PM PDT 23
Peak memory 215852 kb
Host smart-8b40be30-82bd-475f-8fc7-476b739f6934
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257984780 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.257984780
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.4203822407
Short name T645
Test name
Test status
Simulation time 36412861 ps
CPU time 1.04 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:47 PM PDT 23
Peak memory 204788 kb
Host smart-09f169f9-4ec5-4e93-9adf-9aaf58cff2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203822407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4203822407
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4241162081
Short name T87
Test name
Test status
Simulation time 12266581 ps
CPU time 0.87 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:45 PM PDT 23
Peak memory 214504 kb
Host smart-6a2330dc-7dca-4bbc-9d4d-d519a09e1ea5
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241162081 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4241162081
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1858160469
Short name T98
Test name
Test status
Simulation time 106371296 ps
CPU time 0.96 seconds
Started Oct 04 01:50:11 PM PDT 23
Finished Oct 04 01:50:12 PM PDT 23
Peak memory 214696 kb
Host smart-fdb7a389-a1b8-414f-9308-37f15271f2e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858160469 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1858160469
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.692865626
Short name T14
Test name
Test status
Simulation time 30694219 ps
CPU time 0.95 seconds
Started Oct 04 01:52:00 PM PDT 23
Finished Oct 04 01:52:02 PM PDT 23
Peak memory 222188 kb
Host smart-35623bed-c7e6-47dc-a9a0-ea7337f557d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692865626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.692865626
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2542299178
Short name T42
Test name
Test status
Simulation time 70965046 ps
CPU time 1 seconds
Started Oct 04 01:46:00 PM PDT 23
Finished Oct 04 01:46:02 PM PDT 23
Peak memory 205260 kb
Host smart-104b01b9-4046-4f33-9463-bb6ede1c5d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542299178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2542299178
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.129218155
Short name T113
Test name
Test status
Simulation time 18151741 ps
CPU time 1.04 seconds
Started Oct 04 01:43:45 PM PDT 23
Finished Oct 04 01:43:46 PM PDT 23
Peak memory 214800 kb
Host smart-7f3e75ec-e730-4856-8ee3-224a6dcf46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129218155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.129218155
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2211484252
Short name T664
Test name
Test status
Simulation time 48546882 ps
CPU time 0.95 seconds
Started Oct 04 01:48:03 PM PDT 23
Finished Oct 04 01:48:04 PM PDT 23
Peak memory 204924 kb
Host smart-826c0f93-75f5-4751-b9b3-a6b6353a7aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211484252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2211484252
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2317558187
Short name T504
Test name
Test status
Simulation time 1535339780 ps
CPU time 4.87 seconds
Started Oct 04 01:53:43 PM PDT 23
Finished Oct 04 01:53:49 PM PDT 23
Peak memory 206208 kb
Host smart-cf3eaf7e-d44b-4a01-bbf4-dbd687236ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317558187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2317558187
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3582398488
Short name T184
Test name
Test status
Simulation time 78235222080 ps
CPU time 437.13 seconds
Started Oct 04 01:43:44 PM PDT 23
Finished Oct 04 01:51:02 PM PDT 23
Peak memory 215028 kb
Host smart-b7fa73e7-62d3-418c-b218-f33d65df156a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582398488 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3582398488
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1146509504
Short name T311
Test name
Test status
Simulation time 31811263 ps
CPU time 1.02 seconds
Started Oct 04 01:54:23 PM PDT 23
Finished Oct 04 01:54:25 PM PDT 23
Peak memory 206108 kb
Host smart-6eafa03e-ebea-4d04-a82e-990eff821284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146509504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1146509504
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1479094788
Short name T719
Test name
Test status
Simulation time 14370455 ps
CPU time 0.85 seconds
Started Oct 04 01:43:43 PM PDT 23
Finished Oct 04 01:43:44 PM PDT 23
Peak memory 205160 kb
Host smart-26cdf822-204a-4800-a2c3-d4d81b179948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479094788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1479094788
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.289442750
Short name T134
Test name
Test status
Simulation time 18953664 ps
CPU time 0.88 seconds
Started Oct 04 01:47:41 PM PDT 23
Finished Oct 04 01:47:42 PM PDT 23
Peak memory 214488 kb
Host smart-e8aa8c29-31eb-4939-9343-4ec59f642674
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289442750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.289442750
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3589267627
Short name T158
Test name
Test status
Simulation time 46501970 ps
CPU time 0.98 seconds
Started Oct 04 01:54:34 PM PDT 23
Finished Oct 04 01:54:35 PM PDT 23
Peak memory 214768 kb
Host smart-74e338ea-c74b-4d1b-998b-5aa5e9e92e06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589267627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3589267627
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1281366173
Short name T255
Test name
Test status
Simulation time 54372580 ps
CPU time 1 seconds
Started Oct 04 01:52:12 PM PDT 23
Finished Oct 04 01:52:14 PM PDT 23
Peak memory 228564 kb
Host smart-01da4131-e3e5-4eae-95c6-e2989611b61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281366173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1281366173
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1879096037
Short name T629
Test name
Test status
Simulation time 80925096 ps
CPU time 1.14 seconds
Started Oct 04 01:45:51 PM PDT 23
Finished Oct 04 01:45:53 PM PDT 23
Peak memory 214404 kb
Host smart-a7bf9a40-95fb-4584-86c7-8f89280fcf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879096037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1879096037
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.452128333
Short name T48
Test name
Test status
Simulation time 19716414 ps
CPU time 1.15 seconds
Started Oct 04 01:48:14 PM PDT 23
Finished Oct 04 01:48:17 PM PDT 23
Peak memory 221776 kb
Host smart-4c9c46aa-2c00-4718-a3d7-5e5ae60b679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452128333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.452128333
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1150053266
Short name T508
Test name
Test status
Simulation time 24728779 ps
CPU time 0.88 seconds
Started Oct 04 01:46:03 PM PDT 23
Finished Oct 04 01:46:04 PM PDT 23
Peak memory 205024 kb
Host smart-0378806b-19f1-4270-857d-d7410c69720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150053266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1150053266
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1286704308
Short name T541
Test name
Test status
Simulation time 115172962 ps
CPU time 1.35 seconds
Started Oct 04 01:45:32 PM PDT 23
Finished Oct 04 01:45:34 PM PDT 23
Peak memory 206148 kb
Host smart-cb74604f-f136-4b4b-8450-aff2c16fdb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286704308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1286704308
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2072684012
Short name T22
Test name
Test status
Simulation time 35592136528 ps
CPU time 930.64 seconds
Started Oct 04 01:43:29 PM PDT 23
Finished Oct 04 01:59:00 PM PDT 23
Peak memory 215128 kb
Host smart-07deac99-c24f-488c-8b8f-a468379a5364
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072684012 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2072684012
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1370499438
Short name T701
Test name
Test status
Simulation time 36069761 ps
CPU time 0.98 seconds
Started Oct 04 01:46:28 PM PDT 23
Finished Oct 04 01:46:31 PM PDT 23
Peak memory 206196 kb
Host smart-76295f79-b657-4866-8a4a-ed1e610f6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370499438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1370499438
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2865158486
Short name T506
Test name
Test status
Simulation time 60668865 ps
CPU time 0.8 seconds
Started Oct 04 01:46:28 PM PDT 23
Finished Oct 04 01:46:30 PM PDT 23
Peak memory 205132 kb
Host smart-156c11f3-03f5-4385-80a8-a3c364b7d46b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865158486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2865158486
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3620830556
Short name T85
Test name
Test status
Simulation time 12251599 ps
CPU time 0.88 seconds
Started Oct 04 01:49:10 PM PDT 23
Finished Oct 04 01:49:11 PM PDT 23
Peak memory 214536 kb
Host smart-26852906-8de9-41b7-8b7b-214c43548b0b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620830556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3620830556
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1264468594
Short name T148
Test name
Test status
Simulation time 84677616 ps
CPU time 1.04 seconds
Started Oct 04 01:49:44 PM PDT 23
Finished Oct 04 01:49:47 PM PDT 23
Peak memory 214672 kb
Host smart-cb43ce3a-c2e2-4843-ada7-5e51ce479b90
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264468594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1264468594
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1634660809
Short name T525
Test name
Test status
Simulation time 68238244 ps
CPU time 1.01 seconds
Started Oct 04 01:46:23 PM PDT 23
Finished Oct 04 01:46:25 PM PDT 23
Peak memory 216976 kb
Host smart-7d1bbb39-95fc-497a-91ef-440a920cf8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634660809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1634660809
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.575266764
Short name T574
Test name
Test status
Simulation time 16648495 ps
CPU time 1.02 seconds
Started Oct 04 01:48:18 PM PDT 23
Finished Oct 04 01:48:19 PM PDT 23
Peak memory 205284 kb
Host smart-b7a6bec5-0de2-4503-8212-d1a95e963142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575266764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.575266764
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.553964370
Short name T34
Test name
Test status
Simulation time 27997157 ps
CPU time 0.97 seconds
Started Oct 04 01:46:27 PM PDT 23
Finished Oct 04 01:46:30 PM PDT 23
Peak memory 225516 kb
Host smart-c65b0052-ee83-40b2-b3ad-8d872709ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553964370 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.553964370
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1461852347
Short name T594
Test name
Test status
Simulation time 36630871 ps
CPU time 0.81 seconds
Started Oct 04 01:50:53 PM PDT 23
Finished Oct 04 01:50:55 PM PDT 23
Peak memory 204688 kb
Host smart-18475657-66ce-4516-b27e-aec256407522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461852347 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1461852347
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2952553017
Short name T662
Test name
Test status
Simulation time 38835707 ps
CPU time 1.32 seconds
Started Oct 04 01:46:24 PM PDT 23
Finished Oct 04 01:46:26 PM PDT 23
Peak memory 205208 kb
Host smart-a9620eef-8a4b-495f-b0bb-0c9d3b36127b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952553017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2952553017
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3298341589
Short name T344
Test name
Test status
Simulation time 8363843877 ps
CPU time 196.24 seconds
Started Oct 04 01:52:02 PM PDT 23
Finished Oct 04 01:55:18 PM PDT 23
Peak memory 215084 kb
Host smart-51aeff08-5c6c-41ab-ab04-74ae66494ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298341589 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3298341589
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3887143602
Short name T551
Test name
Test status
Simulation time 38092813 ps
CPU time 0.98 seconds
Started Oct 04 01:55:48 PM PDT 23
Finished Oct 04 01:55:50 PM PDT 23
Peak memory 205356 kb
Host smart-27d4ffb0-4184-43ad-84f8-00799fe6f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887143602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3887143602
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1478797663
Short name T321
Test name
Test status
Simulation time 13761478 ps
CPU time 0.87 seconds
Started Oct 04 01:48:30 PM PDT 23
Finished Oct 04 01:48:32 PM PDT 23
Peak memory 204608 kb
Host smart-7809e95c-2f6e-40fc-b72f-bfd81ce80ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478797663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1478797663
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1179831073
Short name T704
Test name
Test status
Simulation time 31292441 ps
CPU time 0.82 seconds
Started Oct 04 01:48:02 PM PDT 23
Finished Oct 04 01:48:03 PM PDT 23
Peak memory 214432 kb
Host smart-2f58d727-c9ce-4dd4-a37a-c56cd0334bf4
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179831073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1179831073
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.820891183
Short name T126
Test name
Test status
Simulation time 64117717 ps
CPU time 0.97 seconds
Started Oct 04 01:48:21 PM PDT 23
Finished Oct 04 01:48:23 PM PDT 23
Peak memory 214784 kb
Host smart-357a599c-585e-49ba-9897-6a366b989b2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820891183 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.820891183
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2759397796
Short name T543
Test name
Test status
Simulation time 21621938 ps
CPU time 0.97 seconds
Started Oct 04 01:46:26 PM PDT 23
Finished Oct 04 01:46:27 PM PDT 23
Peak memory 215936 kb
Host smart-4ac15dbe-68e9-4868-8172-a3aeac666a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759397796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2759397796
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1079876693
Short name T23
Test name
Test status
Simulation time 22121723 ps
CPU time 1.13 seconds
Started Oct 04 01:47:56 PM PDT 23
Finished Oct 04 01:47:57 PM PDT 23
Peak memory 205172 kb
Host smart-3555caf9-7309-4ece-b630-722b015005c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079876693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1079876693
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.915441421
Short name T325
Test name
Test status
Simulation time 44760822 ps
CPU time 0.8 seconds
Started Oct 04 01:46:28 PM PDT 23
Finished Oct 04 01:46:30 PM PDT 23
Peak memory 214668 kb
Host smart-5da5a0af-208b-4983-a5da-cee56e84a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915441421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.915441421
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1415585590
Short name T705
Test name
Test status
Simulation time 16196237 ps
CPU time 0.93 seconds
Started Oct 04 01:54:35 PM PDT 23
Finished Oct 04 01:54:37 PM PDT 23
Peak memory 204912 kb
Host smart-31a99a76-dc03-4e4e-b81f-78f7028d8df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415585590 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1415585590
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.793032208
Short name T625
Test name
Test status
Simulation time 146357293 ps
CPU time 3.01 seconds
Started Oct 04 01:49:50 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 206120 kb
Host smart-d8c39cb2-93bc-4411-850e-58455bbed23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793032208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.793032208
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2240063434
Short name T478
Test name
Test status
Simulation time 127212324494 ps
CPU time 1587.46 seconds
Started Oct 04 01:48:11 PM PDT 23
Finished Oct 04 02:14:39 PM PDT 23
Peak memory 219640 kb
Host smart-b41c6873-0599-41c9-b936-084073864fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240063434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2240063434
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1893833486
Short name T267
Test name
Test status
Simulation time 137599767 ps
CPU time 0.94 seconds
Started Oct 04 01:46:29 PM PDT 23
Finished Oct 04 01:46:31 PM PDT 23
Peak memory 205112 kb
Host smart-53cb9078-80ca-448f-a639-6c01c0da792a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893833486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1893833486
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1403674617
Short name T335
Test name
Test status
Simulation time 95828157 ps
CPU time 0.96 seconds
Started Oct 04 01:46:20 PM PDT 23
Finished Oct 04 01:46:22 PM PDT 23
Peak memory 204660 kb
Host smart-2ae79b49-84e2-493a-b738-e46c6a44fdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403674617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1403674617
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1466489079
Short name T251
Test name
Test status
Simulation time 21380893 ps
CPU time 1.03 seconds
Started Oct 04 01:48:56 PM PDT 23
Finished Oct 04 01:48:58 PM PDT 23
Peak memory 214568 kb
Host smart-28387a8f-8ce8-41c6-9dd5-a6e4ca3289db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466489079 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1466489079
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.916925945
Short name T171
Test name
Test status
Simulation time 22697215 ps
CPU time 0.92 seconds
Started Oct 04 01:46:29 PM PDT 23
Finished Oct 04 01:46:31 PM PDT 23
Peak memory 221316 kb
Host smart-a6b4e5c9-12cf-4be8-a6c0-17ebed1980aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916925945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.916925945
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4079630403
Short name T71
Test name
Test status
Simulation time 74780235 ps
CPU time 1.03 seconds
Started Oct 04 01:51:22 PM PDT 23
Finished Oct 04 01:51:23 PM PDT 23
Peak memory 205164 kb
Host smart-c4abbaa8-e258-4503-8201-f25ec435902b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079630403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4079630403
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.709238623
Short name T657
Test name
Test status
Simulation time 19681359 ps
CPU time 1.03 seconds
Started Oct 04 01:50:58 PM PDT 23
Finished Oct 04 01:51:00 PM PDT 23
Peak memory 214452 kb
Host smart-1985eec4-c135-4cde-8a6c-24c3a048d2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709238623 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.709238623
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.349483466
Short name T460
Test name
Test status
Simulation time 23826353 ps
CPU time 0.88 seconds
Started Oct 04 01:46:23 PM PDT 23
Finished Oct 04 01:46:25 PM PDT 23
Peak memory 204812 kb
Host smart-a99066c0-9ffa-4924-92e5-24d663b0c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349483466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.349483466
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.810166975
Short name T647
Test name
Test status
Simulation time 896355892 ps
CPU time 4.1 seconds
Started Oct 04 01:49:47 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 205908 kb
Host smart-e2817b94-7d00-41f0-a66a-93982fd390af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810166975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.810166975
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3232630008
Short name T694
Test name
Test status
Simulation time 28292034681 ps
CPU time 359.15 seconds
Started Oct 04 01:46:25 PM PDT 23
Finished Oct 04 01:52:24 PM PDT 23
Peak memory 214852 kb
Host smart-ac121ace-cd61-4661-999b-3428d32af9e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232630008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3232630008
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1105286493
Short name T100
Test name
Test status
Simulation time 20835398 ps
CPU time 0.99 seconds
Started Oct 04 01:46:29 PM PDT 23
Finished Oct 04 01:46:31 PM PDT 23
Peak memory 206136 kb
Host smart-76263095-c61b-40b4-abff-20b4c67d9178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105286493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1105286493
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3044217832
Short name T700
Test name
Test status
Simulation time 46157454 ps
CPU time 0.93 seconds
Started Oct 04 01:46:31 PM PDT 23
Finished Oct 04 01:46:32 PM PDT 23
Peak memory 204744 kb
Host smart-fd96eff5-04c6-4663-8bfe-1af2513ffb20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044217832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3044217832
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2285977357
Short name T143
Test name
Test status
Simulation time 75819373 ps
CPU time 0.87 seconds
Started Oct 04 01:46:31 PM PDT 23
Finished Oct 04 01:46:32 PM PDT 23
Peak memory 214616 kb
Host smart-8651f260-cf54-4419-8c51-8f5e8c3760d2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285977357 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2285977357
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3075210487
Short name T488
Test name
Test status
Simulation time 236265576 ps
CPU time 0.99 seconds
Started Oct 04 01:46:28 PM PDT 23
Finished Oct 04 01:46:31 PM PDT 23
Peak memory 214768 kb
Host smart-d737892a-8a48-4df5-ac5d-ef0e2666b57f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075210487 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3075210487
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4210139129
Short name T249
Test name
Test status
Simulation time 30031467 ps
CPU time 1.04 seconds
Started Oct 04 01:50:39 PM PDT 23
Finished Oct 04 01:50:41 PM PDT 23
Peak memory 214540 kb
Host smart-014d8752-239f-4690-a39c-e6add68ddf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210139129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4210139129
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.859235766
Short name T686
Test name
Test status
Simulation time 27687967 ps
CPU time 1.29 seconds
Started Oct 04 01:54:34 PM PDT 23
Finished Oct 04 01:54:36 PM PDT 23
Peak memory 214400 kb
Host smart-34b5c246-272f-4c54-a01e-b4b0a703555d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859235766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.859235766
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2659155939
Short name T114
Test name
Test status
Simulation time 40751595 ps
CPU time 0.82 seconds
Started Oct 04 01:46:28 PM PDT 23
Finished Oct 04 01:46:30 PM PDT 23
Peak memory 214672 kb
Host smart-943a0f03-68ad-44e5-a7e1-5a3d29b1de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659155939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2659155939
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.134689542
Short name T722
Test name
Test status
Simulation time 25281994 ps
CPU time 0.91 seconds
Started Oct 04 01:49:13 PM PDT 23
Finished Oct 04 01:49:15 PM PDT 23
Peak memory 204996 kb
Host smart-32d364cc-052a-4abc-8160-39ac1d69d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134689542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.134689542
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3337827672
Short name T322
Test name
Test status
Simulation time 342638590 ps
CPU time 3.59 seconds
Started Oct 04 01:54:47 PM PDT 23
Finished Oct 04 01:54:51 PM PDT 23
Peak memory 205952 kb
Host smart-52caac08-2d60-4207-8f44-d32c88050660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337827672 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3337827672
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1743503383
Short name T274
Test name
Test status
Simulation time 16538064259 ps
CPU time 407.98 seconds
Started Oct 04 01:54:46 PM PDT 23
Finished Oct 04 02:01:34 PM PDT 23
Peak memory 215244 kb
Host smart-cfe49a70-13bf-4227-97da-29a420b442e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743503383 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1743503383
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2105298164
Short name T648
Test name
Test status
Simulation time 18317040 ps
CPU time 0.97 seconds
Started Oct 04 01:50:27 PM PDT 23
Finished Oct 04 01:50:29 PM PDT 23
Peak memory 205136 kb
Host smart-65664986-a24d-45b4-b43c-cd308fd291a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105298164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2105298164
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.804020918
Short name T480
Test name
Test status
Simulation time 18489690 ps
CPU time 0.93 seconds
Started Oct 04 01:49:54 PM PDT 23
Finished Oct 04 01:49:57 PM PDT 23
Peak memory 204600 kb
Host smart-551f8569-4c44-44f3-b977-31c857dd7080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804020918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.804020918
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3706289834
Short name T133
Test name
Test status
Simulation time 19749622 ps
CPU time 0.81 seconds
Started Oct 04 01:46:48 PM PDT 23
Finished Oct 04 01:46:49 PM PDT 23
Peak memory 214348 kb
Host smart-55257896-7a7b-4fdd-8031-22bfbe39325a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706289834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3706289834
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1686064015
Short name T343
Test name
Test status
Simulation time 69634569 ps
CPU time 0.94 seconds
Started Oct 04 01:50:58 PM PDT 23
Finished Oct 04 01:51:00 PM PDT 23
Peak memory 214652 kb
Host smart-9fe5cc61-ab61-4660-bf0b-341fbb692563
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686064015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1686064015
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.137246919
Short name T246
Test name
Test status
Simulation time 42854970 ps
CPU time 1.07 seconds
Started Oct 04 01:49:54 PM PDT 23
Finished Oct 04 01:49:56 PM PDT 23
Peak memory 216888 kb
Host smart-98b72050-e855-45fa-89db-258de3187aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137246919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.137246919
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2153444004
Short name T583
Test name
Test status
Simulation time 186899803 ps
CPU time 1.04 seconds
Started Oct 04 01:46:18 PM PDT 23
Finished Oct 04 01:46:20 PM PDT 23
Peak memory 205176 kb
Host smart-03b9122c-91a2-47ac-89a1-f4284664e23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153444004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2153444004
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3842829482
Short name T663
Test name
Test status
Simulation time 36923764 ps
CPU time 0.83 seconds
Started Oct 04 01:46:26 PM PDT 23
Finished Oct 04 01:46:27 PM PDT 23
Peak memory 214320 kb
Host smart-8a75c300-9bf7-4b82-8dda-67961a1ea3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842829482 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3842829482
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.398787378
Short name T544
Test name
Test status
Simulation time 12449604 ps
CPU time 0.85 seconds
Started Oct 04 01:49:06 PM PDT 23
Finished Oct 04 01:49:08 PM PDT 23
Peak memory 204816 kb
Host smart-026d63f7-3462-4bf0-9d07-224baf5c6c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398787378 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.398787378
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.384019348
Short name T44
Test name
Test status
Simulation time 125576893 ps
CPU time 1.6 seconds
Started Oct 04 01:48:46 PM PDT 23
Finished Oct 04 01:48:48 PM PDT 23
Peak memory 205556 kb
Host smart-dc95984b-1cbd-4b83-84c5-3188461b8536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384019348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.384019348
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3755022124
Short name T183
Test name
Test status
Simulation time 280892793562 ps
CPU time 2039.23 seconds
Started Oct 04 01:49:53 PM PDT 23
Finished Oct 04 02:23:54 PM PDT 23
Peak memory 221956 kb
Host smart-e4b112e3-a980-4535-9e49-7b7bc22dfe0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755022124 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3755022124
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3986355244
Short name T269
Test name
Test status
Simulation time 62467830 ps
CPU time 0.92 seconds
Started Oct 04 01:42:30 PM PDT 23
Finished Oct 04 01:42:32 PM PDT 23
Peak memory 206064 kb
Host smart-ab1a4dd6-b122-4a69-8e07-94d337719218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986355244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3986355244
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1359359160
Short name T471
Test name
Test status
Simulation time 63576166 ps
CPU time 0.93 seconds
Started Oct 04 01:53:01 PM PDT 23
Finished Oct 04 01:53:03 PM PDT 23
Peak memory 204788 kb
Host smart-26bfa00f-d8b4-49ae-baf6-2e3e6ed7f8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359359160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1359359160
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2636814963
Short name T496
Test name
Test status
Simulation time 20711491 ps
CPU time 0.85 seconds
Started Oct 04 01:52:41 PM PDT 23
Finished Oct 04 01:52:43 PM PDT 23
Peak memory 214424 kb
Host smart-3334111a-14b8-4b04-91fe-25ea64504b00
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636814963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2636814963
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.2973853582
Short name T31
Test name
Test status
Simulation time 25480481 ps
CPU time 0.94 seconds
Started Oct 04 01:46:01 PM PDT 23
Finished Oct 04 01:46:02 PM PDT 23
Peak memory 215772 kb
Host smart-8184db1a-3287-44c7-82ec-42c5508081d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973853582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2973853582
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_intr.942202692
Short name T140
Test name
Test status
Simulation time 22560382 ps
CPU time 0.89 seconds
Started Oct 04 01:47:35 PM PDT 23
Finished Oct 04 01:47:36 PM PDT 23
Peak memory 214532 kb
Host smart-a17dc44e-872c-4de0-89b4-017b3fd9e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942202692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.942202692
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2991819124
Short name T699
Test name
Test status
Simulation time 21398626 ps
CPU time 0.87 seconds
Started Oct 04 01:44:04 PM PDT 23
Finished Oct 04 01:44:06 PM PDT 23
Peak memory 204712 kb
Host smart-f7881ea1-d9a2-4fb0-8315-a987590605c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991819124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2991819124
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.810702575
Short name T618
Test name
Test status
Simulation time 44265303 ps
CPU time 0.83 seconds
Started Oct 04 01:50:35 PM PDT 23
Finished Oct 04 01:50:36 PM PDT 23
Peak memory 204920 kb
Host smart-076cd12b-ef4b-4c7e-bcce-6766d080f435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810702575 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.810702575
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1651995067
Short name T467
Test name
Test status
Simulation time 40711221 ps
CPU time 0.97 seconds
Started Oct 04 01:44:09 PM PDT 23
Finished Oct 04 01:44:11 PM PDT 23
Peak memory 204308 kb
Host smart-8e0dc3f2-0b79-4c02-9b45-dbefb042052d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651995067 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1651995067
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1850133491
Short name T607
Test name
Test status
Simulation time 261103452734 ps
CPU time 2739.26 seconds
Started Oct 04 01:49:54 PM PDT 23
Finished Oct 04 02:35:35 PM PDT 23
Peak memory 223740 kb
Host smart-e734e17d-80b1-4c4a-920c-ca9c55aa3564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850133491 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1850133491
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2332404172
Short name T598
Test name
Test status
Simulation time 40522316 ps
CPU time 0.92 seconds
Started Oct 04 01:49:52 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 215692 kb
Host smart-e07b5b95-60e2-4a15-9ea2-9ea2489e8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332404172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2332404172
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.3139898275
Short name T146
Test name
Test status
Simulation time 33335980 ps
CPU time 1.1 seconds
Started Oct 04 01:49:48 PM PDT 23
Finished Oct 04 01:49:51 PM PDT 23
Peak memory 214500 kb
Host smart-71cb407e-ea32-4b35-877a-ebe41f017263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139898275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3139898275
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.2422644676
Short name T258
Test name
Test status
Simulation time 20030232 ps
CPU time 1.41 seconds
Started Oct 04 01:46:31 PM PDT 23
Finished Oct 04 01:46:33 PM PDT 23
Peak memory 214700 kb
Host smart-93af1025-a69f-4fac-96d1-f44256d1eac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422644676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2422644676
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.2581393997
Short name T724
Test name
Test status
Simulation time 35489651 ps
CPU time 0.81 seconds
Started Oct 04 01:49:53 PM PDT 23
Finished Oct 04 01:49:56 PM PDT 23
Peak memory 215376 kb
Host smart-5c87d99b-3343-48b7-8013-0503ba47ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581393997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2581393997
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.1818108057
Short name T119
Test name
Test status
Simulation time 18354600 ps
CPU time 1.25 seconds
Started Oct 04 01:46:26 PM PDT 23
Finished Oct 04 01:46:28 PM PDT 23
Peak memory 215920 kb
Host smart-7dad10a7-1822-4337-9dee-543b5b5e172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818108057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1818108057
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.428428001
Short name T620
Test name
Test status
Simulation time 22442509 ps
CPU time 0.96 seconds
Started Oct 04 01:50:48 PM PDT 23
Finished Oct 04 01:50:50 PM PDT 23
Peak memory 214644 kb
Host smart-33068e48-7226-4f17-8bc7-a488f11c8ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428428001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.428428001
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.3478411897
Short name T150
Test name
Test status
Simulation time 68595014 ps
CPU time 0.93 seconds
Started Oct 04 01:54:46 PM PDT 23
Finished Oct 04 01:54:48 PM PDT 23
Peak memory 214412 kb
Host smart-f336c6d4-2491-4001-a4d8-220a6d39aa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478411897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3478411897
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.1211507924
Short name T479
Test name
Test status
Simulation time 21824625 ps
CPU time 1 seconds
Started Oct 04 01:49:03 PM PDT 23
Finished Oct 04 01:49:04 PM PDT 23
Peak memory 215676 kb
Host smart-ca1b68bf-d24a-4e29-a48e-b19e0f9ecac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211507924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1211507924
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.4109265311
Short name T655
Test name
Test status
Simulation time 58289165 ps
CPU time 1.01 seconds
Started Oct 04 01:48:09 PM PDT 23
Finished Oct 04 01:48:12 PM PDT 23
Peak memory 215784 kb
Host smart-f23c50e3-098f-4dd2-9a65-b32d00e74a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109265311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4109265311
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.1562576541
Short name T640
Test name
Test status
Simulation time 22933830 ps
CPU time 0.85 seconds
Started Oct 04 01:53:24 PM PDT 23
Finished Oct 04 01:53:26 PM PDT 23
Peak memory 215448 kb
Host smart-37930ac3-8b29-483a-889b-dcd9cd7f3170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562576541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1562576541
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.1960688845
Short name T302
Test name
Test status
Simulation time 37530436 ps
CPU time 0.98 seconds
Started Oct 04 01:50:32 PM PDT 23
Finished Oct 04 01:50:34 PM PDT 23
Peak memory 205092 kb
Host smart-ff0232c6-119f-4166-88d3-ae04094f83c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960688845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1960688845
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3519918496
Short name T565
Test name
Test status
Simulation time 53098100 ps
CPU time 0.73 seconds
Started Oct 04 01:51:13 PM PDT 23
Finished Oct 04 01:51:14 PM PDT 23
Peak memory 204268 kb
Host smart-36d4478d-9a35-413d-ae6c-52a99000929c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519918496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3519918496
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3948854129
Short name T261
Test name
Test status
Simulation time 22221522 ps
CPU time 0.86 seconds
Started Oct 04 01:51:12 PM PDT 23
Finished Oct 04 01:51:13 PM PDT 23
Peak memory 214316 kb
Host smart-8f20664a-7b5c-47b7-91b6-7108a2eac3bb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948854129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3948854129
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.376949629
Short name T295
Test name
Test status
Simulation time 21158982 ps
CPU time 0.98 seconds
Started Oct 04 01:42:29 PM PDT 23
Finished Oct 04 01:42:30 PM PDT 23
Peak memory 214524 kb
Host smart-4c393bdc-ff82-4503-aac1-3ae262ae2c8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376949629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.376949629
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1622417238
Short name T259
Test name
Test status
Simulation time 33247651 ps
CPU time 0.82 seconds
Started Oct 04 01:43:54 PM PDT 23
Finished Oct 04 01:43:55 PM PDT 23
Peak memory 215340 kb
Host smart-305033e3-34e5-4ae5-aaf6-99130016b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622417238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1622417238
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_intr.288046682
Short name T497
Test name
Test status
Simulation time 66954319 ps
CPU time 0.93 seconds
Started Oct 04 01:42:51 PM PDT 23
Finished Oct 04 01:42:53 PM PDT 23
Peak memory 221944 kb
Host smart-73030d63-12d1-4b9b-8635-96bd04357b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288046682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.288046682
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.1300750307
Short name T514
Test name
Test status
Simulation time 34338884 ps
CPU time 0.83 seconds
Started Oct 04 01:53:42 PM PDT 23
Finished Oct 04 01:53:44 PM PDT 23
Peak memory 204736 kb
Host smart-e8e46d9d-b771-47c7-9ef6-c30eaacf9f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300750307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1300750307
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2615094058
Short name T500
Test name
Test status
Simulation time 333747115 ps
CPU time 2.25 seconds
Started Oct 04 01:41:35 PM PDT 23
Finished Oct 04 01:41:38 PM PDT 23
Peak memory 205692 kb
Host smart-aa071dec-f610-491a-9f4a-bdeecec96adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615094058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2615094058
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3390296544
Short name T273
Test name
Test status
Simulation time 30783089576 ps
CPU time 728.75 seconds
Started Oct 04 01:44:00 PM PDT 23
Finished Oct 04 01:56:09 PM PDT 23
Peak memory 215612 kb
Host smart-97e0f780-025d-40e7-bdd6-531dd15c57fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390296544 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3390296544
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2579707968
Short name T677
Test name
Test status
Simulation time 30136167 ps
CPU time 0.93 seconds
Started Oct 04 01:50:03 PM PDT 23
Finished Oct 04 01:50:05 PM PDT 23
Peak memory 221316 kb
Host smart-734113b2-d369-4219-994b-b97f1bdf3178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579707968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2579707968
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.527898907
Short name T596
Test name
Test status
Simulation time 69544041 ps
CPU time 0.98 seconds
Started Oct 04 01:49:41 PM PDT 23
Finished Oct 04 01:49:43 PM PDT 23
Peak memory 221204 kb
Host smart-28981bc5-a329-46e4-9fef-c0ffb0fc8fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527898907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.527898907
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.4236163380
Short name T145
Test name
Test status
Simulation time 70984666 ps
CPU time 0.95 seconds
Started Oct 04 01:46:26 PM PDT 23
Finished Oct 04 01:46:28 PM PDT 23
Peak memory 214412 kb
Host smart-db0cdc95-bd0a-4b0f-9f53-83da883fba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236163380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.4236163380
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.4078953895
Short name T167
Test name
Test status
Simulation time 105993851 ps
CPU time 0.87 seconds
Started Oct 04 01:54:58 PM PDT 23
Finished Oct 04 01:54:59 PM PDT 23
Peak memory 221248 kb
Host smart-b62868d6-28e5-4058-ab1b-ec22b3c38969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078953895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4078953895
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.3000014235
Short name T6
Test name
Test status
Simulation time 45992478 ps
CPU time 0.98 seconds
Started Oct 04 01:51:42 PM PDT 23
Finished Oct 04 01:51:44 PM PDT 23
Peak memory 215664 kb
Host smart-8ca9042f-f6b4-4f3d-8242-9b00917ca864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000014235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3000014235
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.843124481
Short name T209
Test name
Test status
Simulation time 19979503 ps
CPU time 1.04 seconds
Started Oct 04 01:46:46 PM PDT 23
Finished Oct 04 01:46:48 PM PDT 23
Peak memory 215488 kb
Host smart-4665d7b2-672c-424f-bc92-0bdd83286e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843124481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.843124481
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.212466008
Short name T588
Test name
Test status
Simulation time 22583576 ps
CPU time 1 seconds
Started Oct 04 01:48:25 PM PDT 23
Finished Oct 04 01:48:27 PM PDT 23
Peak memory 215664 kb
Host smart-9a992e71-d81e-422f-80b1-9c1c118a52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212466008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.212466008
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.3471416495
Short name T248
Test name
Test status
Simulation time 27437297 ps
CPU time 1.24 seconds
Started Oct 04 01:46:50 PM PDT 23
Finished Oct 04 01:46:52 PM PDT 23
Peak memory 230428 kb
Host smart-35825f91-09f6-4cc4-9f4e-4e88eae89831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471416495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3471416495
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.4046854337
Short name T660
Test name
Test status
Simulation time 18484634 ps
CPU time 1.13 seconds
Started Oct 04 01:50:39 PM PDT 23
Finished Oct 04 01:50:41 PM PDT 23
Peak memory 221652 kb
Host smart-eda159fc-cb96-43b1-991a-3a01373eae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046854337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4046854337
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.2957984312
Short name T174
Test name
Test status
Simulation time 24685851 ps
CPU time 0.99 seconds
Started Oct 04 01:46:51 PM PDT 23
Finished Oct 04 01:46:53 PM PDT 23
Peak memory 222260 kb
Host smart-d716cea9-6e84-44ef-9554-8c3573bf4ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957984312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2957984312
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.1278228152
Short name T310
Test name
Test status
Simulation time 22173647 ps
CPU time 1 seconds
Started Oct 04 01:50:53 PM PDT 23
Finished Oct 04 01:50:54 PM PDT 23
Peak memory 206208 kb
Host smart-b3b870d1-fc07-4b40-9c97-783826324bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278228152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1278228152
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1835218281
Short name T491
Test name
Test status
Simulation time 33374425 ps
CPU time 0.89 seconds
Started Oct 04 01:44:05 PM PDT 23
Finished Oct 04 01:44:07 PM PDT 23
Peak memory 204648 kb
Host smart-0bf99e3d-7c68-4776-b67f-68bfb635efe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835218281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1835218281
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.551526290
Short name T38
Test name
Test status
Simulation time 14429287 ps
CPU time 0.91 seconds
Started Oct 04 01:50:19 PM PDT 23
Finished Oct 04 01:50:21 PM PDT 23
Peak memory 214696 kb
Host smart-c54e097d-a05c-4881-949d-515b84bbdf32
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551526290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.551526290
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2857052565
Short name T27
Test name
Test status
Simulation time 55134317 ps
CPU time 1.1 seconds
Started Oct 04 01:43:37 PM PDT 23
Finished Oct 04 01:43:38 PM PDT 23
Peak memory 214548 kb
Host smart-6006c246-894f-40ba-8473-70f4c72ec168
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857052565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2857052565
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3651888242
Short name T153
Test name
Test status
Simulation time 19323107 ps
CPU time 1.07 seconds
Started Oct 04 01:49:43 PM PDT 23
Finished Oct 04 01:49:44 PM PDT 23
Peak memory 214608 kb
Host smart-485d92d9-827c-4f8c-9b91-20466b9e7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651888242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3651888242
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.1257642071
Short name T580
Test name
Test status
Simulation time 90658589 ps
CPU time 0.77 seconds
Started Oct 04 01:42:30 PM PDT 23
Finished Oct 04 01:42:31 PM PDT 23
Peak memory 214292 kb
Host smart-87572bbf-eb32-4c08-afc1-26c2dcf91ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257642071 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1257642071
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3488154557
Short name T304
Test name
Test status
Simulation time 31594435 ps
CPU time 0.81 seconds
Started Oct 04 01:54:01 PM PDT 23
Finished Oct 04 01:54:03 PM PDT 23
Peak memory 204876 kb
Host smart-23e11e09-1366-4270-a106-9284a1206633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488154557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3488154557
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1886884819
Short name T522
Test name
Test status
Simulation time 26205730 ps
CPU time 0.87 seconds
Started Oct 04 01:44:36 PM PDT 23
Finished Oct 04 01:44:38 PM PDT 23
Peak memory 204820 kb
Host smart-08886712-4f7a-48f6-88a9-0e0bd0d5e615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886884819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1886884819
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1670307085
Short name T595
Test name
Test status
Simulation time 88864035 ps
CPU time 2.24 seconds
Started Oct 04 01:49:38 PM PDT 23
Finished Oct 04 01:49:41 PM PDT 23
Peak memory 205696 kb
Host smart-5e78b830-c74a-442b-88cd-e743ce8d8e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670307085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1670307085
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.367353077
Short name T615
Test name
Test status
Simulation time 584254027126 ps
CPU time 2953.09 seconds
Started Oct 04 01:43:02 PM PDT 23
Finished Oct 04 02:32:16 PM PDT 23
Peak memory 224072 kb
Host smart-fe749515-408d-43b5-b916-de5a0d83d9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367353077 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.367353077
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2224822735
Short name T245
Test name
Test status
Simulation time 21961933 ps
CPU time 0.86 seconds
Started Oct 04 01:50:47 PM PDT 23
Finished Oct 04 01:50:49 PM PDT 23
Peak memory 214624 kb
Host smart-dc1f85f2-7881-4d19-9366-3562495dc66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224822735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2224822735
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.3676270234
Short name T298
Test name
Test status
Simulation time 31148778 ps
CPU time 1.16 seconds
Started Oct 04 01:46:45 PM PDT 23
Finished Oct 04 01:46:46 PM PDT 23
Peak memory 222100 kb
Host smart-b0c2aedf-16a6-41f1-8472-ae46df7f1220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676270234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3676270234
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.2427629814
Short name T166
Test name
Test status
Simulation time 19670949 ps
CPU time 1.08 seconds
Started Oct 04 01:49:55 PM PDT 23
Finished Oct 04 01:49:57 PM PDT 23
Peak memory 221432 kb
Host smart-7772edcc-504d-4cd0-843b-323fb1ecff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427629814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2427629814
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.1089853313
Short name T696
Test name
Test status
Simulation time 18053568 ps
CPU time 0.95 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 01:50:34 PM PDT 23
Peak memory 213600 kb
Host smart-98b025d9-8a98-4300-99c8-9291147be7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089853313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1089853313
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.2134753774
Short name T176
Test name
Test status
Simulation time 19042141 ps
CPU time 1.04 seconds
Started Oct 04 01:46:43 PM PDT 23
Finished Oct 04 01:46:44 PM PDT 23
Peak memory 215848 kb
Host smart-e1604b2d-03f4-457c-8f74-fd2a4c94ba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134753774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2134753774
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.279319994
Short name T151
Test name
Test status
Simulation time 31507000 ps
CPU time 1.11 seconds
Started Oct 04 01:48:44 PM PDT 23
Finished Oct 04 01:48:45 PM PDT 23
Peak memory 228864 kb
Host smart-f47d5448-2bca-4e9d-9386-cc9908bc413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279319994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.279319994
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.1923733627
Short name T530
Test name
Test status
Simulation time 31610002 ps
CPU time 0.96 seconds
Started Oct 04 01:48:29 PM PDT 23
Finished Oct 04 01:48:31 PM PDT 23
Peak memory 215724 kb
Host smart-21ead822-554f-4543-a115-7dd57051c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923733627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1923733627
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.2546785393
Short name T168
Test name
Test status
Simulation time 45361695 ps
CPU time 0.96 seconds
Started Oct 04 01:48:52 PM PDT 23
Finished Oct 04 01:48:53 PM PDT 23
Peak memory 221160 kb
Host smart-412ce544-8069-43bd-a0b1-2e3912a58482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546785393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2546785393
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.3117438762
Short name T476
Test name
Test status
Simulation time 28620126 ps
CPU time 1.19 seconds
Started Oct 04 01:46:40 PM PDT 23
Finished Oct 04 01:46:42 PM PDT 23
Peak memory 214656 kb
Host smart-8aba9d78-693f-4c47-828b-c2ddb3d0d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117438762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3117438762
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.4291691244
Short name T493
Test name
Test status
Simulation time 36391661 ps
CPU time 0.98 seconds
Started Oct 04 01:46:49 PM PDT 23
Finished Oct 04 01:46:50 PM PDT 23
Peak memory 215796 kb
Host smart-47b1b17c-558c-422e-bc2b-d40d6616bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291691244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4291691244
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.3204848701
Short name T529
Test name
Test status
Simulation time 33672653 ps
CPU time 0.95 seconds
Started Oct 04 01:50:53 PM PDT 23
Finished Oct 04 01:50:55 PM PDT 23
Peak memory 206184 kb
Host smart-2acef7bb-6a16-40f3-bb96-d3a903b0f23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204848701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3204848701
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1357057796
Short name T520
Test name
Test status
Simulation time 28840098 ps
CPU time 0.85 seconds
Started Oct 04 01:43:15 PM PDT 23
Finished Oct 04 01:43:16 PM PDT 23
Peak memory 205120 kb
Host smart-0266a031-b8dc-4680-acba-97318f31d4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357057796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1357057796
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.681596038
Short name T95
Test name
Test status
Simulation time 73071832 ps
CPU time 0.8 seconds
Started Oct 04 01:50:49 PM PDT 23
Finished Oct 04 01:50:50 PM PDT 23
Peak memory 214472 kb
Host smart-9d3f7a3b-a7ea-4503-9050-4e6a3ad5948b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681596038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.681596038
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3394061888
Short name T296
Test name
Test status
Simulation time 19252293 ps
CPU time 1.03 seconds
Started Oct 04 01:46:10 PM PDT 23
Finished Oct 04 01:46:11 PM PDT 23
Peak memory 214584 kb
Host smart-38fa57ad-434b-432b-87a5-0479ce611cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394061888 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3394061888
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.197770083
Short name T617
Test name
Test status
Simulation time 49412224 ps
CPU time 1.02 seconds
Started Oct 04 01:41:50 PM PDT 23
Finished Oct 04 01:41:51 PM PDT 23
Peak memory 216736 kb
Host smart-876ff366-113c-449a-a4cc-519fb24a8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197770083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.197770083
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.3312595525
Short name T108
Test name
Test status
Simulation time 23374813 ps
CPU time 0.87 seconds
Started Oct 04 01:50:32 PM PDT 23
Finished Oct 04 01:50:34 PM PDT 23
Peak memory 214852 kb
Host smart-5d625470-a391-4c33-ae7b-512c80dfa4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312595525 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3312595525
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.657083283
Short name T130
Test name
Test status
Simulation time 15978349 ps
CPU time 0.88 seconds
Started Oct 04 01:52:02 PM PDT 23
Finished Oct 04 01:52:04 PM PDT 23
Peak memory 204612 kb
Host smart-3ebd658a-0eb5-49d7-b88c-e079f1550dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657083283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.657083283
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1707025166
Short name T342
Test name
Test status
Simulation time 54438691 ps
CPU time 0.88 seconds
Started Oct 04 01:54:00 PM PDT 23
Finished Oct 04 01:54:02 PM PDT 23
Peak memory 204856 kb
Host smart-e9f8a41c-411d-4398-a0eb-9b063adce2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707025166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1707025166
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.180290931
Short name T534
Test name
Test status
Simulation time 123334181 ps
CPU time 2.89 seconds
Started Oct 04 01:47:31 PM PDT 23
Finished Oct 04 01:47:34 PM PDT 23
Peak memory 205832 kb
Host smart-5dd3a07d-33f7-451a-8bb4-c5788bbdaff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180290931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.180290931
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3032427882
Short name T483
Test name
Test status
Simulation time 63574166201 ps
CPU time 1416.59 seconds
Started Oct 04 01:47:47 PM PDT 23
Finished Oct 04 02:11:24 PM PDT 23
Peak memory 215668 kb
Host smart-3de5f413-a39e-43a7-a406-78cfcde7cfff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032427882 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3032427882
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2307489079
Short name T175
Test name
Test status
Simulation time 24611176 ps
CPU time 0.91 seconds
Started Oct 04 01:50:41 PM PDT 23
Finished Oct 04 01:50:42 PM PDT 23
Peak memory 215848 kb
Host smart-767364d7-0568-479b-9143-b8b85fc976ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307489079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2307489079
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.806355112
Short name T254
Test name
Test status
Simulation time 29581722 ps
CPU time 1.25 seconds
Started Oct 04 01:49:49 PM PDT 23
Finished Oct 04 01:49:52 PM PDT 23
Peak memory 222080 kb
Host smart-2fa231c1-b8f6-4833-8218-1f63f15a1669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806355112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.806355112
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.3626023301
Short name T264
Test name
Test status
Simulation time 29250963 ps
CPU time 1.22 seconds
Started Oct 04 01:49:53 PM PDT 23
Finished Oct 04 01:49:55 PM PDT 23
Peak memory 222092 kb
Host smart-7324682e-9472-4d50-bb5f-18950f8bf03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626023301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3626023301
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.142389593
Short name T519
Test name
Test status
Simulation time 22101324 ps
CPU time 1.01 seconds
Started Oct 04 01:46:44 PM PDT 23
Finished Oct 04 01:46:46 PM PDT 23
Peak memory 215808 kb
Host smart-3e0c34a4-35e3-4ce3-b337-0753ada15686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142389593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.142389593
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.2121772199
Short name T162
Test name
Test status
Simulation time 31336395 ps
CPU time 0.9 seconds
Started Oct 04 01:50:40 PM PDT 23
Finished Oct 04 01:50:42 PM PDT 23
Peak memory 221540 kb
Host smart-76398ad6-cc71-42bf-8e34-ea6dc9224440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121772199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2121772199
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.1320439973
Short name T147
Test name
Test status
Simulation time 19776094 ps
CPU time 1.06 seconds
Started Oct 04 01:51:31 PM PDT 23
Finished Oct 04 01:51:33 PM PDT 23
Peak memory 214592 kb
Host smart-532f9266-db2d-4ba1-834d-791370d60586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320439973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1320439973
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.3278989830
Short name T649
Test name
Test status
Simulation time 23855481 ps
CPU time 1.07 seconds
Started Oct 04 01:48:05 PM PDT 23
Finished Oct 04 01:48:07 PM PDT 23
Peak memory 222284 kb
Host smart-c5c4084c-4787-4fa6-b2b9-10dae89ada6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278989830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3278989830
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.388258289
Short name T706
Test name
Test status
Simulation time 24197470 ps
CPU time 1.08 seconds
Started Oct 04 01:55:07 PM PDT 23
Finished Oct 04 01:55:08 PM PDT 23
Peak memory 222096 kb
Host smart-3bca9f3b-0bcb-4251-8a84-137f925720ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388258289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.388258289
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.630485892
Short name T253
Test name
Test status
Simulation time 25498198 ps
CPU time 1.18 seconds
Started Oct 04 01:50:31 PM PDT 23
Finished Oct 04 01:50:33 PM PDT 23
Peak memory 215856 kb
Host smart-255c38d5-3f75-4be6-a226-7b4fa7df2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630485892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.630485892
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.2467865842
Short name T674
Test name
Test status
Simulation time 21539257 ps
CPU time 0.96 seconds
Started Oct 04 01:45:57 PM PDT 23
Finished Oct 04 01:45:59 PM PDT 23
Peak memory 206128 kb
Host smart-aa4658b7-5d38-46f3-a778-0f9a86aff7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467865842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2467865842
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3987141414
Short name T458
Test name
Test status
Simulation time 21722869 ps
CPU time 0.85 seconds
Started Oct 04 01:54:08 PM PDT 23
Finished Oct 04 01:54:10 PM PDT 23
Peak memory 204676 kb
Host smart-32f2c84d-a39a-47e4-95ac-3f7ad6ac8728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987141414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3987141414
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1342819890
Short name T69
Test name
Test status
Simulation time 26183309 ps
CPU time 0.75 seconds
Started Oct 04 01:51:27 PM PDT 23
Finished Oct 04 01:51:28 PM PDT 23
Peak memory 214408 kb
Host smart-875987bd-0064-4748-8523-07d715829bbb
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342819890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1342819890
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3828946801
Short name T263
Test name
Test status
Simulation time 51381758 ps
CPU time 0.95 seconds
Started Oct 04 01:47:48 PM PDT 23
Finished Oct 04 01:47:50 PM PDT 23
Peak memory 206432 kb
Host smart-d02c69cd-54f9-48ad-8967-7bbe9a287f3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828946801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3828946801
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.740902501
Short name T459
Test name
Test status
Simulation time 28045539 ps
CPU time 0.92 seconds
Started Oct 04 01:46:14 PM PDT 23
Finished Oct 04 01:46:16 PM PDT 23
Peak memory 214504 kb
Host smart-9fb38a5d-5ef0-4a18-bb65-f10ad341431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740902501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.740902501
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4060849603
Short name T64
Test name
Test status
Simulation time 47605479 ps
CPU time 0.94 seconds
Started Oct 04 01:49:50 PM PDT 23
Finished Oct 04 01:49:53 PM PDT 23
Peak memory 205024 kb
Host smart-09a6a9a0-8e30-48be-93b3-986d3e115e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060849603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4060849603
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3343188938
Short name T4
Test name
Test status
Simulation time 18824759 ps
CPU time 1.02 seconds
Started Oct 04 01:52:19 PM PDT 23
Finished Oct 04 01:52:21 PM PDT 23
Peak memory 214752 kb
Host smart-512adc46-ae1f-482e-ade3-cc553741817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343188938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3343188938
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1480197142
Short name T2
Test name
Test status
Simulation time 24219968 ps
CPU time 0.85 seconds
Started Oct 04 01:52:48 PM PDT 23
Finished Oct 04 01:52:49 PM PDT 23
Peak memory 204868 kb
Host smart-d2493052-2c02-4110-8998-f4369e55e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480197142 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1480197142
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.886233525
Short name T33
Test name
Test status
Simulation time 140276307 ps
CPU time 0.84 seconds
Started Oct 04 01:52:58 PM PDT 23
Finished Oct 04 01:52:59 PM PDT 23
Peak memory 204712 kb
Host smart-2008b171-f39a-4cda-a8a6-953685475e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886233525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.886233525
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1765160145
Short name T334
Test name
Test status
Simulation time 68408783 ps
CPU time 1.55 seconds
Started Oct 04 01:41:53 PM PDT 23
Finished Oct 04 01:41:55 PM PDT 23
Peak memory 205532 kb
Host smart-9435d992-9b89-4f2d-a819-f3d281314c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765160145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1765160145
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3228979812
Short name T461
Test name
Test status
Simulation time 440745216570 ps
CPU time 2782.83 seconds
Started Oct 04 01:52:40 PM PDT 23
Finished Oct 04 02:39:03 PM PDT 23
Peak memory 223256 kb
Host smart-82afa9d5-aec4-40f7-bfa8-3cbfa22c17e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228979812 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3228979812
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3571863174
Short name T164
Test name
Test status
Simulation time 19514831 ps
CPU time 1.02 seconds
Started Oct 04 01:49:32 PM PDT 23
Finished Oct 04 01:49:33 PM PDT 23
Peak memory 215700 kb
Host smart-d383d2aa-ff98-4fe6-b418-940fa5719ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571863174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3571863174
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.1052952077
Short name T702
Test name
Test status
Simulation time 32907055 ps
CPU time 1.05 seconds
Started Oct 04 01:53:09 PM PDT 23
Finished Oct 04 01:53:11 PM PDT 23
Peak memory 221492 kb
Host smart-26924943-f667-482b-ae0e-ed3502fd3583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052952077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1052952077
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.3337140353
Short name T49
Test name
Test status
Simulation time 58970117 ps
CPU time 1.16 seconds
Started Oct 04 01:52:11 PM PDT 23
Finished Oct 04 01:52:13 PM PDT 23
Peak memory 222180 kb
Host smart-5e433651-746b-44a3-8bb8-ae6e0ab37801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337140353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3337140353
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.4126452210
Short name T591
Test name
Test status
Simulation time 30058947 ps
CPU time 0.87 seconds
Started Oct 04 01:51:38 PM PDT 23
Finished Oct 04 01:51:40 PM PDT 23
Peak memory 215704 kb
Host smart-7d59ad61-93a6-42d9-bb28-fd35aab0cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126452210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4126452210
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.3999713862
Short name T177
Test name
Test status
Simulation time 95233090 ps
CPU time 0.89 seconds
Started Oct 04 01:49:51 PM PDT 23
Finished Oct 04 01:49:53 PM PDT 23
Peak memory 221176 kb
Host smart-68ffd7f2-c1b5-4d21-b03b-9023f8924dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999713862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3999713862
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.1545799124
Short name T131
Test name
Test status
Simulation time 139745480 ps
CPU time 0.99 seconds
Started Oct 04 01:54:57 PM PDT 23
Finished Oct 04 01:54:59 PM PDT 23
Peak memory 214544 kb
Host smart-24d2e871-4ed5-4e39-8c66-c7a41183ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545799124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1545799124
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.1502949799
Short name T161
Test name
Test status
Simulation time 49805666 ps
CPU time 1.14 seconds
Started Oct 04 01:47:55 PM PDT 23
Finished Oct 04 01:47:57 PM PDT 23
Peak memory 228716 kb
Host smart-1b355139-e442-4816-afd3-91253ba2dd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502949799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1502949799
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.33081780
Short name T118
Test name
Test status
Simulation time 19605679 ps
CPU time 1.07 seconds
Started Oct 04 01:46:45 PM PDT 23
Finished Oct 04 01:46:47 PM PDT 23
Peak memory 214604 kb
Host smart-249bf60c-8a5a-4056-a525-42aa0ba49fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33081780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.33081780
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.3127392471
Short name T712
Test name
Test status
Simulation time 18808402 ps
CPU time 1.14 seconds
Started Oct 04 01:46:43 PM PDT 23
Finished Oct 04 01:46:45 PM PDT 23
Peak memory 215824 kb
Host smart-c41fc240-975d-4c80-84fe-42e5f3f448ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127392471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3127392471
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.1433805499
Short name T679
Test name
Test status
Simulation time 21984418 ps
CPU time 1.02 seconds
Started Oct 04 01:51:23 PM PDT 23
Finished Oct 04 01:51:25 PM PDT 23
Peak memory 221776 kb
Host smart-c7a35dd1-d80f-4c82-9089-e855fbf92478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433805499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1433805499
Directory /workspace/99.edn_err/latest
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