Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.06 99.02 92.39 96.79 95.39 98.62 99.77 97.45


Total test records in report: 729
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T550 /workspace/coverage/default/32.edn_err.4107454407 Oct 08 01:55:56 PM PDT 23 Oct 08 01:55:57 PM PDT 23 19397501 ps
T551 /workspace/coverage/default/42.edn_intr.3067531850 Oct 08 01:47:05 PM PDT 23 Oct 08 01:47:06 PM PDT 23 37121557 ps
T238 /workspace/coverage/default/66.edn_err.450635627 Oct 08 02:29:27 PM PDT 23 Oct 08 02:29:28 PM PDT 23 19900462 ps
T552 /workspace/coverage/default/64.edn_err.1429447850 Oct 08 03:10:02 PM PDT 23 Oct 08 03:10:03 PM PDT 23 89845152 ps
T553 /workspace/coverage/default/6.edn_genbits.369548260 Oct 08 01:56:10 PM PDT 23 Oct 08 01:56:11 PM PDT 23 16482969 ps
T554 /workspace/coverage/default/34.edn_smoke.3471165715 Oct 08 01:44:21 PM PDT 23 Oct 08 01:44:22 PM PDT 23 41740683 ps
T203 /workspace/coverage/default/94.edn_err.3142772415 Oct 08 02:57:16 PM PDT 23 Oct 08 02:57:17 PM PDT 23 20445071 ps
T555 /workspace/coverage/default/25.edn_alert_test.3065016030 Oct 08 01:48:55 PM PDT 23 Oct 08 01:48:56 PM PDT 23 14886538 ps
T556 /workspace/coverage/default/12.edn_err.1018934216 Oct 08 01:43:51 PM PDT 23 Oct 08 01:43:53 PM PDT 23 42844694 ps
T557 /workspace/coverage/default/32.edn_alert.333412063 Oct 08 01:48:09 PM PDT 23 Oct 08 01:48:10 PM PDT 23 54852451 ps
T558 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1470713537 Oct 08 01:46:10 PM PDT 23 Oct 08 01:54:43 PM PDT 23 40352213585 ps
T559 /workspace/coverage/default/33.edn_smoke.1983747279 Oct 08 01:53:03 PM PDT 23 Oct 08 01:53:04 PM PDT 23 22126427 ps
T560 /workspace/coverage/default/49.edn_intr.3895147094 Oct 08 01:46:30 PM PDT 23 Oct 08 01:46:31 PM PDT 23 28357444 ps
T561 /workspace/coverage/default/1.edn_alert_test.3378620843 Oct 08 01:44:05 PM PDT 23 Oct 08 01:44:06 PM PDT 23 15177117 ps
T562 /workspace/coverage/default/38.edn_alert.3833576861 Oct 08 01:44:31 PM PDT 23 Oct 08 01:44:32 PM PDT 23 44178634 ps
T563 /workspace/coverage/default/12.edn_stress_all.673794489 Oct 08 01:50:45 PM PDT 23 Oct 08 01:50:46 PM PDT 23 52948483 ps
T134 /workspace/coverage/default/34.edn_disable.1884505794 Oct 08 01:52:37 PM PDT 23 Oct 08 01:52:38 PM PDT 23 21787626 ps
T564 /workspace/coverage/default/5.edn_genbits.2511393466 Oct 08 01:42:30 PM PDT 23 Oct 08 01:42:31 PM PDT 23 61668543 ps
T565 /workspace/coverage/default/96.edn_err.213451778 Oct 08 01:49:14 PM PDT 23 Oct 08 01:49:15 PM PDT 23 29974754 ps
T191 /workspace/coverage/default/45.edn_err.3837907567 Oct 08 02:31:48 PM PDT 23 Oct 08 02:31:49 PM PDT 23 27343578 ps
T566 /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3801765757 Oct 08 01:52:16 PM PDT 23 Oct 08 01:59:24 PM PDT 23 172021754578 ps
T567 /workspace/coverage/default/16.edn_intr.1480484787 Oct 08 01:44:02 PM PDT 23 Oct 08 01:44:03 PM PDT 23 37438642 ps
T174 /workspace/coverage/default/49.edn_disable_auto_req_mode.3408736703 Oct 08 01:55:12 PM PDT 23 Oct 08 01:55:13 PM PDT 23 17288019 ps
T568 /workspace/coverage/default/7.edn_disable.1064840264 Oct 08 01:45:27 PM PDT 23 Oct 08 01:45:28 PM PDT 23 25386451 ps
T260 /workspace/coverage/default/44.edn_genbits.4235993673 Oct 08 01:52:03 PM PDT 23 Oct 08 01:52:05 PM PDT 23 24748335 ps
T569 /workspace/coverage/default/8.edn_alert_test.2782683174 Oct 08 01:42:55 PM PDT 23 Oct 08 01:42:57 PM PDT 23 31436297 ps
T570 /workspace/coverage/default/11.edn_stress_all_with_rand_reset.369822198 Oct 08 01:41:41 PM PDT 23 Oct 08 02:13:19 PM PDT 23 138977001471 ps
T175 /workspace/coverage/default/35.edn_disable_auto_req_mode.1451357065 Oct 08 01:52:44 PM PDT 23 Oct 08 01:52:45 PM PDT 23 73792732 ps
T240 /workspace/coverage/default/11.edn_disable_auto_req_mode.2857114409 Oct 08 01:55:38 PM PDT 23 Oct 08 01:55:40 PM PDT 23 52216370 ps
T571 /workspace/coverage/default/35.edn_stress_all.737878249 Oct 08 01:49:03 PM PDT 23 Oct 08 01:49:05 PM PDT 23 60813545 ps
T572 /workspace/coverage/default/38.edn_alert_test.82057897 Oct 08 01:44:19 PM PDT 23 Oct 08 01:44:20 PM PDT 23 21885867 ps
T131 /workspace/coverage/default/6.edn_disable.3516717395 Oct 08 01:43:35 PM PDT 23 Oct 08 01:43:36 PM PDT 23 32488143 ps
T284 /workspace/coverage/default/0.edn_genbits.1301271273 Oct 08 12:44:35 PM PDT 23 Oct 08 12:44:36 PM PDT 23 67633157 ps
T573 /workspace/coverage/default/24.edn_err.737784771 Oct 08 01:43:39 PM PDT 23 Oct 08 01:43:40 PM PDT 23 23663813 ps
T574 /workspace/coverage/default/9.edn_alert_test.4094873587 Oct 08 01:49:41 PM PDT 23 Oct 08 01:49:42 PM PDT 23 14105773 ps
T575 /workspace/coverage/default/51.edn_err.3284823340 Oct 08 01:52:44 PM PDT 23 Oct 08 01:52:45 PM PDT 23 24745106 ps
T576 /workspace/coverage/default/12.edn_intr.2928564725 Oct 08 01:44:35 PM PDT 23 Oct 08 01:44:36 PM PDT 23 24424325 ps
T245 /workspace/coverage/default/65.edn_err.3419347378 Oct 08 02:29:55 PM PDT 23 Oct 08 02:29:57 PM PDT 23 29706476 ps
T179 /workspace/coverage/default/36.edn_err.3581099272 Oct 08 01:43:25 PM PDT 23 Oct 08 01:43:26 PM PDT 23 35597569 ps
T269 /workspace/coverage/default/36.edn_stress_all.604253555 Oct 08 02:19:16 PM PDT 23 Oct 08 02:19:20 PM PDT 23 2341257278 ps
T577 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4179020796 Oct 08 01:55:38 PM PDT 23 Oct 08 02:06:15 PM PDT 23 34877533857 ps
T578 /workspace/coverage/default/41.edn_stress_all.4023921511 Oct 08 02:44:12 PM PDT 23 Oct 08 02:44:15 PM PDT 23 115224371 ps
T579 /workspace/coverage/default/36.edn_intr.2979453184 Oct 08 01:43:18 PM PDT 23 Oct 08 01:43:19 PM PDT 23 24219330 ps
T580 /workspace/coverage/default/5.edn_disable_auto_req_mode.3587488150 Oct 08 01:47:11 PM PDT 23 Oct 08 01:47:12 PM PDT 23 26986548 ps
T581 /workspace/coverage/default/14.edn_smoke.3087811700 Oct 08 01:48:53 PM PDT 23 Oct 08 01:48:54 PM PDT 23 48603010 ps
T582 /workspace/coverage/default/7.edn_intr.3376184964 Oct 08 01:50:30 PM PDT 23 Oct 08 01:50:31 PM PDT 23 31330212 ps
T583 /workspace/coverage/default/34.edn_alert_test.2815601176 Oct 08 01:44:23 PM PDT 23 Oct 08 01:44:24 PM PDT 23 44244773 ps
T584 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.492210442 Oct 08 01:55:42 PM PDT 23 Oct 08 02:08:30 PM PDT 23 36609539452 ps
T585 /workspace/coverage/default/14.edn_disable.516684031 Oct 08 01:42:05 PM PDT 23 Oct 08 01:42:06 PM PDT 23 15914603 ps
T586 /workspace/coverage/default/18.edn_alert.3656827273 Oct 08 01:45:06 PM PDT 23 Oct 08 01:45:07 PM PDT 23 149654271 ps
T587 /workspace/coverage/default/32.edn_alert_test.577429155 Oct 08 01:49:09 PM PDT 23 Oct 08 01:49:10 PM PDT 23 13268347 ps
T588 /workspace/coverage/default/41.edn_err.3511811392 Oct 08 03:24:04 PM PDT 23 Oct 08 03:24:06 PM PDT 23 21686258 ps
T589 /workspace/coverage/default/11.edn_intr.1208691608 Oct 08 01:43:30 PM PDT 23 Oct 08 01:43:31 PM PDT 23 22645780 ps
T590 /workspace/coverage/default/9.edn_disable.2554665151 Oct 08 01:46:32 PM PDT 23 Oct 08 01:46:33 PM PDT 23 27661794 ps
T591 /workspace/coverage/default/32.edn_stress_all.1691782437 Oct 08 01:46:44 PM PDT 23 Oct 08 01:46:45 PM PDT 23 144805998 ps
T592 /workspace/coverage/default/26.edn_alert.3931344363 Oct 08 01:49:42 PM PDT 23 Oct 08 01:49:44 PM PDT 23 20541693 ps
T593 /workspace/coverage/default/41.edn_disable_auto_req_mode.1379863117 Oct 08 02:41:37 PM PDT 23 Oct 08 02:41:38 PM PDT 23 80122965 ps
T594 /workspace/coverage/default/17.edn_disable.1118501508 Oct 08 01:53:51 PM PDT 23 Oct 08 01:53:52 PM PDT 23 12754670 ps
T176 /workspace/coverage/default/50.edn_err.3130002768 Oct 08 01:47:09 PM PDT 23 Oct 08 01:47:10 PM PDT 23 40800086 ps
T595 /workspace/coverage/default/4.edn_alert_test.3083689223 Oct 08 01:45:35 PM PDT 23 Oct 08 01:45:37 PM PDT 23 16936990 ps
T596 /workspace/coverage/default/44.edn_smoke.1077915348 Oct 08 01:53:48 PM PDT 23 Oct 08 01:53:49 PM PDT 23 15324785 ps
T597 /workspace/coverage/default/15.edn_smoke.1333527128 Oct 08 01:43:55 PM PDT 23 Oct 08 01:43:56 PM PDT 23 23775589 ps
T598 /workspace/coverage/default/38.edn_stress_all_with_rand_reset.407023012 Oct 08 01:48:10 PM PDT 23 Oct 08 02:22:49 PM PDT 23 383189187199 ps
T599 /workspace/coverage/default/3.edn_intr.2621158270 Oct 08 01:42:50 PM PDT 23 Oct 08 01:42:53 PM PDT 23 18609691 ps
T600 /workspace/coverage/default/27.edn_alert_test.2223719508 Oct 08 01:54:28 PM PDT 23 Oct 08 01:54:29 PM PDT 23 59492070 ps
T601 /workspace/coverage/default/26.edn_genbits.1360869305 Oct 08 01:45:19 PM PDT 23 Oct 08 01:45:20 PM PDT 23 45761140 ps
T602 /workspace/coverage/default/10.edn_stress_all.128109290 Oct 08 01:49:31 PM PDT 23 Oct 08 01:49:35 PM PDT 23 593460932 ps
T603 /workspace/coverage/default/9.edn_disable_auto_req_mode.1964569400 Oct 08 01:43:09 PM PDT 23 Oct 08 01:43:10 PM PDT 23 31046572 ps
T604 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.274471196 Oct 08 01:41:32 PM PDT 23 Oct 08 01:54:44 PM PDT 23 132154686599 ps
T605 /workspace/coverage/default/43.edn_alert.1892560401 Oct 08 03:12:15 PM PDT 23 Oct 08 03:12:16 PM PDT 23 45599322 ps
T606 /workspace/coverage/default/12.edn_alert.3340041307 Oct 08 01:56:08 PM PDT 23 Oct 08 01:56:09 PM PDT 23 19639768 ps
T607 /workspace/coverage/default/1.edn_intr.2795751882 Oct 08 01:47:58 PM PDT 23 Oct 08 01:48:00 PM PDT 23 20346420 ps
T206 /workspace/coverage/default/5.edn_err.2570282460 Oct 08 01:45:45 PM PDT 23 Oct 08 01:45:46 PM PDT 23 21829888 ps
T196 /workspace/coverage/default/3.edn_disable.402621281 Oct 08 01:43:34 PM PDT 23 Oct 08 01:43:35 PM PDT 23 13338933 ps
T608 /workspace/coverage/default/30.edn_err.2100894394 Oct 08 01:43:02 PM PDT 23 Oct 08 01:43:03 PM PDT 23 52533352 ps
T609 /workspace/coverage/default/37.edn_disable_auto_req_mode.3599744438 Oct 08 03:14:36 PM PDT 23 Oct 08 03:14:38 PM PDT 23 36946225 ps
T282 /workspace/coverage/default/28.edn_genbits.1196971016 Oct 08 01:49:18 PM PDT 23 Oct 08 01:49:20 PM PDT 23 17373306 ps
T610 /workspace/coverage/default/46.edn_genbits.1391751267 Oct 08 01:43:54 PM PDT 23 Oct 08 01:43:55 PM PDT 23 30940933 ps
T611 /workspace/coverage/default/29.edn_alert_test.655309657 Oct 08 01:45:17 PM PDT 23 Oct 08 01:45:18 PM PDT 23 68135207 ps
T612 /workspace/coverage/default/34.edn_stress_all.4041424867 Oct 08 01:52:28 PM PDT 23 Oct 08 01:52:31 PM PDT 23 322080615 ps
T613 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3008186071 Oct 08 01:46:29 PM PDT 23 Oct 08 02:01:22 PM PDT 23 82053284730 ps
T614 /workspace/coverage/default/19.edn_stress_all.1327381061 Oct 08 01:42:33 PM PDT 23 Oct 08 01:42:36 PM PDT 23 99586529 ps
T615 /workspace/coverage/default/33.edn_alert.2785365503 Oct 08 01:55:54 PM PDT 23 Oct 08 01:55:55 PM PDT 23 17037930 ps
T616 /workspace/coverage/default/89.edn_err.3132424723 Oct 08 01:44:42 PM PDT 23 Oct 08 01:44:43 PM PDT 23 45954437 ps
T617 /workspace/coverage/default/26.edn_disable_auto_req_mode.3065615592 Oct 08 01:42:43 PM PDT 23 Oct 08 01:42:45 PM PDT 23 86757399 ps
T24 /workspace/coverage/default/4.edn_sec_cm.2116194613 Oct 08 01:50:09 PM PDT 23 Oct 08 01:50:13 PM PDT 23 253426218 ps
T618 /workspace/coverage/default/7.edn_smoke.952791152 Oct 08 01:43:36 PM PDT 23 Oct 08 01:43:37 PM PDT 23 68570228 ps
T267 /workspace/coverage/default/46.edn_stress_all.515724843 Oct 08 01:50:34 PM PDT 23 Oct 08 01:50:37 PM PDT 23 118098579 ps
T619 /workspace/coverage/default/41.edn_disable.3208830839 Oct 08 02:07:39 PM PDT 23 Oct 08 02:07:40 PM PDT 23 10764211 ps
T293 /workspace/coverage/default/37.edn_alert.1821946800 Oct 08 01:45:22 PM PDT 23 Oct 08 01:45:23 PM PDT 23 20819084 ps
T620 /workspace/coverage/default/2.edn_alert.2006812463 Oct 08 01:48:39 PM PDT 23 Oct 08 01:48:41 PM PDT 23 20777282 ps
T171 /workspace/coverage/default/37.edn_err.1011477040 Oct 08 01:50:12 PM PDT 23 Oct 08 01:50:13 PM PDT 23 57121383 ps
T621 /workspace/coverage/default/16.edn_alert.3495666636 Oct 08 01:45:06 PM PDT 23 Oct 08 01:45:12 PM PDT 23 129819761 ps
T622 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3098184738 Oct 08 01:43:32 PM PDT 23 Oct 08 01:46:08 PM PDT 23 6996117013 ps
T52 /workspace/coverage/default/2.edn_sec_cm.232857415 Oct 08 01:41:26 PM PDT 23 Oct 08 01:41:29 PM PDT 23 182391501 ps
T623 /workspace/coverage/default/58.edn_err.2175056967 Oct 08 01:44:37 PM PDT 23 Oct 08 01:44:39 PM PDT 23 29313263 ps
T624 /workspace/coverage/default/15.edn_genbits.789507169 Oct 08 01:46:39 PM PDT 23 Oct 08 01:46:40 PM PDT 23 56344448 ps
T625 /workspace/coverage/default/47.edn_disable_auto_req_mode.3367454019 Oct 08 02:56:29 PM PDT 23 Oct 08 02:56:30 PM PDT 23 23452208 ps
T626 /workspace/coverage/default/47.edn_smoke.1250765757 Oct 08 01:47:56 PM PDT 23 Oct 08 01:47:57 PM PDT 23 40071876 ps
T181 /workspace/coverage/default/43.edn_disable_auto_req_mode.747461680 Oct 08 01:53:48 PM PDT 23 Oct 08 01:53:49 PM PDT 23 80457336 ps
T266 /workspace/coverage/default/7.edn_genbits.2294520200 Oct 08 01:43:36 PM PDT 23 Oct 08 01:43:37 PM PDT 23 109157474 ps
T107 /workspace/coverage/default/0.edn_err.975767624 Oct 08 12:41:05 PM PDT 23 Oct 08 12:41:07 PM PDT 23 66204467 ps
T627 /workspace/coverage/default/27.edn_stress_all.969534306 Oct 08 01:53:00 PM PDT 23 Oct 08 01:53:02 PM PDT 23 149082035 ps
T628 /workspace/coverage/default/49.edn_alert_test.752537097 Oct 08 01:55:12 PM PDT 23 Oct 08 01:55:13 PM PDT 23 84141908 ps
T100 /workspace/coverage/default/49.edn_alert.2575128786 Oct 08 01:54:54 PM PDT 23 Oct 08 01:54:56 PM PDT 23 56613343 ps
T629 /workspace/coverage/default/44.edn_stress_all.3233414593 Oct 08 01:53:00 PM PDT 23 Oct 08 01:53:03 PM PDT 23 123635492 ps
T630 /workspace/coverage/default/55.edn_err.4054469079 Oct 08 01:45:52 PM PDT 23 Oct 08 01:45:53 PM PDT 23 31780168 ps
T631 /workspace/coverage/default/36.edn_disable_auto_req_mode.2343466928 Oct 08 02:07:55 PM PDT 23 Oct 08 02:07:56 PM PDT 23 44581070 ps
T632 /workspace/coverage/default/45.edn_alert_test.2942187184 Oct 08 02:35:48 PM PDT 23 Oct 08 02:35:49 PM PDT 23 16186451 ps
T633 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.861641089 Oct 08 01:48:27 PM PDT 23 Oct 08 01:57:54 PM PDT 23 99190373499 ps
T634 /workspace/coverage/default/85.edn_err.3052968747 Oct 08 01:53:43 PM PDT 23 Oct 08 01:53:44 PM PDT 23 45373947 ps
T635 /workspace/coverage/default/41.edn_alert_test.1172068524 Oct 08 01:46:33 PM PDT 23 Oct 08 01:46:34 PM PDT 23 20236335 ps
T636 /workspace/coverage/default/3.edn_smoke.491185476 Oct 08 01:49:10 PM PDT 23 Oct 08 01:49:11 PM PDT 23 17259507 ps
T637 /workspace/coverage/default/27.edn_alert.2476205021 Oct 08 01:54:28 PM PDT 23 Oct 08 01:54:30 PM PDT 23 32153773 ps
T638 /workspace/coverage/default/45.edn_stress_all.2837428660 Oct 08 01:48:01 PM PDT 23 Oct 08 01:48:02 PM PDT 23 28340830 ps
T101 /workspace/coverage/default/29.edn_genbits.391822025 Oct 08 01:42:53 PM PDT 23 Oct 08 01:42:54 PM PDT 23 24705215 ps
T639 /workspace/coverage/default/3.edn_disable_auto_req_mode.1182115925 Oct 08 01:41:07 PM PDT 23 Oct 08 01:41:08 PM PDT 23 29271637 ps
T640 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3831892321 Oct 08 01:50:28 PM PDT 23 Oct 08 02:19:11 PM PDT 23 81171909121 ps
T641 /workspace/coverage/default/40.edn_alert_test.1206682252 Oct 08 01:56:08 PM PDT 23 Oct 08 01:56:09 PM PDT 23 17561796 ps
T642 /workspace/coverage/default/41.edn_intr.4100527769 Oct 08 03:29:27 PM PDT 23 Oct 08 03:29:28 PM PDT 23 20104873 ps
T270 /workspace/coverage/default/31.edn_genbits.4196486253 Oct 08 01:45:56 PM PDT 23 Oct 08 01:45:58 PM PDT 23 319700600 ps
T195 /workspace/coverage/default/7.edn_err.3633494267 Oct 08 01:42:46 PM PDT 23 Oct 08 01:42:47 PM PDT 23 18131892 ps
T643 /workspace/coverage/default/48.edn_err.2563588223 Oct 08 01:46:12 PM PDT 23 Oct 08 01:46:13 PM PDT 23 29667273 ps
T644 /workspace/coverage/default/36.edn_disable.3270585040 Oct 08 02:46:11 PM PDT 23 Oct 08 02:46:12 PM PDT 23 18556747 ps
T111 /workspace/coverage/default/40.edn_intr.1344117055 Oct 08 01:51:48 PM PDT 23 Oct 08 01:51:50 PM PDT 23 24356750 ps
T645 /workspace/coverage/default/21.edn_alert_test.2064606117 Oct 08 01:43:34 PM PDT 23 Oct 08 01:43:35 PM PDT 23 31064650 ps
T261 /workspace/coverage/default/41.edn_genbits.539495132 Oct 08 02:57:31 PM PDT 23 Oct 08 02:57:32 PM PDT 23 16486626 ps
T646 /workspace/coverage/default/16.edn_disable_auto_req_mode.2929526861 Oct 08 01:46:31 PM PDT 23 Oct 08 01:46:32 PM PDT 23 83359610 ps
T647 /workspace/coverage/default/22.edn_err.3028807371 Oct 08 01:43:52 PM PDT 23 Oct 08 01:43:53 PM PDT 23 94860860 ps
T183 /workspace/coverage/default/79.edn_err.4204601705 Oct 08 01:44:27 PM PDT 23 Oct 08 01:44:29 PM PDT 23 20252134 ps
T102 /workspace/coverage/default/32.edn_disable.729827780 Oct 08 01:44:25 PM PDT 23 Oct 08 01:44:26 PM PDT 23 37034221 ps
T53 /workspace/coverage/default/1.edn_sec_cm.3635250490 Oct 08 01:41:01 PM PDT 23 Oct 08 01:41:08 PM PDT 23 1428242983 ps
T648 /workspace/coverage/default/6.edn_intr.2452415900 Oct 08 01:42:55 PM PDT 23 Oct 08 01:42:57 PM PDT 23 23105237 ps
T649 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2159996725 Oct 08 01:50:00 PM PDT 23 Oct 08 02:16:31 PM PDT 23 69536399989 ps
T650 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2656851922 Oct 08 01:42:45 PM PDT 23 Oct 08 02:02:16 PM PDT 23 108801603151 ps
T651 /workspace/coverage/default/8.edn_stress_all.806846437 Oct 08 01:42:30 PM PDT 23 Oct 08 01:42:34 PM PDT 23 600445846 ps
T652 /workspace/coverage/default/10.edn_intr.1757494437 Oct 08 01:49:30 PM PDT 23 Oct 08 01:49:31 PM PDT 23 26915586 ps
T653 /workspace/coverage/default/9.edn_alert.3711734845 Oct 08 01:46:42 PM PDT 23 Oct 08 01:46:44 PM PDT 23 16322798 ps
T654 /workspace/coverage/default/35.edn_alert_test.934045945 Oct 08 01:52:43 PM PDT 23 Oct 08 01:52:44 PM PDT 23 27916409 ps
T177 /workspace/coverage/default/80.edn_err.2538537290 Oct 08 01:44:28 PM PDT 23 Oct 08 01:44:30 PM PDT 23 24247887 ps
T655 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1116743094 Oct 08 01:43:41 PM PDT 23 Oct 08 02:03:01 PM PDT 23 49618952547 ps
T656 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2987520270 Oct 08 01:45:42 PM PDT 23 Oct 08 01:59:25 PM PDT 23 70069390967 ps
T657 /workspace/coverage/default/27.edn_intr.1774415451 Oct 08 01:45:53 PM PDT 23 Oct 08 01:45:54 PM PDT 23 45830389 ps
T658 /workspace/coverage/default/63.edn_err.3719723343 Oct 08 01:46:27 PM PDT 23 Oct 08 01:46:28 PM PDT 23 33354065 ps
T659 /workspace/coverage/default/19.edn_err.1275078757 Oct 08 01:43:23 PM PDT 23 Oct 08 01:43:25 PM PDT 23 42996017 ps
T660 /workspace/coverage/default/34.edn_genbits.1471735148 Oct 08 01:45:27 PM PDT 23 Oct 08 01:45:29 PM PDT 23 80123425 ps
T661 /workspace/coverage/default/42.edn_alert.969447346 Oct 08 01:47:09 PM PDT 23 Oct 08 01:47:10 PM PDT 23 20028673 ps
T283 /workspace/coverage/default/9.edn_genbits.3773723900 Oct 08 01:55:46 PM PDT 23 Oct 08 01:55:48 PM PDT 23 43244097 ps
T662 /workspace/coverage/default/30.edn_alert_test.516695361 Oct 08 01:48:28 PM PDT 23 Oct 08 01:48:29 PM PDT 23 31952508 ps
T663 /workspace/coverage/default/3.edn_err.1409555746 Oct 08 01:43:13 PM PDT 23 Oct 08 01:43:14 PM PDT 23 19386484 ps
T664 /workspace/coverage/default/34.edn_alert.2102897317 Oct 08 01:46:43 PM PDT 23 Oct 08 01:46:44 PM PDT 23 67259773 ps
T665 /workspace/coverage/default/28.edn_alert_test.4082219524 Oct 08 01:44:08 PM PDT 23 Oct 08 01:44:09 PM PDT 23 18946789 ps
T666 /workspace/coverage/default/9.edn_err.2153124354 Oct 08 01:43:54 PM PDT 23 Oct 08 01:43:56 PM PDT 23 19151533 ps
T124 /workspace/coverage/default/0.edn_disable_auto_req_mode.1591093972 Oct 08 01:12:35 PM PDT 23 Oct 08 01:12:37 PM PDT 23 126234509 ps
T667 /workspace/coverage/default/38.edn_intr.1141012828 Oct 08 01:44:18 PM PDT 23 Oct 08 01:44:19 PM PDT 23 93022502 ps
T668 /workspace/coverage/default/5.edn_smoke.983352424 Oct 08 01:43:14 PM PDT 23 Oct 08 01:43:15 PM PDT 23 33122586 ps
T669 /workspace/coverage/default/38.edn_disable_auto_req_mode.1242186153 Oct 08 01:44:20 PM PDT 23 Oct 08 01:44:22 PM PDT 23 26631029 ps
T670 /workspace/coverage/default/42.edn_smoke.3345744591 Oct 08 01:46:28 PM PDT 23 Oct 08 01:46:29 PM PDT 23 27948604 ps
T671 /workspace/coverage/default/17.edn_genbits.4098974149 Oct 08 01:50:19 PM PDT 23 Oct 08 01:50:20 PM PDT 23 58727489 ps
T672 /workspace/coverage/default/17.edn_smoke.3032893161 Oct 08 01:42:21 PM PDT 23 Oct 08 01:42:22 PM PDT 23 15848403 ps
T673 /workspace/coverage/default/29.edn_disable.2552978094 Oct 08 01:46:24 PM PDT 23 Oct 08 01:46:25 PM PDT 23 12727890 ps
T242 /workspace/coverage/default/21.edn_disable_auto_req_mode.2401193341 Oct 08 01:43:29 PM PDT 23 Oct 08 01:43:30 PM PDT 23 24277406 ps
T674 /workspace/coverage/default/10.edn_alert.944270709 Oct 08 01:43:36 PM PDT 23 Oct 08 01:43:37 PM PDT 23 33864117 ps
T675 /workspace/coverage/default/18.edn_disable_auto_req_mode.107016254 Oct 08 01:42:40 PM PDT 23 Oct 08 01:42:42 PM PDT 23 36672977 ps
T676 /workspace/coverage/default/29.edn_stress_all.2117885518 Oct 08 01:42:54 PM PDT 23 Oct 08 01:42:55 PM PDT 23 38779978 ps
T677 /workspace/coverage/default/6.edn_smoke.3280165285 Oct 08 01:49:04 PM PDT 23 Oct 08 01:49:05 PM PDT 23 37617912 ps
T678 /workspace/coverage/default/16.edn_smoke.2429718001 Oct 08 01:42:05 PM PDT 23 Oct 08 01:42:07 PM PDT 23 13436241 ps
T268 /workspace/coverage/default/42.edn_genbits.1039774630 Oct 08 01:43:44 PM PDT 23 Oct 08 01:43:45 PM PDT 23 50333211 ps
T679 /workspace/coverage/default/4.edn_disable.4139569253 Oct 08 01:55:42 PM PDT 23 Oct 08 01:55:43 PM PDT 23 22932104 ps
T680 /workspace/coverage/default/5.edn_disable.1168235502 Oct 08 01:46:13 PM PDT 23 Oct 08 01:46:14 PM PDT 23 46052908 ps
T258 /workspace/coverage/default/53.edn_err.3187829360 Oct 08 01:56:19 PM PDT 23 Oct 08 01:56:20 PM PDT 23 26655586 ps
T681 /workspace/coverage/default/62.edn_err.1068316676 Oct 08 01:47:33 PM PDT 23 Oct 08 01:47:35 PM PDT 23 42992744 ps
T262 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3126246456 Oct 08 01:43:52 PM PDT 23 Oct 08 01:58:02 PM PDT 23 36237245500 ps
T249 /workspace/coverage/default/17.edn_err.1637094581 Oct 08 01:47:42 PM PDT 23 Oct 08 01:47:43 PM PDT 23 22023503 ps
T682 /workspace/coverage/default/22.edn_stress_all.181965691 Oct 08 01:48:50 PM PDT 23 Oct 08 01:48:52 PM PDT 23 107414519 ps
T683 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2232714200 Oct 08 01:47:25 PM PDT 23 Oct 08 01:59:12 PM PDT 23 65357302197 ps
T684 /workspace/coverage/default/35.edn_alert.106030247 Oct 08 01:44:21 PM PDT 23 Oct 08 01:44:23 PM PDT 23 66732815 ps
T685 /workspace/coverage/default/1.edn_smoke.2163292999 Oct 08 01:48:00 PM PDT 23 Oct 08 01:48:01 PM PDT 23 42177433 ps
T686 /workspace/coverage/default/6.edn_err.4268922467 Oct 08 01:42:43 PM PDT 23 Oct 08 01:42:44 PM PDT 23 19027028 ps
T687 /workspace/coverage/default/11.edn_disable.1383675563 Oct 08 01:55:38 PM PDT 23 Oct 08 01:55:40 PM PDT 23 13651099 ps
T688 /workspace/coverage/default/32.edn_disable_auto_req_mode.1951864053 Oct 08 01:47:30 PM PDT 23 Oct 08 01:47:31 PM PDT 23 22178701 ps
T689 /workspace/coverage/default/2.edn_err.605774146 Oct 08 01:41:04 PM PDT 23 Oct 08 01:41:05 PM PDT 23 24608150 ps
T169 /workspace/coverage/default/38.edn_err.568251937 Oct 08 02:17:09 PM PDT 23 Oct 08 02:17:10 PM PDT 23 19204078 ps
T690 /workspace/coverage/default/23.edn_genbits.3264217227 Oct 08 01:48:48 PM PDT 23 Oct 08 01:48:49 PM PDT 23 23793570 ps
T691 /workspace/coverage/default/28.edn_disable.459552651 Oct 08 01:48:27 PM PDT 23 Oct 08 01:48:28 PM PDT 23 50416879 ps
T692 /workspace/coverage/default/23.edn_disable_auto_req_mode.3705789474 Oct 08 01:45:45 PM PDT 23 Oct 08 01:45:46 PM PDT 23 76516390 ps
T693 /workspace/coverage/default/73.edn_err.1681225389 Oct 08 01:53:50 PM PDT 23 Oct 08 01:53:51 PM PDT 23 20952436 ps
T108 /workspace/coverage/default/15.edn_intr.2225265119 Oct 08 01:42:05 PM PDT 23 Oct 08 01:42:06 PM PDT 23 23041692 ps
T694 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2968867352 Oct 08 01:42:08 PM PDT 23 Oct 08 02:14:55 PM PDT 23 155328996647 ps
T135 /workspace/coverage/default/8.edn_disable.1051012854 Oct 08 01:48:52 PM PDT 23 Oct 08 01:48:53 PM PDT 23 27104863 ps
T695 /workspace/coverage/default/30.edn_genbits.3683768763 Oct 08 01:47:25 PM PDT 23 Oct 08 01:47:26 PM PDT 23 54151330 ps
T696 /workspace/coverage/default/32.edn_smoke.1767654633 Oct 08 01:50:25 PM PDT 23 Oct 08 01:50:31 PM PDT 23 29507299 ps
T697 /workspace/coverage/default/32.edn_intr.3693532660 Oct 08 01:43:16 PM PDT 23 Oct 08 01:43:17 PM PDT 23 36243607 ps
T698 /workspace/coverage/default/31.edn_smoke.4245653878 Oct 08 01:50:34 PM PDT 23 Oct 08 01:50:35 PM PDT 23 14515244 ps
T699 /workspace/coverage/default/44.edn_disable_auto_req_mode.4137124319 Oct 08 01:50:57 PM PDT 23 Oct 08 01:50:58 PM PDT 23 59167707 ps
T184 /workspace/coverage/default/61.edn_err.1018055807 Oct 08 03:13:24 PM PDT 23 Oct 08 03:13:26 PM PDT 23 31183452 ps
T700 /workspace/coverage/default/25.edn_disable_auto_req_mode.1454606208 Oct 08 01:44:33 PM PDT 23 Oct 08 01:44:34 PM PDT 23 24767064 ps
T701 /workspace/coverage/default/93.edn_err.3833315786 Oct 08 01:44:45 PM PDT 23 Oct 08 01:44:46 PM PDT 23 32957965 ps
T702 /workspace/coverage/default/29.edn_alert.1042200512 Oct 08 01:45:19 PM PDT 23 Oct 08 01:45:20 PM PDT 23 26779225 ps
T703 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1065819324 Oct 08 01:43:14 PM PDT 23 Oct 08 01:48:35 PM PDT 23 13593671495 ps
T704 /workspace/coverage/default/25.edn_stress_all.308220291 Oct 08 01:42:43 PM PDT 23 Oct 08 01:42:45 PM PDT 23 31781187 ps
T705 /workspace/coverage/default/24.edn_stress_all.651588207 Oct 08 01:49:07 PM PDT 23 Oct 08 01:49:11 PM PDT 23 826401553 ps
T706 /workspace/coverage/default/4.edn_regwen.2298543830 Oct 08 01:43:27 PM PDT 23 Oct 08 01:43:28 PM PDT 23 12859525 ps
T707 /workspace/coverage/default/9.edn_smoke.873388653 Oct 08 01:48:52 PM PDT 23 Oct 08 01:48:53 PM PDT 23 41408552 ps
T708 /workspace/coverage/default/46.edn_disable.3123981718 Oct 08 01:49:59 PM PDT 23 Oct 08 01:50:00 PM PDT 23 24501438 ps
T709 /workspace/coverage/default/7.edn_stress_all.1342564230 Oct 08 01:56:24 PM PDT 23 Oct 08 01:56:27 PM PDT 23 451469110 ps
T235 /workspace/coverage/default/67.edn_err.1273298030 Oct 08 02:29:25 PM PDT 23 Oct 08 02:29:26 PM PDT 23 59730879 ps
T710 /workspace/coverage/default/5.edn_alert.3383968683 Oct 08 01:46:12 PM PDT 23 Oct 08 01:46:13 PM PDT 23 56168421 ps
T711 /workspace/coverage/default/27.edn_disable_auto_req_mode.1628606098 Oct 08 01:46:11 PM PDT 23 Oct 08 01:46:13 PM PDT 23 127629431 ps
T712 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4005963610 Oct 08 01:50:33 PM PDT 23 Oct 08 01:54:38 PM PDT 23 40494019573 ps
T713 /workspace/coverage/default/20.edn_disable.39851403 Oct 08 01:44:37 PM PDT 23 Oct 08 01:44:38 PM PDT 23 18782836 ps
T714 /workspace/coverage/default/70.edn_err.2136367506 Oct 08 01:53:50 PM PDT 23 Oct 08 01:53:52 PM PDT 23 38069025 ps
T715 /workspace/coverage/default/24.edn_genbits.1171589822 Oct 08 01:45:45 PM PDT 23 Oct 08 01:45:46 PM PDT 23 72137641 ps
T716 /workspace/coverage/default/34.edn_disable_auto_req_mode.1294121584 Oct 08 01:49:19 PM PDT 23 Oct 08 01:49:20 PM PDT 23 118868520 ps
T717 /workspace/coverage/default/19.edn_alert.71185511 Oct 08 01:44:52 PM PDT 23 Oct 08 01:44:53 PM PDT 23 26210232 ps
T718 /workspace/coverage/default/48.edn_alert.547968410 Oct 08 01:48:23 PM PDT 23 Oct 08 01:48:25 PM PDT 23 19024307 ps
T719 /workspace/coverage/default/14.edn_stress_all.1828699127 Oct 08 01:51:30 PM PDT 23 Oct 08 01:51:34 PM PDT 23 157202145 ps
T720 /workspace/coverage/default/22.edn_intr.3595677794 Oct 08 01:55:14 PM PDT 23 Oct 08 01:55:15 PM PDT 23 20092214 ps
T721 /workspace/coverage/default/11.edn_smoke.476636493 Oct 08 01:49:43 PM PDT 23 Oct 08 01:49:44 PM PDT 23 14820781 ps
T722 /workspace/coverage/default/31.edn_disable_auto_req_mode.4200027586 Oct 08 01:45:15 PM PDT 23 Oct 08 01:45:16 PM PDT 23 103875347 ps
T198 /workspace/coverage/default/13.edn_err.1529918551 Oct 08 01:46:08 PM PDT 23 Oct 08 01:46:09 PM PDT 23 18141431 ps
T723 /workspace/coverage/default/11.edn_genbits.2889532130 Oct 08 01:45:25 PM PDT 23 Oct 08 01:45:27 PM PDT 23 34880892 ps
T724 /workspace/coverage/default/13.edn_stress_all.3480866586 Oct 08 01:44:28 PM PDT 23 Oct 08 01:44:32 PM PDT 23 172457091 ps
T725 /workspace/coverage/default/48.edn_disable_auto_req_mode.1123951870 Oct 08 01:52:55 PM PDT 23 Oct 08 01:52:56 PM PDT 23 33703939 ps
T136 /workspace/coverage/default/23.edn_disable.119631784 Oct 08 01:43:39 PM PDT 23 Oct 08 01:43:40 PM PDT 23 43827028 ps
T726 /workspace/coverage/default/6.edn_stress_all.2770945715 Oct 08 01:44:57 PM PDT 23 Oct 08 01:45:00 PM PDT 23 490749571 ps
T727 /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4198703766 Oct 08 01:48:20 PM PDT 23 Oct 08 02:08:34 PM PDT 23 113883088808 ps
T728 /workspace/coverage/default/48.edn_alert_test.314780427 Oct 08 02:43:36 PM PDT 23 Oct 08 02:43:37 PM PDT 23 93491302 ps
T729 /workspace/coverage/default/25.edn_err.3409415965 Oct 08 01:44:25 PM PDT 23 Oct 08 01:44:26 PM PDT 23 20852054 ps

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3439354555
Short name T3
Test name
Test status
Simulation time 186008926365 ps
CPU time 591.48 seconds
Started Oct 08 01:42:23 PM PDT 23
Finished Oct 08 01:52:14 PM PDT 23
Peak memory 215348 kb
Host smart-637e4c2d-4328-453d-8fc1-4e8fe9658854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439354555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3439354555
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_genbits.1961753661
Short name T9
Test name
Test status
Simulation time 75369833 ps
CPU time 1.49 seconds
Started Oct 08 01:44:16 PM PDT 23
Finished Oct 08 01:44:18 PM PDT 23
Peak memory 214356 kb
Host smart-29da06ad-1fee-435b-9b78-115c4b3773b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961753661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1961753661
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.492266668
Short name T15
Test name
Test status
Simulation time 361070833 ps
CPU time 3.71 seconds
Started Oct 08 01:41:35 PM PDT 23
Finished Oct 08 01:41:39 PM PDT 23
Peak memory 232128 kb
Host smart-b83440fe-d96f-41d7-9aab-1cd24ad7b2fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492266668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.492266668
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/45.edn_genbits.659598846
Short name T18
Test name
Test status
Simulation time 25834626 ps
CPU time 1.14 seconds
Started Oct 08 03:05:11 PM PDT 23
Finished Oct 08 03:05:13 PM PDT 23
Peak memory 205448 kb
Host smart-6f3d2298-b93a-493c-a0cc-5cf198318be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659598846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.659598846
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2805169617
Short name T8
Test name
Test status
Simulation time 46397825 ps
CPU time 1.03 seconds
Started Oct 08 01:50:37 PM PDT 23
Finished Oct 08 01:50:38 PM PDT 23
Peak memory 214616 kb
Host smart-29e87210-a726-4f92-b121-9cadad301074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805169617 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2805169617
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2553707364
Short name T92
Test name
Test status
Simulation time 19693500 ps
CPU time 0.96 seconds
Started Oct 08 01:43:21 PM PDT 23
Finished Oct 08 01:43:22 PM PDT 23
Peak memory 214676 kb
Host smart-f0ef5fc6-1e87-47fc-8b09-47c76f27b815
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553707364 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2553707364
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1092100194
Short name T26
Test name
Test status
Simulation time 48673046536 ps
CPU time 1075.56 seconds
Started Oct 08 03:12:42 PM PDT 23
Finished Oct 08 03:30:40 PM PDT 23
Peak memory 214652 kb
Host smart-9a17c84b-7c09-4433-b0aa-712ee893af25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092100194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1092100194
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1823157762
Short name T23
Test name
Test status
Simulation time 749412974 ps
CPU time 4.45 seconds
Started Oct 08 01:48:17 PM PDT 23
Finished Oct 08 01:48:22 PM PDT 23
Peak memory 231912 kb
Host smart-24b257f4-0f2e-4ecf-aac7-5f65538284ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823157762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1823157762
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/44.edn_alert.553842665
Short name T17
Test name
Test status
Simulation time 16262355 ps
CPU time 0.94 seconds
Started Oct 08 01:43:46 PM PDT 23
Finished Oct 08 01:43:47 PM PDT 23
Peak memory 206152 kb
Host smart-194e70f4-98af-4ede-9fa7-b4173db0f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553842665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.553842665
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/6.edn_regwen.527296704
Short name T58
Test name
Test status
Simulation time 67710776 ps
CPU time 0.88 seconds
Started Oct 08 01:41:26 PM PDT 23
Finished Oct 08 01:41:27 PM PDT 23
Peak memory 204552 kb
Host smart-f04b65c4-f2e3-410a-85c5-d13322736dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527296704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.527296704
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/27.edn_err.3435764542
Short name T105
Test name
Test status
Simulation time 34533609 ps
CPU time 1.04 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:52 PM PDT 23
Peak memory 215800 kb
Host smart-a6dec18b-05a6-4373-9de5-a826c0e7c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435764542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3435764542
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/43.edn_disable.1404279667
Short name T39
Test name
Test status
Simulation time 20747557 ps
CPU time 0.83 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:52 PM PDT 23
Peak memory 214292 kb
Host smart-f12d6e02-e8cf-415b-a3dc-e0efffb01cc3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404279667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1404279667
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3402095584
Short name T41
Test name
Test status
Simulation time 99233314 ps
CPU time 1.09 seconds
Started Oct 08 01:42:25 PM PDT 23
Finished Oct 08 01:42:26 PM PDT 23
Peak memory 214592 kb
Host smart-8264f841-73d2-4a0e-98fe-b8704e983d0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402095584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3402095584
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1081752245
Short name T148
Test name
Test status
Simulation time 306399583 ps
CPU time 2.27 seconds
Started Oct 08 01:54:44 PM PDT 23
Finished Oct 08 01:54:47 PM PDT 23
Peak memory 205824 kb
Host smart-9ee7b449-47a5-4a23-ad9d-8329c9b9fdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081752245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1081752245
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.4038750418
Short name T99
Test name
Test status
Simulation time 14054862 ps
CPU time 0.91 seconds
Started Oct 08 01:10:31 PM PDT 23
Finished Oct 08 01:10:32 PM PDT 23
Peak memory 214784 kb
Host smart-3e01349a-6860-4940-a94a-c570b2427631
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038750418 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4038750418
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.78887402
Short name T128
Test name
Test status
Simulation time 40740526 ps
CPU time 0.9 seconds
Started Oct 08 01:45:28 PM PDT 23
Finished Oct 08 01:45:31 PM PDT 23
Peak memory 214380 kb
Host smart-6e495833-4fac-4de0-923d-caa87017e654
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78887402 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.78887402
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.106175944
Short name T241
Test name
Test status
Simulation time 53221237 ps
CPU time 0.83 seconds
Started Oct 08 01:42:35 PM PDT 23
Finished Oct 08 01:42:36 PM PDT 23
Peak memory 214360 kb
Host smart-311b1826-01bf-43df-8710-d084712eab8b
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106175944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.106175944
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.1253966148
Short name T185
Test name
Test status
Simulation time 40110904 ps
CPU time 0.85 seconds
Started Oct 08 01:48:01 PM PDT 23
Finished Oct 08 01:48:02 PM PDT 23
Peak memory 214472 kb
Host smart-d205c52f-a0fc-41d0-b7b1-0408a15d0149
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253966148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1253966148
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1768770954
Short name T160
Test name
Test status
Simulation time 16835701 ps
CPU time 0.95 seconds
Started Oct 08 01:40:55 PM PDT 23
Finished Oct 08 01:40:56 PM PDT 23
Peak memory 205660 kb
Host smart-93affb98-71ad-4ce1-be2c-d6d2885c52b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768770954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1768770954
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1386724621
Short name T93
Test name
Test status
Simulation time 17900661 ps
CPU time 0.92 seconds
Started Oct 08 01:43:15 PM PDT 23
Finished Oct 08 01:43:16 PM PDT 23
Peak memory 214576 kb
Host smart-10c5f60a-55c0-40af-9a66-0a4257382b78
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386724621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1386724621
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_intr.2375338752
Short name T28
Test name
Test status
Simulation time 22693606 ps
CPU time 0.89 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:45 PM PDT 23
Peak memory 214840 kb
Host smart-fb58187c-633b-4bc9-b333-aa96e04cd205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375338752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2375338752
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3408736703
Short name T174
Test name
Test status
Simulation time 17288019 ps
CPU time 0.92 seconds
Started Oct 08 01:55:12 PM PDT 23
Finished Oct 08 01:55:13 PM PDT 23
Peak memory 214652 kb
Host smart-18bb0e0d-c556-4f4b-8cb8-ba58dd838fde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408736703 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3408736703
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_disable.283631103
Short name T35
Test name
Test status
Simulation time 19015590 ps
CPU time 0.82 seconds
Started Oct 08 01:44:18 PM PDT 23
Finished Oct 08 01:44:19 PM PDT 23
Peak memory 214384 kb
Host smart-f38b2b5b-c416-4488-a897-ba55c4a2485a
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283631103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.283631103
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4216068591
Short name T10
Test name
Test status
Simulation time 70458931 ps
CPU time 0.99 seconds
Started Oct 08 01:53:51 PM PDT 23
Finished Oct 08 01:53:53 PM PDT 23
Peak memory 214668 kb
Host smart-85d4abff-eb9e-49ba-a63a-6cddd4d0d53f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216068591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4216068591
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.2294520200
Short name T266
Test name
Test status
Simulation time 109157474 ps
CPU time 1.34 seconds
Started Oct 08 01:43:36 PM PDT 23
Finished Oct 08 01:43:37 PM PDT 23
Peak memory 214376 kb
Host smart-74d3cbb4-1da4-42bd-b3b2-7e401e1eaf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294520200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2294520200
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.1362077920
Short name T289
Test name
Test status
Simulation time 23502420 ps
CPU time 0.89 seconds
Started Oct 08 01:42:50 PM PDT 23
Finished Oct 08 01:42:52 PM PDT 23
Peak memory 204748 kb
Host smart-c0861c12-58af-40de-afa6-0a3bf9258ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362077920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1362077920
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/44.edn_genbits.4235993673
Short name T260
Test name
Test status
Simulation time 24748335 ps
CPU time 0.99 seconds
Started Oct 08 01:52:03 PM PDT 23
Finished Oct 08 01:52:05 PM PDT 23
Peak memory 205368 kb
Host smart-6fa864dd-f403-44a3-96a1-6d563cdc9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235993673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.4235993673
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_disable.119631784
Short name T136
Test name
Test status
Simulation time 43827028 ps
CPU time 0.84 seconds
Started Oct 08 01:43:39 PM PDT 23
Finished Oct 08 01:43:40 PM PDT 23
Peak memory 214432 kb
Host smart-6b831239-1db4-4da6-9d09-3a4d95fc9336
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119631784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.119631784
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.443553321
Short name T127
Test name
Test status
Simulation time 13305192 ps
CPU time 0.86 seconds
Started Oct 08 01:45:16 PM PDT 23
Finished Oct 08 01:45:17 PM PDT 23
Peak memory 214480 kb
Host smart-b4a6acf7-c047-4ef6-9e0d-3253c7f114c8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443553321 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.443553321
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable.3516717395
Short name T131
Test name
Test status
Simulation time 32488143 ps
CPU time 0.84 seconds
Started Oct 08 01:43:35 PM PDT 23
Finished Oct 08 01:43:36 PM PDT 23
Peak memory 214288 kb
Host smart-2c65c15a-42f4-4bca-8392-c390638c0141
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516717395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3516717395
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/23.edn_intr.2960462759
Short name T109
Test name
Test status
Simulation time 46312401 ps
CPU time 0.87 seconds
Started Oct 08 01:46:26 PM PDT 23
Finished Oct 08 01:46:27 PM PDT 23
Peak memory 224560 kb
Host smart-0f2bcc5c-f239-428a-999e-a9efec0bf251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960462759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2960462759
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/13.edn_disable.2271748128
Short name T200
Test name
Test status
Simulation time 30269405 ps
CPU time 0.86 seconds
Started Oct 08 01:45:42 PM PDT 23
Finished Oct 08 01:45:43 PM PDT 23
Peak memory 214384 kb
Host smart-957a7486-1e1b-4ead-bb73-77a1b4fd0f3e
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271748128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2271748128
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1089905416
Short name T36
Test name
Test status
Simulation time 21682895 ps
CPU time 1.06 seconds
Started Oct 08 01:48:57 PM PDT 23
Finished Oct 08 01:48:58 PM PDT 23
Peak memory 214688 kb
Host smart-ce700baf-9277-4074-9317-bee8a31024bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089905416 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1089905416
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.588881633
Short name T90
Test name
Test status
Simulation time 18255923 ps
CPU time 0.87 seconds
Started Oct 08 01:41:01 PM PDT 23
Finished Oct 08 01:41:02 PM PDT 23
Peak memory 214584 kb
Host smart-0f8f7bad-15de-49b9-a027-871d08dd0b3f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588881633 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.588881633
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/9.edn_genbits.3773723900
Short name T283
Test name
Test status
Simulation time 43244097 ps
CPU time 1.1 seconds
Started Oct 08 01:55:46 PM PDT 23
Finished Oct 08 01:55:48 PM PDT 23
Peak memory 214388 kb
Host smart-dee888d2-2f3f-4169-ada7-3c0d6c1fe4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773723900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3773723900
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3656827273
Short name T586
Test name
Test status
Simulation time 149654271 ps
CPU time 0.97 seconds
Started Oct 08 01:45:06 PM PDT 23
Finished Oct 08 01:45:07 PM PDT 23
Peak memory 205248 kb
Host smart-c8ecd3ca-d5f0-4cd7-b84d-872584b79f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656827273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3656827273
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.2765894574
Short name T16
Test name
Test status
Simulation time 35235833 ps
CPU time 0.97 seconds
Started Oct 08 01:48:50 PM PDT 23
Finished Oct 08 01:48:52 PM PDT 23
Peak memory 205116 kb
Host smart-7fde7fc5-d894-4d24-9237-53e294d96fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765894574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2765894574
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert.3427856397
Short name T54
Test name
Test status
Simulation time 41402062 ps
CPU time 0.93 seconds
Started Oct 08 01:42:51 PM PDT 23
Finished Oct 08 01:42:53 PM PDT 23
Peak memory 204968 kb
Host smart-5b1f7e82-0e6c-4abf-8aa5-81eb41d4b61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427856397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3427856397
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1761923218
Short name T301
Test name
Test status
Simulation time 19690558 ps
CPU time 0.95 seconds
Started Oct 08 01:44:49 PM PDT 23
Finished Oct 08 01:44:50 PM PDT 23
Peak memory 204604 kb
Host smart-461b9c8c-ee87-45dd-aa94-aa719ce2b351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761923218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1761923218
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_regwen.2828299623
Short name T153
Test name
Test status
Simulation time 49896126 ps
CPU time 0.86 seconds
Started Oct 08 01:43:20 PM PDT 23
Finished Oct 08 01:43:21 PM PDT 23
Peak memory 204632 kb
Host smart-28287e8b-7e7f-448f-b6c5-822056581f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828299623 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2828299623
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3126246456
Short name T262
Test name
Test status
Simulation time 36237245500 ps
CPU time 849.69 seconds
Started Oct 08 01:43:52 PM PDT 23
Finished Oct 08 01:58:02 PM PDT 23
Peak memory 214820 kb
Host smart-267b2efa-86e5-404b-ad24-3ab0f7d7455f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126246456 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3126246456
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.4070928394
Short name T142
Test name
Test status
Simulation time 42048885281 ps
CPU time 1043.51 seconds
Started Oct 08 01:53:49 PM PDT 23
Finished Oct 08 02:11:13 PM PDT 23
Peak memory 215040 kb
Host smart-3665df45-523c-4e66-8f78-9ef7a30c58a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070928394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.4070928394
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_genbits.391822025
Short name T101
Test name
Test status
Simulation time 24705215 ps
CPU time 1.11 seconds
Started Oct 08 01:42:53 PM PDT 23
Finished Oct 08 01:42:54 PM PDT 23
Peak memory 205664 kb
Host smart-b28b8c9a-8b1f-456c-8409-303d142bb34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391822025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.391822025
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3462587679
Short name T272
Test name
Test status
Simulation time 1225828144 ps
CPU time 2.19 seconds
Started Oct 08 01:46:57 PM PDT 23
Finished Oct 08 01:47:00 PM PDT 23
Peak memory 205772 kb
Host smart-c80711de-d099-44f7-971d-565ec90c9111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462587679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3462587679
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1301271273
Short name T284
Test name
Test status
Simulation time 67633157 ps
CPU time 1.27 seconds
Started Oct 08 12:44:35 PM PDT 23
Finished Oct 08 12:44:36 PM PDT 23
Peak memory 214280 kb
Host smart-b7480a85-ed27-40fc-965a-3619d9f15763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301271273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1301271273
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4244656493
Short name T263
Test name
Test status
Simulation time 119352866924 ps
CPU time 705.65 seconds
Started Oct 08 12:30:09 PM PDT 23
Finished Oct 08 12:41:55 PM PDT 23
Peak memory 215696 kb
Host smart-39aa771a-367e-4a47-9c71-8b5244f43890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244656493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4244656493
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.190763492
Short name T250
Test name
Test status
Simulation time 94572718 ps
CPU time 0.96 seconds
Started Oct 08 01:43:36 PM PDT 23
Finished Oct 08 01:43:37 PM PDT 23
Peak memory 214652 kb
Host smart-187f0f59-b544-428e-bfc6-56a0c56efd14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190763492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.190763492
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3289897076
Short name T265
Test name
Test status
Simulation time 83989561325 ps
CPU time 732.39 seconds
Started Oct 08 01:44:42 PM PDT 23
Finished Oct 08 01:56:55 PM PDT 23
Peak memory 215856 kb
Host smart-573b17b6-adcd-4534-8f45-5ebb60311b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289897076 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3289897076
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_err.12779927
Short name T4
Test name
Test status
Simulation time 19249503 ps
CPU time 1.15 seconds
Started Oct 08 01:43:26 PM PDT 23
Finished Oct 08 01:43:27 PM PDT 23
Peak memory 222168 kb
Host smart-4b4e2b26-420f-4719-b411-6c2cecba5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12779927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.12779927
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1414200123
Short name T286
Test name
Test status
Simulation time 15306561 ps
CPU time 1.05 seconds
Started Oct 08 01:41:01 PM PDT 23
Finished Oct 08 01:41:02 PM PDT 23
Peak memory 205108 kb
Host smart-9b9d7a63-eb0c-4890-a331-40b144b8e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414200123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1414200123
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_genbits.4126138622
Short name T278
Test name
Test status
Simulation time 28114876 ps
CPU time 0.92 seconds
Started Oct 08 01:44:31 PM PDT 23
Finished Oct 08 01:44:32 PM PDT 23
Peak memory 204992 kb
Host smart-89acfaf6-b5ae-4e2e-b344-ce204b810fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126138622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4126138622
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_alert.4168442425
Short name T77
Test name
Test status
Simulation time 23496397 ps
CPU time 0.98 seconds
Started Oct 08 01:46:41 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 206116 kb
Host smart-19e44ed6-73d4-4dbe-a58e-3ed3855e19a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168442425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.4168442425
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/41.edn_genbits.539495132
Short name T261
Test name
Test status
Simulation time 16486626 ps
CPU time 0.95 seconds
Started Oct 08 02:57:31 PM PDT 23
Finished Oct 08 02:57:32 PM PDT 23
Peak memory 205112 kb
Host smart-330fef46-eac1-45f4-9e5e-a84fdb44e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539495132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.539495132
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2225265119
Short name T108
Test name
Test status
Simulation time 23041692 ps
CPU time 0.86 seconds
Started Oct 08 01:42:05 PM PDT 23
Finished Oct 08 01:42:06 PM PDT 23
Peak memory 214676 kb
Host smart-a78bd523-c18b-40fb-bd4c-9189ae919970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225265119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2225265119
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/11.edn_intr.1208691608
Short name T589
Test name
Test status
Simulation time 22645780 ps
CPU time 0.88 seconds
Started Oct 08 01:43:30 PM PDT 23
Finished Oct 08 01:43:31 PM PDT 23
Peak memory 214732 kb
Host smart-40a64aad-ff22-4625-a496-d5c8a7186db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208691608 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1208691608
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1591093972
Short name T124
Test name
Test status
Simulation time 126234509 ps
CPU time 1.1 seconds
Started Oct 08 01:12:35 PM PDT 23
Finished Oct 08 01:12:37 PM PDT 23
Peak memory 214524 kb
Host smart-da4a157c-8cdf-4664-9d1d-577be42e7bf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591093972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1591093972
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_disable.1383675563
Short name T687
Test name
Test status
Simulation time 13651099 ps
CPU time 0.82 seconds
Started Oct 08 01:55:38 PM PDT 23
Finished Oct 08 01:55:40 PM PDT 23
Peak memory 214256 kb
Host smart-bd23dfef-c53a-40d4-9eae-149ca4773f09
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383675563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1383675563
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3326991139
Short name T403
Test name
Test status
Simulation time 201789332 ps
CPU time 1.18 seconds
Started Oct 08 12:57:05 PM PDT 23
Finished Oct 08 12:57:06 PM PDT 23
Peak memory 205812 kb
Host smart-05115f02-98a7-4e82-9a0f-13cbb7b9002c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326991139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3326991139
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1720651220
Short name T425
Test name
Test status
Simulation time 66121594 ps
CPU time 2.07 seconds
Started Oct 08 01:25:03 PM PDT 23
Finished Oct 08 01:25:05 PM PDT 23
Peak memory 205872 kb
Host smart-67d19815-fcbd-4b9e-9717-41cca4efa3ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720651220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1720651220
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.783481239
Short name T217
Test name
Test status
Simulation time 13942416 ps
CPU time 0.9 seconds
Started Oct 08 12:55:11 PM PDT 23
Finished Oct 08 12:55:12 PM PDT 23
Peak memory 205732 kb
Host smart-053ba1d0-0e27-4d91-859e-2d54d3315cef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783481239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.783481239
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.211834297
Short name T376
Test name
Test status
Simulation time 22346717 ps
CPU time 1.2 seconds
Started Oct 08 01:19:29 PM PDT 23
Finished Oct 08 01:19:30 PM PDT 23
Peak memory 213928 kb
Host smart-4e1e87c5-7201-4493-9912-10aa460f35ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211834297 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.211834297
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1594386793
Short name T432
Test name
Test status
Simulation time 14894807 ps
CPU time 0.88 seconds
Started Oct 08 12:57:16 PM PDT 23
Finished Oct 08 12:57:17 PM PDT 23
Peak memory 205620 kb
Host smart-6a72bcc2-5931-45ec-aa8c-0bb5ccf02ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594386793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1594386793
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1864993370
Short name T447
Test name
Test status
Simulation time 47204309 ps
CPU time 0.78 seconds
Started Oct 08 01:41:43 PM PDT 23
Finished Oct 08 01:41:46 PM PDT 23
Peak memory 205564 kb
Host smart-0a8680a6-efe2-4556-9b38-fa5ae2e3067e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864993370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1864993370
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.370530520
Short name T452
Test name
Test status
Simulation time 108918298 ps
CPU time 1.09 seconds
Started Oct 08 02:40:10 PM PDT 23
Finished Oct 08 02:40:12 PM PDT 23
Peak memory 205668 kb
Host smart-87940618-f797-4071-8ebd-f60d9dd29805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370530520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.370530520
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3157002272
Short name T329
Test name
Test status
Simulation time 61317976 ps
CPU time 2.48 seconds
Started Oct 08 01:35:21 PM PDT 23
Finished Oct 08 01:35:23 PM PDT 23
Peak memory 213940 kb
Host smart-e7ad8f2b-3cb1-4988-aa1f-46dae2c06040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157002272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3157002272
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2484785327
Short name T227
Test name
Test status
Simulation time 126428231 ps
CPU time 1.43 seconds
Started Oct 08 01:38:35 PM PDT 23
Finished Oct 08 01:38:36 PM PDT 23
Peak memory 205812 kb
Host smart-ecfe8771-b0c2-41de-956e-0ab0cad095b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484785327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2484785327
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3716818240
Short name T361
Test name
Test status
Simulation time 109409629 ps
CPU time 3.1 seconds
Started Oct 08 01:38:57 PM PDT 23
Finished Oct 08 01:39:00 PM PDT 23
Peak memory 205788 kb
Host smart-39e30b8f-8ac1-43fe-ad42-34257e3198ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716818240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3716818240
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1778337739
Short name T328
Test name
Test status
Simulation time 38092945 ps
CPU time 0.82 seconds
Started Oct 08 12:54:22 PM PDT 23
Finished Oct 08 12:54:24 PM PDT 23
Peak memory 205612 kb
Host smart-3570107a-9901-4486-a079-66506448d8f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778337739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1778337739
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3766298856
Short name T337
Test name
Test status
Simulation time 36079517 ps
CPU time 1.56 seconds
Started Oct 08 01:38:50 PM PDT 23
Finished Oct 08 01:38:51 PM PDT 23
Peak memory 216244 kb
Host smart-7f3ecbd9-381c-4150-bf47-63da27d7ba65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766298856 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3766298856
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2285128144
Short name T220
Test name
Test status
Simulation time 14389813 ps
CPU time 0.9 seconds
Started Oct 08 01:42:51 PM PDT 23
Finished Oct 08 01:42:53 PM PDT 23
Peak memory 205584 kb
Host smart-a179f495-3796-458a-ac81-9aabb5db2a67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285128144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2285128144
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.44972401
Short name T348
Test name
Test status
Simulation time 19535837 ps
CPU time 0.77 seconds
Started Oct 08 01:38:57 PM PDT 23
Finished Oct 08 01:38:58 PM PDT 23
Peak memory 205504 kb
Host smart-9374e608-ec69-4bcf-9d40-d1b5560d3add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44972401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.44972401
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2649403068
Short name T213
Test name
Test status
Simulation time 18291244 ps
CPU time 1.12 seconds
Started Oct 08 01:42:58 PM PDT 23
Finished Oct 08 01:43:00 PM PDT 23
Peak memory 205596 kb
Host smart-2cc71620-ed30-45ce-b847-8e299162c354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649403068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2649403068
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2763321661
Short name T426
Test name
Test status
Simulation time 47363241 ps
CPU time 1.5 seconds
Started Oct 08 01:33:11 PM PDT 23
Finished Oct 08 01:33:13 PM PDT 23
Peak memory 213864 kb
Host smart-25e7eb8f-57a9-4866-b769-ed06cea9d994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763321661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2763321661
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2511967602
Short name T223
Test name
Test status
Simulation time 70265741 ps
CPU time 1.39 seconds
Started Oct 08 01:18:44 PM PDT 23
Finished Oct 08 01:18:46 PM PDT 23
Peak memory 205784 kb
Host smart-a10971b0-22f7-47ce-81de-4dfb58451ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511967602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2511967602
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3878707120
Short name T327
Test name
Test status
Simulation time 49734324 ps
CPU time 1.67 seconds
Started Oct 08 01:39:02 PM PDT 23
Finished Oct 08 01:39:04 PM PDT 23
Peak memory 214100 kb
Host smart-0deac15e-529d-4d73-aed4-a56691ba021c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878707120 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3878707120
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3190304807
Short name T437
Test name
Test status
Simulation time 29348673 ps
CPU time 0.81 seconds
Started Oct 08 01:42:26 PM PDT 23
Finished Oct 08 01:42:27 PM PDT 23
Peak memory 205580 kb
Host smart-0949847d-d475-4358-8181-defc7a953cd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190304807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3190304807
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2829480961
Short name T419
Test name
Test status
Simulation time 12451677 ps
CPU time 0.84 seconds
Started Oct 08 01:54:30 PM PDT 23
Finished Oct 08 01:54:31 PM PDT 23
Peak memory 205640 kb
Host smart-d678b574-dccc-416f-9bfc-9c639dddde8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829480961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2829480961
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.160544823
Short name T349
Test name
Test status
Simulation time 49265722 ps
CPU time 1.27 seconds
Started Oct 08 01:47:20 PM PDT 23
Finished Oct 08 01:47:22 PM PDT 23
Peak memory 205756 kb
Host smart-ca704560-179f-4605-9978-349cc17c4d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160544823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.160544823
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3707357539
Short name T152
Test name
Test status
Simulation time 1306890844 ps
CPU time 4.42 seconds
Started Oct 08 01:42:12 PM PDT 23
Finished Oct 08 01:42:16 PM PDT 23
Peak memory 214096 kb
Host smart-e7f87b21-9385-4613-8766-6f6d99083446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707357539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3707357539
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2024922253
Short name T409
Test name
Test status
Simulation time 159035623 ps
CPU time 2.31 seconds
Started Oct 08 01:46:17 PM PDT 23
Finished Oct 08 01:46:19 PM PDT 23
Peak memory 205756 kb
Host smart-8f773e63-ef5c-4d1b-9887-2c5037b559ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024922253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2024922253
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3069522281
Short name T331
Test name
Test status
Simulation time 24347848 ps
CPU time 1.26 seconds
Started Oct 08 01:40:58 PM PDT 23
Finished Oct 08 01:40:59 PM PDT 23
Peak memory 214060 kb
Host smart-517f884c-eabb-45e7-b23d-4afb38642d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069522281 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3069522281
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2154050759
Short name T224
Test name
Test status
Simulation time 14029320 ps
CPU time 0.87 seconds
Started Oct 08 01:39:14 PM PDT 23
Finished Oct 08 01:39:16 PM PDT 23
Peak memory 205580 kb
Host smart-8607a222-c89d-4bcb-86a0-c957611eb5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154050759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2154050759
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1993200694
Short name T399
Test name
Test status
Simulation time 132113421 ps
CPU time 1.38 seconds
Started Oct 08 01:40:25 PM PDT 23
Finished Oct 08 01:40:27 PM PDT 23
Peak memory 205888 kb
Host smart-c1721561-f570-4289-b0f2-4dcacd74a1d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993200694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1993200694
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2447424428
Short name T416
Test name
Test status
Simulation time 476324861 ps
CPU time 4.12 seconds
Started Oct 08 01:39:09 PM PDT 23
Finished Oct 08 01:39:14 PM PDT 23
Peak memory 214096 kb
Host smart-e03b82df-cd82-402a-8e8c-691590ff495c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447424428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2447424428
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3738441170
Short name T274
Test name
Test status
Simulation time 84961243 ps
CPU time 2.35 seconds
Started Oct 08 01:46:43 PM PDT 23
Finished Oct 08 01:46:46 PM PDT 23
Peak memory 205788 kb
Host smart-c8d59cdf-e8fa-4119-98f9-d7a729bc7b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738441170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3738441170
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4274295493
Short name T334
Test name
Test status
Simulation time 33375247 ps
CPU time 0.83 seconds
Started Oct 08 01:40:13 PM PDT 23
Finished Oct 08 01:40:14 PM PDT 23
Peak memory 205652 kb
Host smart-b70b8c59-cb21-4ee4-b6cb-f3bba97dfd3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274295493 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4274295493
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1193397645
Short name T383
Test name
Test status
Simulation time 145882379 ps
CPU time 0.9 seconds
Started Oct 08 01:49:22 PM PDT 23
Finished Oct 08 01:49:23 PM PDT 23
Peak memory 205780 kb
Host smart-ce220634-4dbe-4cb4-bbe7-d7b3b1e7319a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193397645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1193397645
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3080406127
Short name T336
Test name
Test status
Simulation time 15110213 ps
CPU time 0.89 seconds
Started Oct 08 01:40:28 PM PDT 23
Finished Oct 08 01:40:29 PM PDT 23
Peak memory 205596 kb
Host smart-2b54dac1-3d73-434e-8b72-f3776d8d0cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080406127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3080406127
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.635420550
Short name T382
Test name
Test status
Simulation time 194178098 ps
CPU time 1.38 seconds
Started Oct 08 01:54:43 PM PDT 23
Finished Oct 08 01:54:45 PM PDT 23
Peak memory 205812 kb
Host smart-dd016eec-1677-4980-bf25-8f3ba8d6b017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635420550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.635420550
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1378056153
Short name T381
Test name
Test status
Simulation time 437569167 ps
CPU time 4.2 seconds
Started Oct 08 01:47:58 PM PDT 23
Finished Oct 08 01:48:02 PM PDT 23
Peak memory 213976 kb
Host smart-91935968-6c70-4b5d-8e25-9579ba8526b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378056153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1378056153
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.335599306
Short name T257
Test name
Test status
Simulation time 130423000 ps
CPU time 1.37 seconds
Started Oct 08 01:55:01 PM PDT 23
Finished Oct 08 01:55:02 PM PDT 23
Peak memory 205788 kb
Host smart-ad06f736-c676-44f1-98cc-d11539ea0709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335599306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.335599306
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.261958878
Short name T414
Test name
Test status
Simulation time 29233206 ps
CPU time 1.43 seconds
Started Oct 08 01:41:10 PM PDT 23
Finished Oct 08 01:41:11 PM PDT 23
Peak memory 213944 kb
Host smart-c573e767-4501-427a-af8b-ecadc9a04cc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261958878 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.261958878
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1528904778
Short name T211
Test name
Test status
Simulation time 12966667 ps
CPU time 0.88 seconds
Started Oct 08 01:43:30 PM PDT 23
Finished Oct 08 01:43:31 PM PDT 23
Peak memory 205708 kb
Host smart-d8f6a2a3-3caa-400a-98da-788f5c6f3d82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528904778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1528904778
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4078928702
Short name T442
Test name
Test status
Simulation time 21170506 ps
CPU time 0.83 seconds
Started Oct 08 01:45:07 PM PDT 23
Finished Oct 08 01:45:08 PM PDT 23
Peak memory 205668 kb
Host smart-260f1115-3898-43f4-9d83-e03862b97d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078928702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4078928702
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3305993955
Short name T441
Test name
Test status
Simulation time 27593322 ps
CPU time 0.99 seconds
Started Oct 08 01:49:04 PM PDT 23
Finished Oct 08 01:49:05 PM PDT 23
Peak memory 205784 kb
Host smart-dd6a88c9-6a1f-46f7-bd51-c5eff404cc68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305993955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3305993955
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3095077333
Short name T408
Test name
Test status
Simulation time 23660760 ps
CPU time 1.61 seconds
Started Oct 08 01:42:51 PM PDT 23
Finished Oct 08 01:42:53 PM PDT 23
Peak memory 213900 kb
Host smart-01ade7e3-763e-47e6-ad43-a2a19f5a64ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095077333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3095077333
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3832631467
Short name T438
Test name
Test status
Simulation time 81549673 ps
CPU time 1.14 seconds
Started Oct 08 01:41:44 PM PDT 23
Finished Oct 08 01:41:47 PM PDT 23
Peak memory 212640 kb
Host smart-b7a8f9f0-f3ae-49c2-84d1-12ff23bdca3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832631467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3832631467
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1311274249
Short name T218
Test name
Test status
Simulation time 85120741 ps
CPU time 0.89 seconds
Started Oct 08 01:41:43 PM PDT 23
Finished Oct 08 01:41:46 PM PDT 23
Peak memory 204204 kb
Host smart-89ba5ec9-cdde-4a51-82d5-add9f4b7a313
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311274249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1311274249
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2304973043
Short name T420
Test name
Test status
Simulation time 16427887 ps
CPU time 0.9 seconds
Started Oct 08 01:49:04 PM PDT 23
Finished Oct 08 01:49:05 PM PDT 23
Peak memory 205640 kb
Host smart-e94447af-1a0d-4026-ab59-02e70c4095cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304973043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2304973043
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2630557972
Short name T231
Test name
Test status
Simulation time 102106788 ps
CPU time 1.34 seconds
Started Oct 08 01:41:42 PM PDT 23
Finished Oct 08 01:41:47 PM PDT 23
Peak memory 203932 kb
Host smart-50c51ec8-597b-4f15-88ce-5d4a57046232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630557972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2630557972
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1827170151
Short name T390
Test name
Test status
Simulation time 53780583 ps
CPU time 2.21 seconds
Started Oct 08 01:50:21 PM PDT 23
Finished Oct 08 01:50:23 PM PDT 23
Peak memory 213932 kb
Host smart-c429cf23-aaaa-4cef-8a0a-729cd3e0727b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827170151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1827170151
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1550088135
Short name T271
Test name
Test status
Simulation time 81518744 ps
CPU time 2.22 seconds
Started Oct 08 01:39:54 PM PDT 23
Finished Oct 08 01:39:57 PM PDT 23
Peak memory 205732 kb
Host smart-f1900e13-b8c1-4da2-a2d6-ae2676b08347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550088135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1550088135
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1753183761
Short name T364
Test name
Test status
Simulation time 18037759 ps
CPU time 1.01 seconds
Started Oct 08 01:45:05 PM PDT 23
Finished Oct 08 01:45:07 PM PDT 23
Peak memory 213996 kb
Host smart-571b4de0-c9c4-4ad2-8294-599433354867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753183761 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1753183761
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.380445888
Short name T219
Test name
Test status
Simulation time 24091721 ps
CPU time 0.89 seconds
Started Oct 08 01:44:26 PM PDT 23
Finished Oct 08 01:44:27 PM PDT 23
Peak memory 205752 kb
Host smart-86ce3308-1762-43cf-af2e-f55349c71644
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380445888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.380445888
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3155838649
Short name T335
Test name
Test status
Simulation time 14971155 ps
CPU time 0.87 seconds
Started Oct 08 01:41:15 PM PDT 23
Finished Oct 08 01:41:16 PM PDT 23
Peak memory 205596 kb
Host smart-a7e39d54-20b2-4b89-ae83-c395c0139a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155838649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3155838649
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2370656942
Short name T424
Test name
Test status
Simulation time 22616521 ps
CPU time 1.09 seconds
Started Oct 08 01:48:59 PM PDT 23
Finished Oct 08 01:49:01 PM PDT 23
Peak memory 205796 kb
Host smart-926aa3ff-8101-4484-aa14-95cb8e695993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370656942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2370656942
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1497539072
Short name T385
Test name
Test status
Simulation time 145033241 ps
CPU time 4.37 seconds
Started Oct 08 01:42:00 PM PDT 23
Finished Oct 08 01:42:06 PM PDT 23
Peak memory 213880 kb
Host smart-bcc3c4c2-1068-48e4-a631-171dcc62f6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497539072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1497539072
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1469145733
Short name T428
Test name
Test status
Simulation time 127984106 ps
CPU time 2.71 seconds
Started Oct 08 01:41:43 PM PDT 23
Finished Oct 08 01:41:48 PM PDT 23
Peak memory 204436 kb
Host smart-d112978b-493d-467c-9963-ee8e83c77551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469145733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1469145733
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2507525004
Short name T333
Test name
Test status
Simulation time 113832862 ps
CPU time 1.97 seconds
Started Oct 08 01:39:17 PM PDT 23
Finished Oct 08 01:39:19 PM PDT 23
Peak memory 214000 kb
Host smart-17441c0f-bc16-441e-8309-13af93e5594a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507525004 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2507525004
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2241018998
Short name T221
Test name
Test status
Simulation time 39036543 ps
CPU time 0.8 seconds
Started Oct 08 01:43:50 PM PDT 23
Finished Oct 08 01:43:51 PM PDT 23
Peak memory 205648 kb
Host smart-79e21313-35b0-4169-836e-3a95d97b234a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241018998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2241018998
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.173431821
Short name T353
Test name
Test status
Simulation time 13861113 ps
CPU time 0.89 seconds
Started Oct 08 01:44:10 PM PDT 23
Finished Oct 08 01:44:12 PM PDT 23
Peak memory 205548 kb
Host smart-593c111d-ac82-4871-b283-6c31cbba6451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173431821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.173431821
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3512926130
Short name T365
Test name
Test status
Simulation time 113746475 ps
CPU time 1.29 seconds
Started Oct 08 01:43:00 PM PDT 23
Finished Oct 08 01:43:01 PM PDT 23
Peak memory 205660 kb
Host smart-daf80104-21ee-4ec5-a9a0-4138adce4ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512926130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3512926130
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1912899778
Short name T341
Test name
Test status
Simulation time 155553837 ps
CPU time 2.02 seconds
Started Oct 08 01:43:43 PM PDT 23
Finished Oct 08 01:43:45 PM PDT 23
Peak memory 214040 kb
Host smart-7e4be4c5-7e47-46bd-9ead-67c52e39b061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912899778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1912899778
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1155141052
Short name T444
Test name
Test status
Simulation time 72142939 ps
CPU time 1.49 seconds
Started Oct 08 01:42:53 PM PDT 23
Finished Oct 08 01:42:55 PM PDT 23
Peak memory 205684 kb
Host smart-6c8b16ca-edc0-4d27-84d8-f1cc397fa7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155141052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1155141052
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1261925394
Short name T422
Test name
Test status
Simulation time 293531647 ps
CPU time 1.26 seconds
Started Oct 08 01:46:42 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 213860 kb
Host smart-7cfc1141-a8ef-41fa-b0e0-c1aa8e12accf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261925394 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1261925394
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3806408294
Short name T391
Test name
Test status
Simulation time 21197621 ps
CPU time 0.9 seconds
Started Oct 08 01:43:31 PM PDT 23
Finished Oct 08 01:43:32 PM PDT 23
Peak memory 205648 kb
Host smart-6aeea2ab-f7ab-4130-a653-57266ae292a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806408294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3806408294
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.38359231
Short name T214
Test name
Test status
Simulation time 16609184 ps
CPU time 0.89 seconds
Started Oct 08 01:41:16 PM PDT 23
Finished Oct 08 01:41:17 PM PDT 23
Peak memory 205592 kb
Host smart-9d311ba5-372f-41cd-b1f2-bd6e5d7073b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38359231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.38359231
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1817778553
Short name T449
Test name
Test status
Simulation time 28151731 ps
CPU time 1.11 seconds
Started Oct 08 01:41:54 PM PDT 23
Finished Oct 08 01:41:56 PM PDT 23
Peak memory 203624 kb
Host smart-4ba838f7-e2ea-4a6c-b16c-97289371fe9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817778553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1817778553
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.148335223
Short name T451
Test name
Test status
Simulation time 493074189 ps
CPU time 2.84 seconds
Started Oct 08 01:47:15 PM PDT 23
Finished Oct 08 01:47:18 PM PDT 23
Peak memory 213976 kb
Host smart-bdddd346-0673-4325-8b3d-83acffbeb32b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148335223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.148335223
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4268987669
Short name T359
Test name
Test status
Simulation time 504117576 ps
CPU time 1.44 seconds
Started Oct 08 01:49:00 PM PDT 23
Finished Oct 08 01:49:02 PM PDT 23
Peak memory 205876 kb
Host smart-3c123a61-927b-4679-8a3b-4df81896eac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268987669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4268987669
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2757801990
Short name T379
Test name
Test status
Simulation time 50254203 ps
CPU time 1.27 seconds
Started Oct 08 01:40:28 PM PDT 23
Finished Oct 08 01:40:30 PM PDT 23
Peak memory 213928 kb
Host smart-7a1c1a5c-0025-4676-bf93-ddfa67da7058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757801990 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2757801990
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.334643597
Short name T439
Test name
Test status
Simulation time 26378597 ps
CPU time 0.84 seconds
Started Oct 08 01:39:21 PM PDT 23
Finished Oct 08 01:39:22 PM PDT 23
Peak memory 205604 kb
Host smart-ff4efbe5-7652-4fd9-b30d-c814394d21b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334643597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.334643597
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4179814513
Short name T427
Test name
Test status
Simulation time 11802625 ps
CPU time 0.83 seconds
Started Oct 08 01:41:59 PM PDT 23
Finished Oct 08 01:42:00 PM PDT 23
Peak memory 205620 kb
Host smart-7b62b9ec-c01f-4e25-8758-fbbf07bf61d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179814513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4179814513
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1261005924
Short name T435
Test name
Test status
Simulation time 593144649 ps
CPU time 1.55 seconds
Started Oct 08 01:41:54 PM PDT 23
Finished Oct 08 01:41:56 PM PDT 23
Peak memory 203408 kb
Host smart-6607eb19-6b37-4758-abfa-1e4340cfc93a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261005924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1261005924
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.909020698
Short name T342
Test name
Test status
Simulation time 91785310 ps
CPU time 3.19 seconds
Started Oct 08 01:41:54 PM PDT 23
Finished Oct 08 01:41:58 PM PDT 23
Peak memory 211556 kb
Host smart-7e6c5b95-90d8-490a-8ca3-f5d2f8a3c43e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909020698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.909020698
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.865773568
Short name T398
Test name
Test status
Simulation time 405146084 ps
CPU time 1.4 seconds
Started Oct 08 01:43:58 PM PDT 23
Finished Oct 08 01:43:59 PM PDT 23
Peak memory 205676 kb
Host smart-9b46e42d-88ce-48a5-93e6-9a5894ae5a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865773568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.865773568
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2150826869
Short name T401
Test name
Test status
Simulation time 25001844 ps
CPU time 1.25 seconds
Started Oct 08 01:45:48 PM PDT 23
Finished Oct 08 01:45:50 PM PDT 23
Peak memory 216588 kb
Host smart-4003e1d6-27ef-4dd4-bc50-29e6caeb4f27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150826869 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2150826869
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2359344362
Short name T453
Test name
Test status
Simulation time 13509873 ps
CPU time 0.86 seconds
Started Oct 08 01:40:42 PM PDT 23
Finished Oct 08 01:40:43 PM PDT 23
Peak memory 205576 kb
Host smart-2650ef9b-c08c-423b-b698-8456f514ec49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359344362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2359344362
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4181867180
Short name T374
Test name
Test status
Simulation time 18494193 ps
CPU time 0.8 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 205728 kb
Host smart-4fedb182-5b0e-4926-a98b-2e55d4b9f8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181867180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4181867180
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.429291191
Short name T230
Test name
Test status
Simulation time 20997170 ps
CPU time 1.18 seconds
Started Oct 08 01:40:21 PM PDT 23
Finished Oct 08 01:40:23 PM PDT 23
Peak memory 205864 kb
Host smart-2b3b6910-ca30-4577-adb1-26cc5d00f8ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429291191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.429291191
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2201321466
Short name T411
Test name
Test status
Simulation time 197616605 ps
CPU time 2.04 seconds
Started Oct 08 01:40:39 PM PDT 23
Finished Oct 08 01:40:41 PM PDT 23
Peak memory 214016 kb
Host smart-36b64361-1251-4473-80c8-b47f4ebcd1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201321466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2201321466
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3799272650
Short name T256
Test name
Test status
Simulation time 158446015 ps
CPU time 1.4 seconds
Started Oct 08 01:39:27 PM PDT 23
Finished Oct 08 01:39:28 PM PDT 23
Peak memory 205704 kb
Host smart-8cbb92f2-c4a2-43bf-850f-eb445bcfa7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799272650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3799272650
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1189233927
Short name T146
Test name
Test status
Simulation time 51103188 ps
CPU time 1.42 seconds
Started Oct 08 01:39:56 PM PDT 23
Finished Oct 08 01:39:58 PM PDT 23
Peak memory 205712 kb
Host smart-9c3398ea-b19e-4fd0-90d4-61d9dc3199e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189233927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1189233927
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2375856303
Short name T225
Test name
Test status
Simulation time 104710902 ps
CPU time 1.93 seconds
Started Oct 08 01:40:51 PM PDT 23
Finished Oct 08 01:40:53 PM PDT 23
Peak memory 205676 kb
Host smart-e69ddefc-fd8f-47e0-a6d5-e26d1ce02940
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375856303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2375856303
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1187972156
Short name T339
Test name
Test status
Simulation time 13347153 ps
CPU time 0.9 seconds
Started Oct 08 01:41:42 PM PDT 23
Finished Oct 08 01:41:46 PM PDT 23
Peak memory 205848 kb
Host smart-a44acaae-71fe-4468-8e95-cf9d64d02760
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187972156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1187972156
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2574670711
Short name T370
Test name
Test status
Simulation time 55444325 ps
CPU time 1 seconds
Started Oct 08 01:40:29 PM PDT 23
Finished Oct 08 01:40:30 PM PDT 23
Peak memory 205708 kb
Host smart-f4603b74-17af-4604-8499-cf6134865851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574670711 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2574670711
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1705724455
Short name T228
Test name
Test status
Simulation time 12649947 ps
CPU time 0.86 seconds
Started Oct 08 01:42:50 PM PDT 23
Finished Oct 08 01:42:51 PM PDT 23
Peak memory 205604 kb
Host smart-d6f44f33-9fad-40c0-a9fd-c5cfb923600e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705724455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1705724455
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1878827198
Short name T450
Test name
Test status
Simulation time 17556650 ps
CPU time 0.99 seconds
Started Oct 08 01:39:55 PM PDT 23
Finished Oct 08 01:39:56 PM PDT 23
Peak memory 205696 kb
Host smart-1a63e4ba-5836-44b7-99f9-5e3f23114733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878827198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1878827198
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2069407126
Short name T421
Test name
Test status
Simulation time 425716952 ps
CPU time 1.62 seconds
Started Oct 08 01:39:57 PM PDT 23
Finished Oct 08 01:39:59 PM PDT 23
Peak memory 205796 kb
Host smart-d8f85e1b-8cd8-4b43-a7ad-380d9c83b9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069407126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2069407126
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2501534067
Short name T389
Test name
Test status
Simulation time 172836808 ps
CPU time 3.02 seconds
Started Oct 08 01:39:07 PM PDT 23
Finished Oct 08 01:39:11 PM PDT 23
Peak memory 213924 kb
Host smart-ff359df9-ec3b-4a02-b410-a4470172ab19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501534067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2501534067
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4000811394
Short name T357
Test name
Test status
Simulation time 52393356 ps
CPU time 1.71 seconds
Started Oct 08 01:47:03 PM PDT 23
Finished Oct 08 01:47:05 PM PDT 23
Peak memory 205848 kb
Host smart-82ecfb18-87b8-4ff6-99ba-e63bc83b91cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000811394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4000811394
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2940810078
Short name T346
Test name
Test status
Simulation time 76026066 ps
CPU time 0.83 seconds
Started Oct 08 01:40:40 PM PDT 23
Finished Oct 08 01:40:41 PM PDT 23
Peak memory 205672 kb
Host smart-66b9d594-df7e-481f-a1d7-67e729cf3154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940810078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2940810078
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4222830104
Short name T392
Test name
Test status
Simulation time 32984991 ps
CPU time 0.84 seconds
Started Oct 08 01:45:48 PM PDT 23
Finished Oct 08 01:45:49 PM PDT 23
Peak memory 205544 kb
Host smart-ae7fb702-e9da-4752-b48f-edf736accd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222830104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4222830104
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3056906461
Short name T384
Test name
Test status
Simulation time 13290487 ps
CPU time 0.85 seconds
Started Oct 08 01:43:56 PM PDT 23
Finished Oct 08 01:43:57 PM PDT 23
Peak memory 205540 kb
Host smart-4d6a14d0-640a-42ff-ad07-ddf3f452a561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056906461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3056906461
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1248165658
Short name T430
Test name
Test status
Simulation time 42673483 ps
CPU time 0.75 seconds
Started Oct 08 01:40:22 PM PDT 23
Finished Oct 08 01:40:23 PM PDT 23
Peak memory 205376 kb
Host smart-a310f96e-1d0d-4e4c-820c-8df9ebb28cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248165658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1248165658
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2048830297
Short name T355
Test name
Test status
Simulation time 35392861 ps
CPU time 0.78 seconds
Started Oct 08 01:44:01 PM PDT 23
Finished Oct 08 01:44:02 PM PDT 23
Peak memory 205468 kb
Host smart-19e710eb-51c5-478e-aae9-4dbcb29b6e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048830297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2048830297
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3184326662
Short name T448
Test name
Test status
Simulation time 55851120 ps
CPU time 0.86 seconds
Started Oct 08 01:39:37 PM PDT 23
Finished Oct 08 01:39:38 PM PDT 23
Peak memory 205508 kb
Host smart-f3ce8afe-7f90-45ea-b204-ae0f848dc07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184326662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3184326662
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2890070087
Short name T436
Test name
Test status
Simulation time 16161548 ps
CPU time 0.86 seconds
Started Oct 08 01:52:34 PM PDT 23
Finished Oct 08 01:52:35 PM PDT 23
Peak memory 205660 kb
Host smart-74f21e74-bb1e-43de-85d4-5303f63f72f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890070087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2890070087
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1711005925
Short name T418
Test name
Test status
Simulation time 22751534 ps
CPU time 0.83 seconds
Started Oct 08 01:41:30 PM PDT 23
Finished Oct 08 01:41:31 PM PDT 23
Peak memory 205584 kb
Host smart-5f38222a-9268-4b4a-ad75-53a289c8d58a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711005925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1711005925
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2423649730
Short name T406
Test name
Test status
Simulation time 16155308 ps
CPU time 0.92 seconds
Started Oct 08 01:42:58 PM PDT 23
Finished Oct 08 01:43:00 PM PDT 23
Peak memory 205480 kb
Host smart-8efa3743-98aa-4612-98e6-3bd8760fc39b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423649730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2423649730
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4014872671
Short name T443
Test name
Test status
Simulation time 12008559 ps
CPU time 0.95 seconds
Started Oct 08 01:42:32 PM PDT 23
Finished Oct 08 01:42:33 PM PDT 23
Peak memory 205668 kb
Host smart-1a83e3e5-0fd9-4190-801b-b95a0d7ef984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014872671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4014872671
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.508121793
Short name T413
Test name
Test status
Simulation time 184958696 ps
CPU time 1.4 seconds
Started Oct 08 01:47:31 PM PDT 23
Finished Oct 08 01:47:32 PM PDT 23
Peak memory 205816 kb
Host smart-f3e0b30b-b1d2-4ceb-89f6-a2a86a06b331
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508121793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.508121793
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3231999550
Short name T222
Test name
Test status
Simulation time 64673637 ps
CPU time 2.03 seconds
Started Oct 08 01:44:07 PM PDT 23
Finished Oct 08 01:44:09 PM PDT 23
Peak memory 205904 kb
Host smart-8ca43d4c-65f5-4493-8310-3fd35522a6af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231999550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3231999550
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2586893100
Short name T215
Test name
Test status
Simulation time 28305240 ps
CPU time 0.81 seconds
Started Oct 08 01:40:34 PM PDT 23
Finished Oct 08 01:40:35 PM PDT 23
Peak memory 205560 kb
Host smart-f4ccbc1c-da9d-471f-9a3d-fbf40d426933
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586893100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2586893100
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1830166636
Short name T440
Test name
Test status
Simulation time 156596755 ps
CPU time 1.44 seconds
Started Oct 08 01:39:38 PM PDT 23
Finished Oct 08 01:39:40 PM PDT 23
Peak memory 214060 kb
Host smart-da4f2efc-ffd7-4242-9507-46760080bbdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830166636 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1830166636
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1763685712
Short name T380
Test name
Test status
Simulation time 24976067 ps
CPU time 0.92 seconds
Started Oct 08 01:40:22 PM PDT 23
Finished Oct 08 01:40:23 PM PDT 23
Peak memory 205776 kb
Host smart-45dff9ca-652a-4e51-919b-7def0153aa7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763685712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1763685712
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.706082840
Short name T344
Test name
Test status
Simulation time 16638740 ps
CPU time 0.75 seconds
Started Oct 08 01:40:19 PM PDT 23
Finished Oct 08 01:40:20 PM PDT 23
Peak memory 205392 kb
Host smart-e2db1adb-95f2-4782-8ae3-a2cb29327ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706082840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.706082840
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2291630087
Short name T394
Test name
Test status
Simulation time 67239140 ps
CPU time 1.02 seconds
Started Oct 08 01:38:40 PM PDT 23
Finished Oct 08 01:38:42 PM PDT 23
Peak memory 205644 kb
Host smart-e2ed5737-c56f-4e36-b53c-becbe54fce14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291630087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2291630087
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1960538666
Short name T393
Test name
Test status
Simulation time 31804569 ps
CPU time 2.01 seconds
Started Oct 08 01:44:07 PM PDT 23
Finished Oct 08 01:44:09 PM PDT 23
Peak memory 214120 kb
Host smart-60494a24-a486-4753-9acc-e7b34603a836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960538666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1960538666
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4207109550
Short name T154
Test name
Test status
Simulation time 311901892 ps
CPU time 2.48 seconds
Started Oct 08 01:44:05 PM PDT 23
Finished Oct 08 01:44:08 PM PDT 23
Peak memory 205696 kb
Host smart-6787ac21-b910-41b2-a55b-8be65cd83721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207109550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4207109550
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.81901626
Short name T354
Test name
Test status
Simulation time 15757387 ps
CPU time 0.88 seconds
Started Oct 08 01:47:07 PM PDT 23
Finished Oct 08 01:47:08 PM PDT 23
Peak memory 205580 kb
Host smart-cc442f37-f0a5-45fb-958b-9d14bc897705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81901626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.81901626
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2206606868
Short name T366
Test name
Test status
Simulation time 43075980 ps
CPU time 0.89 seconds
Started Oct 08 01:47:07 PM PDT 23
Finished Oct 08 01:47:08 PM PDT 23
Peak memory 205684 kb
Host smart-1c79fcdb-e637-45fb-9c8a-5c8209af5a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206606868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2206606868
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2130402233
Short name T216
Test name
Test status
Simulation time 48035918 ps
CPU time 0.74 seconds
Started Oct 08 01:51:42 PM PDT 23
Finished Oct 08 01:51:43 PM PDT 23
Peak memory 205640 kb
Host smart-8d2786d2-2ed4-4b16-9255-03014052761b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130402233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2130402233
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2474412288
Short name T350
Test name
Test status
Simulation time 15231449 ps
CPU time 0.86 seconds
Started Oct 08 01:51:42 PM PDT 23
Finished Oct 08 01:51:43 PM PDT 23
Peak memory 205636 kb
Host smart-f477377a-a444-425d-970a-1244db30b516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474412288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2474412288
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.250843193
Short name T407
Test name
Test status
Simulation time 25721920 ps
CPU time 0.85 seconds
Started Oct 08 01:47:12 PM PDT 23
Finished Oct 08 01:47:14 PM PDT 23
Peak memory 205728 kb
Host smart-0aed06b8-fa7e-4c32-946c-4062c0a48ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250843193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.250843193
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.10818066
Short name T351
Test name
Test status
Simulation time 16975967 ps
CPU time 0.81 seconds
Started Oct 08 01:40:33 PM PDT 23
Finished Oct 08 01:40:34 PM PDT 23
Peak memory 205480 kb
Host smart-bfdcf00e-a115-460e-830c-5a1a7dd0ed90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.10818066
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.818397673
Short name T330
Test name
Test status
Simulation time 12751811 ps
CPU time 0.8 seconds
Started Oct 08 01:44:08 PM PDT 23
Finished Oct 08 01:44:09 PM PDT 23
Peak memory 205560 kb
Host smart-24527281-a685-4bf9-b0a1-e5d915ec7b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818397673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.818397673
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1364427436
Short name T397
Test name
Test status
Simulation time 25436848 ps
CPU time 0.84 seconds
Started Oct 08 01:39:42 PM PDT 23
Finished Oct 08 01:39:43 PM PDT 23
Peak memory 205664 kb
Host smart-f2774083-a009-426e-bf03-c7159d237a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364427436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1364427436
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2597135189
Short name T400
Test name
Test status
Simulation time 12205651 ps
CPU time 0.88 seconds
Started Oct 08 01:41:15 PM PDT 23
Finished Oct 08 01:41:16 PM PDT 23
Peak memory 205732 kb
Host smart-266779f2-1be0-48c1-aadb-697eda1edef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597135189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2597135189
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1567146586
Short name T375
Test name
Test status
Simulation time 12798583 ps
CPU time 0.88 seconds
Started Oct 08 01:39:44 PM PDT 23
Finished Oct 08 01:39:45 PM PDT 23
Peak memory 205564 kb
Host smart-e6de527b-ffa1-4871-af58-df481c2e3dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567146586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1567146586
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.951570380
Short name T226
Test name
Test status
Simulation time 19709939 ps
CPU time 1.26 seconds
Started Oct 08 01:41:54 PM PDT 23
Finished Oct 08 01:41:56 PM PDT 23
Peak memory 203536 kb
Host smart-a1b37e6f-62f8-49af-b1f8-6a114f554f40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951570380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.951570380
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1269728171
Short name T387
Test name
Test status
Simulation time 200272268 ps
CPU time 3.7 seconds
Started Oct 08 01:38:56 PM PDT 23
Finished Oct 08 01:39:00 PM PDT 23
Peak memory 205616 kb
Host smart-0ada412d-e68e-4100-980d-e728c27f1ff0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269728171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1269728171
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3002206532
Short name T149
Test name
Test status
Simulation time 54394953 ps
CPU time 0.83 seconds
Started Oct 08 01:41:50 PM PDT 23
Finished Oct 08 01:41:51 PM PDT 23
Peak memory 205484 kb
Host smart-68ec72f9-f416-40c9-9864-fc8dba2acb26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002206532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3002206532
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1546854888
Short name T431
Test name
Test status
Simulation time 68983591 ps
CPU time 1.21 seconds
Started Oct 08 01:39:55 PM PDT 23
Finished Oct 08 01:39:56 PM PDT 23
Peak memory 214000 kb
Host smart-1830bc09-5b48-4b9c-a54a-f0d040031368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546854888 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1546854888
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.718815356
Short name T396
Test name
Test status
Simulation time 121750367 ps
CPU time 0.85 seconds
Started Oct 08 01:38:43 PM PDT 23
Finished Oct 08 01:38:44 PM PDT 23
Peak memory 205576 kb
Host smart-3beb517a-2b24-4d76-b821-f0975268d0ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718815356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.718815356
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1514638392
Short name T446
Test name
Test status
Simulation time 12609613 ps
CPU time 0.89 seconds
Started Oct 08 01:40:00 PM PDT 23
Finished Oct 08 01:40:02 PM PDT 23
Peak memory 205512 kb
Host smart-8e4a30af-cbc0-4c89-84cc-8ce7e8f49406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514638392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1514638392
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.144393109
Short name T145
Test name
Test status
Simulation time 58353798 ps
CPU time 1.44 seconds
Started Oct 08 01:40:33 PM PDT 23
Finished Oct 08 01:40:35 PM PDT 23
Peak memory 205728 kb
Host smart-8013bdbb-8519-4e50-9f0f-12057352b132
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144393109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.144393109
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1621134688
Short name T402
Test name
Test status
Simulation time 169990962 ps
CPU time 2.43 seconds
Started Oct 08 01:39:26 PM PDT 23
Finished Oct 08 01:39:29 PM PDT 23
Peak memory 214080 kb
Host smart-f7ce1751-a4fb-4700-9ba9-4be24e5bc9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621134688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1621134688
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1901659712
Short name T405
Test name
Test status
Simulation time 123131976 ps
CPU time 1.45 seconds
Started Oct 08 01:52:38 PM PDT 23
Finished Oct 08 01:52:40 PM PDT 23
Peak memory 205844 kb
Host smart-03ffd4ed-9089-4cc9-a14f-6d2c7561e40a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901659712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1901659712
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1926381517
Short name T356
Test name
Test status
Simulation time 25264247 ps
CPU time 0.82 seconds
Started Oct 08 01:42:57 PM PDT 23
Finished Oct 08 01:42:58 PM PDT 23
Peak memory 205624 kb
Host smart-2a96ed72-1300-4ddc-863e-50bcf8c5c5e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926381517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1926381517
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2265029079
Short name T368
Test name
Test status
Simulation time 25025215 ps
CPU time 0.82 seconds
Started Oct 08 01:41:18 PM PDT 23
Finished Oct 08 01:41:19 PM PDT 23
Peak memory 205516 kb
Host smart-c57c021c-0e67-41cb-9275-50bcfed04f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265029079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2265029079
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1631765543
Short name T371
Test name
Test status
Simulation time 22992502 ps
CPU time 0.9 seconds
Started Oct 08 01:39:40 PM PDT 23
Finished Oct 08 01:39:41 PM PDT 23
Peak memory 205484 kb
Host smart-3885ec80-174c-48ca-a09b-1bfe011de360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631765543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1631765543
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2890797075
Short name T352
Test name
Test status
Simulation time 23822484 ps
CPU time 0.86 seconds
Started Oct 08 01:51:30 PM PDT 23
Finished Oct 08 01:51:31 PM PDT 23
Peak memory 205636 kb
Host smart-ebc84b7d-378f-4a0c-ad7f-332d8b930609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890797075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2890797075
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4117501949
Short name T369
Test name
Test status
Simulation time 13221918 ps
CPU time 0.87 seconds
Started Oct 08 01:43:58 PM PDT 23
Finished Oct 08 01:43:59 PM PDT 23
Peak memory 205668 kb
Host smart-3748b13f-901b-4eeb-8518-2f431d206b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117501949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4117501949
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2928788175
Short name T378
Test name
Test status
Simulation time 42676543 ps
CPU time 0.86 seconds
Started Oct 08 01:44:42 PM PDT 23
Finished Oct 08 01:44:43 PM PDT 23
Peak memory 205496 kb
Host smart-8208bcb1-d4cc-46bf-af33-ccd4abd06391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928788175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2928788175
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1467368509
Short name T433
Test name
Test status
Simulation time 66646627 ps
CPU time 0.8 seconds
Started Oct 08 01:43:12 PM PDT 23
Finished Oct 08 01:43:13 PM PDT 23
Peak memory 205528 kb
Host smart-fbd31855-74bc-451b-91f4-da23be2f8328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467368509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1467368509
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3825039469
Short name T395
Test name
Test status
Simulation time 12699688 ps
CPU time 0.84 seconds
Started Oct 08 01:55:36 PM PDT 23
Finished Oct 08 01:55:37 PM PDT 23
Peak memory 205732 kb
Host smart-d7c0656e-08a3-47f6-ac19-3df6745d838b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825039469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3825039469
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4050027315
Short name T347
Test name
Test status
Simulation time 40130968 ps
CPU time 0.84 seconds
Started Oct 08 01:41:20 PM PDT 23
Finished Oct 08 01:41:21 PM PDT 23
Peak memory 205620 kb
Host smart-9548646b-cd80-4f07-a696-f325a539af8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050027315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4050027315
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.185584638
Short name T386
Test name
Test status
Simulation time 11816581 ps
CPU time 0.83 seconds
Started Oct 08 01:42:01 PM PDT 23
Finished Oct 08 01:42:02 PM PDT 23
Peak memory 205548 kb
Host smart-522c9b59-1d09-4931-9497-b731e8e957eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185584638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.185584638
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.210653276
Short name T372
Test name
Test status
Simulation time 100419725 ps
CPU time 1.78 seconds
Started Oct 08 01:42:27 PM PDT 23
Finished Oct 08 01:42:30 PM PDT 23
Peak memory 214016 kb
Host smart-4dca1201-3f4a-4166-99be-504046e3c70e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210653276 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.210653276
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4249388995
Short name T161
Test name
Test status
Simulation time 26522622 ps
CPU time 0.94 seconds
Started Oct 08 01:42:18 PM PDT 23
Finished Oct 08 01:42:20 PM PDT 23
Peak memory 205472 kb
Host smart-19a70736-8e6b-438f-95c7-a05f0c1c23c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249388995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4249388995
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2410941877
Short name T332
Test name
Test status
Simulation time 22785432 ps
CPU time 0.75 seconds
Started Oct 08 01:40:58 PM PDT 23
Finished Oct 08 01:40:59 PM PDT 23
Peak memory 205436 kb
Host smart-873c7913-115d-43fb-947d-025cafbb9bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410941877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2410941877
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1840644757
Short name T144
Test name
Test status
Simulation time 99206376 ps
CPU time 1.16 seconds
Started Oct 08 01:50:47 PM PDT 23
Finished Oct 08 01:50:49 PM PDT 23
Peak memory 205856 kb
Host smart-06aca4f7-92d1-4b23-9a57-3dd1c9a695ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840644757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1840644757
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1295703724
Short name T147
Test name
Test status
Simulation time 299330519 ps
CPU time 2.8 seconds
Started Oct 08 01:39:55 PM PDT 23
Finished Oct 08 01:39:58 PM PDT 23
Peak memory 214024 kb
Host smart-412b8426-0812-480a-b1d0-fe18d0b666a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295703724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1295703724
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3109933807
Short name T388
Test name
Test status
Simulation time 83461537 ps
CPU time 1.7 seconds
Started Oct 08 01:39:24 PM PDT 23
Finished Oct 08 01:39:26 PM PDT 23
Peak memory 205820 kb
Host smart-ad946289-e4bf-4cc4-b611-cd0149d6977c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109933807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3109933807
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3151251774
Short name T373
Test name
Test status
Simulation time 19346138 ps
CPU time 1.18 seconds
Started Oct 08 01:49:38 PM PDT 23
Finished Oct 08 01:49:39 PM PDT 23
Peak memory 214156 kb
Host smart-ea6cadfc-67bf-49f4-8697-0a896539cbcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151251774 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3151251774
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.296117222
Short name T415
Test name
Test status
Simulation time 33177124 ps
CPU time 0.86 seconds
Started Oct 08 01:39:44 PM PDT 23
Finished Oct 08 01:39:45 PM PDT 23
Peak memory 205600 kb
Host smart-67966f2e-07f9-41df-b027-43fbda8f0676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296117222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.296117222
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3641339124
Short name T362
Test name
Test status
Simulation time 19490822 ps
CPU time 0.77 seconds
Started Oct 08 01:42:19 PM PDT 23
Finished Oct 08 01:42:20 PM PDT 23
Peak memory 205256 kb
Host smart-7ef694e4-7829-4b0b-87d4-ead8d7479178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641339124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3641339124
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2185607055
Short name T410
Test name
Test status
Simulation time 44243026 ps
CPU time 1.31 seconds
Started Oct 08 01:46:02 PM PDT 23
Finished Oct 08 01:46:03 PM PDT 23
Peak memory 205720 kb
Host smart-5b3fbbbf-1783-43d8-b776-a1727fa0386b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185607055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2185607055
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3805485218
Short name T434
Test name
Test status
Simulation time 144546646 ps
CPU time 4.08 seconds
Started Oct 08 01:42:19 PM PDT 23
Finished Oct 08 01:42:24 PM PDT 23
Peak memory 213824 kb
Host smart-3703b493-4a80-49f2-9389-a27165f7e760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805485218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3805485218
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2624592276
Short name T404
Test name
Test status
Simulation time 49482285 ps
CPU time 1.54 seconds
Started Oct 08 01:42:33 PM PDT 23
Finished Oct 08 01:42:35 PM PDT 23
Peak memory 205648 kb
Host smart-b7dadd62-8110-4d8e-8a56-ca9ee77aebdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624592276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2624592276
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2229082618
Short name T360
Test name
Test status
Simulation time 15342812 ps
CPU time 0.95 seconds
Started Oct 08 01:39:41 PM PDT 23
Finished Oct 08 01:39:42 PM PDT 23
Peak memory 205752 kb
Host smart-2e6e4725-e5f4-486d-a4c7-fce11cdaff96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229082618 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2229082618
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.362770768
Short name T162
Test name
Test status
Simulation time 46594246 ps
CPU time 0.84 seconds
Started Oct 08 01:40:47 PM PDT 23
Finished Oct 08 01:40:49 PM PDT 23
Peak memory 205800 kb
Host smart-63bb3aa3-7027-450b-9f75-6f6283c44b90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362770768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.362770768
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1195327370
Short name T340
Test name
Test status
Simulation time 28040500 ps
CPU time 0.91 seconds
Started Oct 08 01:40:15 PM PDT 23
Finished Oct 08 01:40:16 PM PDT 23
Peak memory 205540 kb
Host smart-8260b4d2-0a09-4cd0-93c6-84b3acaf67dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195327370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1195327370
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1869468504
Short name T417
Test name
Test status
Simulation time 66147831 ps
CPU time 1.08 seconds
Started Oct 08 01:39:47 PM PDT 23
Finished Oct 08 01:39:48 PM PDT 23
Peak memory 205692 kb
Host smart-44ccdac0-9682-4eaf-88e7-f7af74793bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869468504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1869468504
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3547007223
Short name T367
Test name
Test status
Simulation time 73813193 ps
CPU time 2.55 seconds
Started Oct 08 01:44:13 PM PDT 23
Finished Oct 08 01:44:16 PM PDT 23
Peak memory 217168 kb
Host smart-fd958b9e-d942-4fb3-b4e1-7a0b3290c908
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547007223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3547007223
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1095249130
Short name T273
Test name
Test status
Simulation time 334700731 ps
CPU time 2.33 seconds
Started Oct 08 01:41:54 PM PDT 23
Finished Oct 08 01:41:57 PM PDT 23
Peak memory 203708 kb
Host smart-17e41728-293b-4e19-89ec-8acd52dc4de6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095249130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1095249130
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3087286191
Short name T212
Test name
Test status
Simulation time 55561937 ps
CPU time 1.41 seconds
Started Oct 08 01:40:38 PM PDT 23
Finished Oct 08 01:40:40 PM PDT 23
Peak memory 214380 kb
Host smart-c05f3a70-8c85-4d76-a4f0-7f70cbc6f8d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087286191 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3087286191
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.241821859
Short name T229
Test name
Test status
Simulation time 40237017 ps
CPU time 0.85 seconds
Started Oct 08 01:39:36 PM PDT 23
Finished Oct 08 01:39:37 PM PDT 23
Peak memory 205676 kb
Host smart-08ffbf0c-32cf-4945-9b04-62c04a8c1da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241821859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.241821859
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3087693202
Short name T445
Test name
Test status
Simulation time 43516735 ps
CPU time 0.82 seconds
Started Oct 08 01:39:44 PM PDT 23
Finished Oct 08 01:39:45 PM PDT 23
Peak memory 205596 kb
Host smart-c8799935-76af-403b-92d6-889748de2e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087693202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3087693202
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3936142597
Short name T429
Test name
Test status
Simulation time 17859477 ps
CPU time 1.14 seconds
Started Oct 08 01:40:21 PM PDT 23
Finished Oct 08 01:40:23 PM PDT 23
Peak memory 205684 kb
Host smart-a00f26ad-944d-47cf-915f-fc5d79201a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936142597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3936142597
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.688089102
Short name T338
Test name
Test status
Simulation time 27291260 ps
CPU time 1.56 seconds
Started Oct 08 01:44:09 PM PDT 23
Finished Oct 08 01:44:11 PM PDT 23
Peak memory 213940 kb
Host smart-1cc7e934-06e7-43c1-a622-ae7d87b97963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688089102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.688089102
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1809151194
Short name T423
Test name
Test status
Simulation time 156502807 ps
CPU time 1.54 seconds
Started Oct 08 01:40:48 PM PDT 23
Finished Oct 08 01:40:49 PM PDT 23
Peak memory 205660 kb
Host smart-b44f8276-ac2d-445d-a003-cb7d0ab83426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809151194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1809151194
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2685289726
Short name T343
Test name
Test status
Simulation time 18741491 ps
CPU time 0.85 seconds
Started Oct 08 01:49:34 PM PDT 23
Finished Oct 08 01:49:35 PM PDT 23
Peak memory 205808 kb
Host smart-ed9296a0-2ad6-4630-b75d-4ab1dcf3b825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685289726 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2685289726
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.712500899
Short name T377
Test name
Test status
Simulation time 66712469 ps
CPU time 0.8 seconds
Started Oct 08 01:40:41 PM PDT 23
Finished Oct 08 01:40:42 PM PDT 23
Peak memory 205584 kb
Host smart-7efa5d62-e3b6-414f-9417-509b8055995d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712500899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.712500899
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2685716035
Short name T345
Test name
Test status
Simulation time 47822055 ps
CPU time 0.81 seconds
Started Oct 08 01:39:49 PM PDT 23
Finished Oct 08 01:39:50 PM PDT 23
Peak memory 205532 kb
Host smart-0a2f757b-93cc-47fa-9ad3-29e242393e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685716035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2685716035
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1665276362
Short name T412
Test name
Test status
Simulation time 133923324 ps
CPU time 1.27 seconds
Started Oct 08 01:44:29 PM PDT 23
Finished Oct 08 01:44:30 PM PDT 23
Peak memory 205728 kb
Host smart-538ada8d-cb5f-47cb-860d-1c7f4a920dbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665276362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1665276362
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1701131509
Short name T358
Test name
Test status
Simulation time 271068698 ps
CPU time 2.45 seconds
Started Oct 08 01:40:22 PM PDT 23
Finished Oct 08 01:40:25 PM PDT 23
Peak memory 213948 kb
Host smart-ad5af070-a86e-47d3-b5eb-ee2be49b2984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701131509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1701131509
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3493871889
Short name T363
Test name
Test status
Simulation time 176139136 ps
CPU time 1.71 seconds
Started Oct 08 01:49:53 PM PDT 23
Finished Oct 08 01:49:54 PM PDT 23
Peak memory 205744 kb
Host smart-c2f1e48a-8037-4c72-b77c-1817538b4e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493871889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3493871889
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3416347240
Short name T2
Test name
Test status
Simulation time 34811607 ps
CPU time 0.95 seconds
Started Oct 08 12:43:39 PM PDT 23
Finished Oct 08 12:43:40 PM PDT 23
Peak memory 205376 kb
Host smart-43d0db20-3430-43b5-9906-8ff3d6af5e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416347240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3416347240
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_err.975767624
Short name T107
Test name
Test status
Simulation time 66204467 ps
CPU time 1.06 seconds
Started Oct 08 12:41:05 PM PDT 23
Finished Oct 08 12:41:07 PM PDT 23
Peak memory 220028 kb
Host smart-44555a25-9b0e-479c-8768-363c8fc6674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975767624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.975767624
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1513018727
Short name T547
Test name
Test status
Simulation time 37361598 ps
CPU time 0.83 seconds
Started Oct 08 12:42:27 PM PDT 23
Finished Oct 08 12:42:29 PM PDT 23
Peak memory 214276 kb
Host smart-0182f345-8bc9-4d32-8f49-3de42c789c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513018727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1513018727
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3257522245
Short name T288
Test name
Test status
Simulation time 16335533 ps
CPU time 0.86 seconds
Started Oct 08 02:19:14 PM PDT 23
Finished Oct 08 02:19:15 PM PDT 23
Peak memory 204824 kb
Host smart-8dc38050-795d-446d-9435-7a0e40b9cd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257522245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3257522245
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3201797856
Short name T524
Test name
Test status
Simulation time 37761130 ps
CPU time 0.81 seconds
Started Oct 08 01:37:29 PM PDT 23
Finished Oct 08 01:37:30 PM PDT 23
Peak memory 204440 kb
Host smart-eb61e8e4-e6c1-4381-a384-5e08f10c11ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201797856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3201797856
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4216149104
Short name T506
Test name
Test status
Simulation time 148099268 ps
CPU time 3.32 seconds
Started Oct 08 12:51:08 PM PDT 23
Finished Oct 08 12:51:12 PM PDT 23
Peak memory 205856 kb
Host smart-cae17390-7f42-418c-b85b-bbd400a3732a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216149104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4216149104
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1396654109
Short name T509
Test name
Test status
Simulation time 18027299 ps
CPU time 0.94 seconds
Started Oct 08 01:42:01 PM PDT 23
Finished Oct 08 01:42:03 PM PDT 23
Peak memory 205052 kb
Host smart-d987561f-6bf4-44c9-afbc-dd2ca0b0c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396654109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1396654109
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3378620843
Short name T561
Test name
Test status
Simulation time 15177117 ps
CPU time 0.88 seconds
Started Oct 08 01:44:05 PM PDT 23
Finished Oct 08 01:44:06 PM PDT 23
Peak memory 204664 kb
Host smart-c9fc0a27-de69-47a5-89d2-acd0ceb323f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378620843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3378620843
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.792476250
Short name T119
Test name
Test status
Simulation time 16330615 ps
CPU time 0.82 seconds
Started Oct 08 01:46:42 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 214360 kb
Host smart-b971aec3-dc5c-41bb-aedc-f722b7e2463c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792476250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.792476250
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3393961187
Short name T482
Test name
Test status
Simulation time 30184597 ps
CPU time 0.92 seconds
Started Oct 08 01:44:08 PM PDT 23
Finished Oct 08 01:44:09 PM PDT 23
Peak memory 214588 kb
Host smart-5d8cb3c1-6638-4e71-a7f9-c3be466905bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393961187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3393961187
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.929954641
Short name T236
Test name
Test status
Simulation time 43524752 ps
CPU time 0.95 seconds
Started Oct 08 01:41:56 PM PDT 23
Finished Oct 08 01:41:57 PM PDT 23
Peak memory 215772 kb
Host smart-dbf335b9-50fa-4fb7-aff0-3fcdb1abbf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929954641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.929954641
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2840937385
Short name T277
Test name
Test status
Simulation time 45923017 ps
CPU time 0.88 seconds
Started Oct 08 01:43:31 PM PDT 23
Finished Oct 08 01:43:32 PM PDT 23
Peak memory 204996 kb
Host smart-23e22997-a6c1-4817-9a78-2aae5e80651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840937385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2840937385
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2795751882
Short name T607
Test name
Test status
Simulation time 20346420 ps
CPU time 1.08 seconds
Started Oct 08 01:47:58 PM PDT 23
Finished Oct 08 01:48:00 PM PDT 23
Peak memory 214588 kb
Host smart-f6712e97-4024-4384-acfa-450879331721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795751882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2795751882
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.374890818
Short name T291
Test name
Test status
Simulation time 24442331 ps
CPU time 0.86 seconds
Started Oct 08 01:55:59 PM PDT 23
Finished Oct 08 01:56:00 PM PDT 23
Peak memory 204904 kb
Host smart-d8f2f21c-d882-45cc-8148-5fc2a1878c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374890818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.374890818
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3635250490
Short name T53
Test name
Test status
Simulation time 1428242983 ps
CPU time 6.44 seconds
Started Oct 08 01:41:01 PM PDT 23
Finished Oct 08 01:41:08 PM PDT 23
Peak memory 232136 kb
Host smart-1f4164eb-f107-4c5a-b615-f833a20671dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635250490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3635250490
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2163292999
Short name T685
Test name
Test status
Simulation time 42177433 ps
CPU time 0.83 seconds
Started Oct 08 01:48:00 PM PDT 23
Finished Oct 08 01:48:01 PM PDT 23
Peak memory 204756 kb
Host smart-bdcdd7c5-70f4-41ea-a677-ea634f450302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163292999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2163292999
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3842927358
Short name T88
Test name
Test status
Simulation time 433006617 ps
CPU time 2.69 seconds
Started Oct 08 01:42:26 PM PDT 23
Finished Oct 08 01:42:29 PM PDT 23
Peak memory 206040 kb
Host smart-6107919f-cca2-46ac-9344-a11695df3e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842927358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3842927358
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3098184738
Short name T622
Test name
Test status
Simulation time 6996117013 ps
CPU time 155.52 seconds
Started Oct 08 01:43:32 PM PDT 23
Finished Oct 08 01:46:08 PM PDT 23
Peak memory 214520 kb
Host smart-056dff30-4da7-4727-99be-5c42822f8bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098184738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3098184738
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.944270709
Short name T674
Test name
Test status
Simulation time 33864117 ps
CPU time 0.93 seconds
Started Oct 08 01:43:36 PM PDT 23
Finished Oct 08 01:43:37 PM PDT 23
Peak memory 206052 kb
Host smart-1f9d27c6-65d7-48a8-a374-c09f33fda99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944270709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.944270709
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3251243186
Short name T455
Test name
Test status
Simulation time 33624103 ps
CPU time 0.76 seconds
Started Oct 08 01:44:19 PM PDT 23
Finished Oct 08 01:44:20 PM PDT 23
Peak memory 203944 kb
Host smart-b5f676e3-530d-491c-a7eb-bd17d326705d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251243186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3251243186
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3772386835
Short name T130
Test name
Test status
Simulation time 12816567 ps
CPU time 0.85 seconds
Started Oct 08 01:43:36 PM PDT 23
Finished Oct 08 01:43:37 PM PDT 23
Peak memory 214552 kb
Host smart-cf5d543a-5812-44f1-955a-f3f742a9c884
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772386835 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3772386835
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1217144130
Short name T168
Test name
Test status
Simulation time 54962759 ps
CPU time 0.95 seconds
Started Oct 08 01:54:27 PM PDT 23
Finished Oct 08 01:54:29 PM PDT 23
Peak memory 214608 kb
Host smart-63d433ec-b5ea-48fb-b411-302acc047ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217144130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1217144130
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.169096809
Short name T91
Test name
Test status
Simulation time 21576062 ps
CPU time 1.07 seconds
Started Oct 08 01:49:30 PM PDT 23
Finished Oct 08 01:49:31 PM PDT 23
Peak memory 205168 kb
Host smart-8515d230-e31b-437f-91ae-1f0db91be160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169096809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.169096809
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1757494437
Short name T652
Test name
Test status
Simulation time 26915586 ps
CPU time 1.03 seconds
Started Oct 08 01:49:30 PM PDT 23
Finished Oct 08 01:49:31 PM PDT 23
Peak memory 221616 kb
Host smart-5a4da393-28f2-438a-ba39-81ab38f6c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757494437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1757494437
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2753558497
Short name T21
Test name
Test status
Simulation time 16679217 ps
CPU time 1.01 seconds
Started Oct 08 01:46:42 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 204672 kb
Host smart-9fed2d3b-783c-46d4-8e44-2ce091a9dc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753558497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2753558497
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.128109290
Short name T602
Test name
Test status
Simulation time 593460932 ps
CPU time 4.31 seconds
Started Oct 08 01:49:31 PM PDT 23
Finished Oct 08 01:49:35 PM PDT 23
Peak memory 206000 kb
Host smart-435670ba-1e2f-44bf-b9a5-52f958c39f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128109290 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.128109290
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1116743094
Short name T655
Test name
Test status
Simulation time 49618952547 ps
CPU time 1160.29 seconds
Started Oct 08 01:43:41 PM PDT 23
Finished Oct 08 02:03:01 PM PDT 23
Peak memory 216036 kb
Host smart-34c56135-50c4-496a-84ed-01b6da253341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116743094 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1116743094
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_alert.1638513302
Short name T254
Test name
Test status
Simulation time 24675231 ps
CPU time 0.96 seconds
Started Oct 08 01:55:38 PM PDT 23
Finished Oct 08 01:55:39 PM PDT 23
Peak memory 204724 kb
Host smart-258065dd-e58d-4feb-b288-700a8354ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638513302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1638513302
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1894545075
Short name T460
Test name
Test status
Simulation time 40408962 ps
CPU time 0.83 seconds
Started Oct 08 01:44:24 PM PDT 23
Finished Oct 08 01:44:25 PM PDT 23
Peak memory 204500 kb
Host smart-da3be4d7-61e4-467f-86a5-924a463c3929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894545075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1894545075
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2857114409
Short name T240
Test name
Test status
Simulation time 52216370 ps
CPU time 1.13 seconds
Started Oct 08 01:55:38 PM PDT 23
Finished Oct 08 01:55:40 PM PDT 23
Peak memory 214588 kb
Host smart-3208b15d-4e9e-4e8f-8d3b-9b6ccc16f0dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857114409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2857114409
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.649536865
Short name T137
Test name
Test status
Simulation time 27211094 ps
CPU time 1.17 seconds
Started Oct 08 01:43:08 PM PDT 23
Finished Oct 08 01:43:09 PM PDT 23
Peak memory 214608 kb
Host smart-b856e7ca-28b2-4478-a634-2a0bcdb02a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649536865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.649536865
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2889532130
Short name T723
Test name
Test status
Simulation time 34880892 ps
CPU time 1.14 seconds
Started Oct 08 01:45:25 PM PDT 23
Finished Oct 08 01:45:27 PM PDT 23
Peak memory 214272 kb
Host smart-0317acab-43d4-4bf7-9f9c-61ddbdf7dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889532130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2889532130
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.476636493
Short name T721
Test name
Test status
Simulation time 14820781 ps
CPU time 0.88 seconds
Started Oct 08 01:49:43 PM PDT 23
Finished Oct 08 01:49:44 PM PDT 23
Peak memory 204788 kb
Host smart-e2b5ac89-e601-494b-baba-58b82350e30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476636493 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.476636493
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.518641547
Short name T519
Test name
Test status
Simulation time 50106855 ps
CPU time 1.4 seconds
Started Oct 08 01:45:53 PM PDT 23
Finished Oct 08 01:45:54 PM PDT 23
Peak memory 205936 kb
Host smart-07c4aed2-df96-41ed-946f-02de72d39c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518641547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.518641547
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.369822198
Short name T570
Test name
Test status
Simulation time 138977001471 ps
CPU time 1893.65 seconds
Started Oct 08 01:41:41 PM PDT 23
Finished Oct 08 02:13:19 PM PDT 23
Peak memory 220552 kb
Host smart-5ab3835a-f311-4873-acb5-98a5fe979c07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369822198 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.369822198
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.3340041307
Short name T606
Test name
Test status
Simulation time 19639768 ps
CPU time 1.08 seconds
Started Oct 08 01:56:08 PM PDT 23
Finished Oct 08 01:56:09 PM PDT 23
Peak memory 206080 kb
Host smart-93b6ad35-a258-41af-b4f8-cc3a72edaf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340041307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3340041307
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1639714639
Short name T488
Test name
Test status
Simulation time 203638666 ps
CPU time 0.86 seconds
Started Oct 08 01:45:44 PM PDT 23
Finished Oct 08 01:45:45 PM PDT 23
Peak memory 205192 kb
Host smart-5683be47-7cdb-4200-8a60-c84a02f00633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639714639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1639714639
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3117236397
Short name T76
Test name
Test status
Simulation time 11957151 ps
CPU time 0.9 seconds
Started Oct 08 01:51:42 PM PDT 23
Finished Oct 08 01:51:43 PM PDT 23
Peak memory 214508 kb
Host smart-51dedfb5-3042-48f0-94fb-3bfd880854be
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117236397 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3117236397
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1018934216
Short name T556
Test name
Test status
Simulation time 42844694 ps
CPU time 1.22 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 222044 kb
Host smart-71d2e8ca-29a5-487b-86e3-e907a8a805db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018934216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1018934216
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3225117499
Short name T281
Test name
Test status
Simulation time 171463613 ps
CPU time 1.01 seconds
Started Oct 08 01:43:52 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 205172 kb
Host smart-21ff36e1-c75a-41fd-a86b-0997e2ae3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225117499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3225117499
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2928564725
Short name T576
Test name
Test status
Simulation time 24424325 ps
CPU time 0.93 seconds
Started Oct 08 01:44:35 PM PDT 23
Finished Oct 08 01:44:36 PM PDT 23
Peak memory 214652 kb
Host smart-0a17d249-d2e0-4791-9692-84e8dc7c2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928564725 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2928564725
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1941955772
Short name T307
Test name
Test status
Simulation time 54098241 ps
CPU time 0.88 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:52 PM PDT 23
Peak memory 204868 kb
Host smart-d3654ca6-b983-4351-bb84-24a6218ea493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941955772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1941955772
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.673794489
Short name T563
Test name
Test status
Simulation time 52948483 ps
CPU time 1.61 seconds
Started Oct 08 01:50:45 PM PDT 23
Finished Oct 08 01:50:46 PM PDT 23
Peak memory 206216 kb
Host smart-87c3f616-0a0a-49b1-95d9-7905c40e0ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673794489 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.673794489
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3667149999
Short name T486
Test name
Test status
Simulation time 47555978550 ps
CPU time 637.61 seconds
Started Oct 08 01:50:47 PM PDT 23
Finished Oct 08 02:01:25 PM PDT 23
Peak memory 215644 kb
Host smart-1fd12dec-76e3-4685-8028-2d0a2561997c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667149999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3667149999
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.2032508856
Short name T253
Test name
Test status
Simulation time 121141960 ps
CPU time 1 seconds
Started Oct 08 01:46:17 PM PDT 23
Finished Oct 08 01:46:18 PM PDT 23
Peak memory 205268 kb
Host smart-d73d4f18-4957-40ea-8c53-e7361ee8bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032508856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2032508856
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3688415988
Short name T51
Test name
Test status
Simulation time 43941491 ps
CPU time 0.86 seconds
Started Oct 08 01:43:27 PM PDT 23
Finished Oct 08 01:43:28 PM PDT 23
Peak memory 205548 kb
Host smart-9497ee49-d816-4d6b-9ced-a653659710f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688415988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3688415988
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3935255256
Short name T42
Test name
Test status
Simulation time 38055518 ps
CPU time 1.07 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 214732 kb
Host smart-ec15cb12-46a1-4cf5-b8d5-0a734d98c75d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935255256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3935255256
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1529918551
Short name T198
Test name
Test status
Simulation time 18141431 ps
CPU time 1 seconds
Started Oct 08 01:46:08 PM PDT 23
Finished Oct 08 01:46:09 PM PDT 23
Peak memory 215664 kb
Host smart-d8a4e72a-ce6f-4c79-981d-66b22a190921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529918551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1529918551
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3580740617
Short name T71
Test name
Test status
Simulation time 41692680 ps
CPU time 1.14 seconds
Started Oct 08 01:43:04 PM PDT 23
Finished Oct 08 01:43:05 PM PDT 23
Peak memory 204952 kb
Host smart-52da5494-26e5-406f-80a2-4dd3e48dbd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580740617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3580740617
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.902600862
Short name T497
Test name
Test status
Simulation time 20779415 ps
CPU time 1.14 seconds
Started Oct 08 01:43:48 PM PDT 23
Finished Oct 08 01:43:49 PM PDT 23
Peak memory 221588 kb
Host smart-b9b5379a-33cd-4146-826b-5d6d67750f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902600862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.902600862
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3065519603
Short name T510
Test name
Test status
Simulation time 15202192 ps
CPU time 0.91 seconds
Started Oct 08 01:41:47 PM PDT 23
Finished Oct 08 01:41:48 PM PDT 23
Peak memory 204880 kb
Host smart-8e3a3035-e1d7-45a5-a968-87456d017e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065519603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3065519603
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3480866586
Short name T724
Test name
Test status
Simulation time 172457091 ps
CPU time 3.68 seconds
Started Oct 08 01:44:28 PM PDT 23
Finished Oct 08 01:44:32 PM PDT 23
Peak memory 206256 kb
Host smart-fa259fab-82ee-4445-8c3f-198cc9c12e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480866586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3480866586
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_alert.1401914320
Short name T483
Test name
Test status
Simulation time 20558841 ps
CPU time 0.99 seconds
Started Oct 08 01:46:12 PM PDT 23
Finished Oct 08 01:46:13 PM PDT 23
Peak memory 205204 kb
Host smart-5168cfb4-d773-47fc-b300-099eeeba5263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401914320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1401914320
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2568568384
Short name T311
Test name
Test status
Simulation time 25370348 ps
CPU time 0.88 seconds
Started Oct 08 01:41:56 PM PDT 23
Finished Oct 08 01:41:57 PM PDT 23
Peak memory 205236 kb
Host smart-24086f8f-1c70-48e8-82a7-06b91133c1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568568384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2568568384
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.516684031
Short name T585
Test name
Test status
Simulation time 15914603 ps
CPU time 0.82 seconds
Started Oct 08 01:42:05 PM PDT 23
Finished Oct 08 01:42:06 PM PDT 23
Peak memory 214344 kb
Host smart-02f39445-3103-447e-8436-64059c6b6f18
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516684031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.516684031
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1763561399
Short name T197
Test name
Test status
Simulation time 22432453 ps
CPU time 0.96 seconds
Started Oct 08 01:55:59 PM PDT 23
Finished Oct 08 01:56:00 PM PDT 23
Peak memory 221448 kb
Host smart-3447142a-dfab-4a02-b7fc-235d2aafc80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763561399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1763561399
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.360833299
Short name T11
Test name
Test status
Simulation time 53593083 ps
CPU time 1.28 seconds
Started Oct 08 01:46:18 PM PDT 23
Finished Oct 08 01:46:20 PM PDT 23
Peak memory 214404 kb
Host smart-f2480514-2280-4411-af98-8d3c46048645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360833299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.360833299
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3229911742
Short name T309
Test name
Test status
Simulation time 31333557 ps
CPU time 0.87 seconds
Started Oct 08 01:44:35 PM PDT 23
Finished Oct 08 01:44:36 PM PDT 23
Peak memory 214388 kb
Host smart-cbb1252e-c90d-4ba7-b33d-d0b637a3df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229911742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3229911742
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3087811700
Short name T581
Test name
Test status
Simulation time 48603010 ps
CPU time 0.8 seconds
Started Oct 08 01:48:53 PM PDT 23
Finished Oct 08 01:48:54 PM PDT 23
Peak memory 204724 kb
Host smart-9070c216-00bd-4171-a901-135ec1740549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087811700 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3087811700
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1828699127
Short name T719
Test name
Test status
Simulation time 157202145 ps
CPU time 3.62 seconds
Started Oct 08 01:51:30 PM PDT 23
Finished Oct 08 01:51:34 PM PDT 23
Peak memory 206160 kb
Host smart-d5268c9f-ebb6-46b2-92ab-c5ec0f2d6631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828699127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1828699127
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_alert.3131095069
Short name T544
Test name
Test status
Simulation time 65720817 ps
CPU time 0.9 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:44 PM PDT 23
Peak memory 205108 kb
Host smart-29327f32-9859-46ce-b40d-9f46a1abdb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131095069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3131095069
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3754521066
Short name T512
Test name
Test status
Simulation time 15836205 ps
CPU time 0.94 seconds
Started Oct 08 01:49:25 PM PDT 23
Finished Oct 08 01:49:27 PM PDT 23
Peak memory 204676 kb
Host smart-bee0a31f-d084-48c7-8e4d-d3d69df34bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754521066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3754521066
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3775365200
Short name T129
Test name
Test status
Simulation time 28304670 ps
CPU time 0.84 seconds
Started Oct 08 01:42:48 PM PDT 23
Finished Oct 08 01:42:49 PM PDT 23
Peak memory 214500 kb
Host smart-19df7d1d-0dec-4095-b901-3cae569f0233
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775365200 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3775365200
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.666270606
Short name T82
Test name
Test status
Simulation time 28193217 ps
CPU time 0.88 seconds
Started Oct 08 01:42:05 PM PDT 23
Finished Oct 08 01:42:06 PM PDT 23
Peak memory 214672 kb
Host smart-6ad75055-f119-42b0-8874-fe6387f53dd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666270606 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.666270606
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.483802810
Short name T527
Test name
Test status
Simulation time 70277308 ps
CPU time 0.97 seconds
Started Oct 08 01:42:44 PM PDT 23
Finished Oct 08 01:42:45 PM PDT 23
Peak memory 216852 kb
Host smart-7c6b2960-b084-40a2-94a2-95c01855aecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483802810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.483802810
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.789507169
Short name T624
Test name
Test status
Simulation time 56344448 ps
CPU time 1.14 seconds
Started Oct 08 01:46:39 PM PDT 23
Finished Oct 08 01:46:40 PM PDT 23
Peak memory 214444 kb
Host smart-8fa83589-3ae5-4bec-b871-dcfb4c889917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789507169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.789507169
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.1333527128
Short name T597
Test name
Test status
Simulation time 23775589 ps
CPU time 0.88 seconds
Started Oct 08 01:43:55 PM PDT 23
Finished Oct 08 01:43:56 PM PDT 23
Peak memory 204680 kb
Host smart-d9888aa4-1b4f-4144-915a-ceb658be1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333527128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1333527128
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3456597296
Short name T118
Test name
Test status
Simulation time 61718711 ps
CPU time 1.75 seconds
Started Oct 08 01:42:52 PM PDT 23
Finished Oct 08 01:42:54 PM PDT 23
Peak memory 205648 kb
Host smart-63b2f94a-4a93-4623-bf9a-b4b3a759f529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456597296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3456597296
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.861641089
Short name T633
Test name
Test status
Simulation time 99190373499 ps
CPU time 566.25 seconds
Started Oct 08 01:48:27 PM PDT 23
Finished Oct 08 01:57:54 PM PDT 23
Peak memory 215716 kb
Host smart-692f4113-fde2-4e8b-9832-b0c664078620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861641089 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.861641089
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.edn_alert.3495666636
Short name T621
Test name
Test status
Simulation time 129819761 ps
CPU time 0.97 seconds
Started Oct 08 01:45:06 PM PDT 23
Finished Oct 08 01:45:12 PM PDT 23
Peak memory 205156 kb
Host smart-62272929-7704-49de-a32e-10d1f2cf6f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495666636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3495666636
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2293938666
Short name T313
Test name
Test status
Simulation time 188999059 ps
CPU time 0.83 seconds
Started Oct 08 01:45:30 PM PDT 23
Finished Oct 08 01:45:31 PM PDT 23
Peak memory 204356 kb
Host smart-b1d3feee-5939-4cbe-9c76-87aa9998d659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293938666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2293938666
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3916067728
Short name T79
Test name
Test status
Simulation time 61706093 ps
CPU time 0.88 seconds
Started Oct 08 01:46:17 PM PDT 23
Finished Oct 08 01:46:18 PM PDT 23
Peak memory 214444 kb
Host smart-e236d350-87c0-4c11-86ea-3e54f7a924b0
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916067728 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3916067728
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2929526861
Short name T646
Test name
Test status
Simulation time 83359610 ps
CPU time 0.97 seconds
Started Oct 08 01:46:31 PM PDT 23
Finished Oct 08 01:46:32 PM PDT 23
Peak memory 214656 kb
Host smart-79bacab2-d7b8-413f-b2e1-895fa58207e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929526861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2929526861
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_genbits.2432851012
Short name T535
Test name
Test status
Simulation time 55658454 ps
CPU time 0.91 seconds
Started Oct 08 01:48:20 PM PDT 23
Finished Oct 08 01:48:21 PM PDT 23
Peak memory 205104 kb
Host smart-3c1fa6c6-08be-4416-bde4-37a19f6a70fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432851012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2432851012
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1480484787
Short name T567
Test name
Test status
Simulation time 37438642 ps
CPU time 0.97 seconds
Started Oct 08 01:44:02 PM PDT 23
Finished Oct 08 01:44:03 PM PDT 23
Peak memory 221452 kb
Host smart-26f9510d-b22e-4919-9850-be3b648e34dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480484787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1480484787
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2429718001
Short name T678
Test name
Test status
Simulation time 13436241 ps
CPU time 0.85 seconds
Started Oct 08 01:42:05 PM PDT 23
Finished Oct 08 01:42:07 PM PDT 23
Peak memory 204648 kb
Host smart-1b520417-e825-4847-806d-e135cc5df7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429718001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2429718001
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2211751361
Short name T502
Test name
Test status
Simulation time 32295968 ps
CPU time 1.19 seconds
Started Oct 08 01:44:45 PM PDT 23
Finished Oct 08 01:44:46 PM PDT 23
Peak memory 205048 kb
Host smart-4332e9d3-eeed-4824-8cf5-9eea5df0f4ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211751361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2211751361
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2968867352
Short name T694
Test name
Test status
Simulation time 155328996647 ps
CPU time 1966.05 seconds
Started Oct 08 01:42:08 PM PDT 23
Finished Oct 08 02:14:55 PM PDT 23
Peak memory 223236 kb
Host smart-4bd3e601-78da-4ad7-ab43-043846f83892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968867352 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2968867352
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_alert.2331222176
Short name T317
Test name
Test status
Simulation time 56735848 ps
CPU time 0.97 seconds
Started Oct 08 01:55:16 PM PDT 23
Finished Oct 08 01:55:18 PM PDT 23
Peak memory 206084 kb
Host smart-c55bc125-975d-46ef-9275-d2aaeb7189d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331222176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2331222176
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.311777347
Short name T320
Test name
Test status
Simulation time 21465471 ps
CPU time 0.78 seconds
Started Oct 08 01:49:12 PM PDT 23
Finished Oct 08 01:49:13 PM PDT 23
Peak memory 204248 kb
Host smart-5b2737c4-97d8-495b-84d5-510223fb4d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311777347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.311777347
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1118501508
Short name T594
Test name
Test status
Simulation time 12754670 ps
CPU time 0.82 seconds
Started Oct 08 01:53:51 PM PDT 23
Finished Oct 08 01:53:52 PM PDT 23
Peak memory 214436 kb
Host smart-e976784e-3a45-49d2-9ce6-d92ea1d661df
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118501508 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1118501508
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.1637094581
Short name T249
Test name
Test status
Simulation time 22023503 ps
CPU time 1.13 seconds
Started Oct 08 01:47:42 PM PDT 23
Finished Oct 08 01:47:43 PM PDT 23
Peak memory 214780 kb
Host smart-9042324e-e992-481c-8cdb-326365a8b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637094581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1637094581
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.4098974149
Short name T671
Test name
Test status
Simulation time 58727489 ps
CPU time 0.94 seconds
Started Oct 08 01:50:19 PM PDT 23
Finished Oct 08 01:50:20 PM PDT 23
Peak memory 205728 kb
Host smart-a9eeccc5-e6a8-4e1d-804e-b66c681fa8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098974149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4098974149
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.882668234
Short name T454
Test name
Test status
Simulation time 33762757 ps
CPU time 0.85 seconds
Started Oct 08 01:44:53 PM PDT 23
Finished Oct 08 01:44:54 PM PDT 23
Peak memory 214264 kb
Host smart-3ac9f50e-628e-414c-8ec5-dc9574d742c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882668234 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.882668234
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3032893161
Short name T672
Test name
Test status
Simulation time 15848403 ps
CPU time 0.89 seconds
Started Oct 08 01:42:21 PM PDT 23
Finished Oct 08 01:42:22 PM PDT 23
Peak memory 204736 kb
Host smart-13a51c82-eceb-40d4-a2ea-fb64950ee7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032893161 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3032893161
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1468658772
Short name T504
Test name
Test status
Simulation time 59892561 ps
CPU time 1.64 seconds
Started Oct 08 01:45:05 PM PDT 23
Finished Oct 08 01:45:07 PM PDT 23
Peak memory 205376 kb
Host smart-e22a8118-ee23-44d5-9d29-ea7aa7ceaa9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468658772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1468658772
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_alert_test.849185569
Short name T299
Test name
Test status
Simulation time 15756921 ps
CPU time 0.9 seconds
Started Oct 08 01:46:53 PM PDT 23
Finished Oct 08 01:46:54 PM PDT 23
Peak memory 204576 kb
Host smart-6d4cce6a-fa87-4259-91a3-9b9dc315c443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849185569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.849185569
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.4125366484
Short name T239
Test name
Test status
Simulation time 13536888 ps
CPU time 0.84 seconds
Started Oct 08 01:56:32 PM PDT 23
Finished Oct 08 01:56:33 PM PDT 23
Peak memory 214592 kb
Host smart-9f6092ee-ea14-49e3-93b7-b596619f0188
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125366484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4125366484
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.107016254
Short name T675
Test name
Test status
Simulation time 36672977 ps
CPU time 0.96 seconds
Started Oct 08 01:42:40 PM PDT 23
Finished Oct 08 01:42:42 PM PDT 23
Peak memory 214556 kb
Host smart-9e03e7b5-a5fd-4e85-8e8a-21b6e38eb3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107016254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.107016254
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4021915881
Short name T166
Test name
Test status
Simulation time 35013405 ps
CPU time 1.01 seconds
Started Oct 08 01:44:57 PM PDT 23
Finished Oct 08 01:44:58 PM PDT 23
Peak memory 214404 kb
Host smart-dca13bb3-5e43-4ecb-985a-25059ea2ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021915881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4021915881
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.833694366
Short name T489
Test name
Test status
Simulation time 27559603 ps
CPU time 1.15 seconds
Started Oct 08 01:53:50 PM PDT 23
Finished Oct 08 01:53:51 PM PDT 23
Peak memory 214468 kb
Host smart-bc37e5a7-be16-4181-aae3-6210799a7294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833694366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.833694366
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1381360985
Short name T22
Test name
Test status
Simulation time 23289124 ps
CPU time 0.93 seconds
Started Oct 08 01:42:35 PM PDT 23
Finished Oct 08 01:42:36 PM PDT 23
Peak memory 214564 kb
Host smart-3f9e60e2-aa77-45bb-8174-008f51f610c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381360985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1381360985
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2217939130
Short name T304
Test name
Test status
Simulation time 14541640 ps
CPU time 0.89 seconds
Started Oct 08 01:45:05 PM PDT 23
Finished Oct 08 01:45:06 PM PDT 23
Peak memory 204644 kb
Host smart-ecdd28bd-e11b-430b-99b7-749daae9739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217939130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2217939130
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.457656761
Short name T156
Test name
Test status
Simulation time 242952121 ps
CPU time 1.76 seconds
Started Oct 08 01:52:35 PM PDT 23
Finished Oct 08 01:52:37 PM PDT 23
Peak memory 205356 kb
Host smart-be814951-bf06-482a-8adb-64513bb73331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457656761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.457656761
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1065819324
Short name T703
Test name
Test status
Simulation time 13593671495 ps
CPU time 321.4 seconds
Started Oct 08 01:43:14 PM PDT 23
Finished Oct 08 01:48:35 PM PDT 23
Peak memory 214704 kb
Host smart-4545cb8d-9d5d-4a47-aec8-06b69781f1c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065819324 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1065819324
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_alert.71185511
Short name T717
Test name
Test status
Simulation time 26210232 ps
CPU time 1 seconds
Started Oct 08 01:44:52 PM PDT 23
Finished Oct 08 01:44:53 PM PDT 23
Peak memory 206228 kb
Host smart-e45f061a-d513-4df6-8a67-9edcfa35c22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71185511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.71185511
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3034463419
Short name T308
Test name
Test status
Simulation time 48266623 ps
CPU time 0.85 seconds
Started Oct 08 01:48:24 PM PDT 23
Finished Oct 08 01:48:25 PM PDT 23
Peak memory 205264 kb
Host smart-6f79c2b7-9376-4b9d-8734-4da9b9894a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034463419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3034463419
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1206664847
Short name T73
Test name
Test status
Simulation time 33070132 ps
CPU time 0.92 seconds
Started Oct 08 01:44:54 PM PDT 23
Finished Oct 08 01:44:56 PM PDT 23
Peak memory 214560 kb
Host smart-4dc3b432-eb86-4325-934f-ec833ef1115b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206664847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1206664847
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1275078757
Short name T659
Test name
Test status
Simulation time 42996017 ps
CPU time 1.22 seconds
Started Oct 08 01:43:23 PM PDT 23
Finished Oct 08 01:43:25 PM PDT 23
Peak memory 222172 kb
Host smart-f4b5f8f1-7380-4726-a7ae-2bc0eefa30f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275078757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1275078757
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3865199023
Short name T280
Test name
Test status
Simulation time 61112069 ps
CPU time 0.95 seconds
Started Oct 08 01:49:41 PM PDT 23
Finished Oct 08 01:49:43 PM PDT 23
Peak memory 205128 kb
Host smart-4afbc6ce-c633-41ee-90f4-595b18b71314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865199023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3865199023
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1337979188
Short name T32
Test name
Test status
Simulation time 19831538 ps
CPU time 1.05 seconds
Started Oct 08 01:45:31 PM PDT 23
Finished Oct 08 01:45:32 PM PDT 23
Peak memory 214540 kb
Host smart-121a5956-e155-4085-8c42-eb1bca4b154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337979188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1337979188
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2498684871
Short name T321
Test name
Test status
Simulation time 54250015 ps
CPU time 0.84 seconds
Started Oct 08 01:46:54 PM PDT 23
Finished Oct 08 01:46:55 PM PDT 23
Peak memory 204944 kb
Host smart-81e5ef56-4855-4bce-931a-9e71fc58fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498684871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2498684871
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1327381061
Short name T614
Test name
Test status
Simulation time 99586529 ps
CPU time 2.58 seconds
Started Oct 08 01:42:33 PM PDT 23
Finished Oct 08 01:42:36 PM PDT 23
Peak memory 205768 kb
Host smart-525eab92-c88d-4ecd-a484-8b9a56973408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327381061 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1327381061
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.355692509
Short name T511
Test name
Test status
Simulation time 105129100514 ps
CPU time 1270.1 seconds
Started Oct 08 01:44:08 PM PDT 23
Finished Oct 08 02:05:18 PM PDT 23
Peak memory 219132 kb
Host smart-5ec964f5-18db-420c-badd-d73eb5947dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355692509 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.355692509
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_alert.2006812463
Short name T620
Test name
Test status
Simulation time 20777282 ps
CPU time 1.05 seconds
Started Oct 08 01:48:39 PM PDT 23
Finished Oct 08 01:48:41 PM PDT 23
Peak memory 206036 kb
Host smart-ff5a5cdb-aa36-400c-85b2-45b7d1e82c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006812463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2006812463
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2392416088
Short name T493
Test name
Test status
Simulation time 13743776 ps
CPU time 0.9 seconds
Started Oct 08 01:41:06 PM PDT 23
Finished Oct 08 01:41:07 PM PDT 23
Peak memory 204656 kb
Host smart-123637e5-dd08-4e8e-866e-d3667a9934b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392416088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2392416088
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.723492180
Short name T173
Test name
Test status
Simulation time 68601602 ps
CPU time 0.94 seconds
Started Oct 08 01:53:05 PM PDT 23
Finished Oct 08 01:53:06 PM PDT 23
Peak memory 214724 kb
Host smart-413c2846-3f19-4e19-9e1f-cbdcbe0a220d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723492180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.723492180
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.605774146
Short name T689
Test name
Test status
Simulation time 24608150 ps
CPU time 1 seconds
Started Oct 08 01:41:04 PM PDT 23
Finished Oct 08 01:41:05 PM PDT 23
Peak memory 221612 kb
Host smart-3fc75310-fda1-41ae-8b84-6c7f451d38e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605774146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.605774146
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_intr.1389927950
Short name T319
Test name
Test status
Simulation time 66103544 ps
CPU time 0.83 seconds
Started Oct 08 01:56:33 PM PDT 23
Finished Oct 08 01:56:34 PM PDT 23
Peak memory 214388 kb
Host smart-34d3944c-5979-4098-a1f8-22b8fcaadbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389927950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1389927950
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.232857415
Short name T52
Test name
Test status
Simulation time 182391501 ps
CPU time 3.28 seconds
Started Oct 08 01:41:26 PM PDT 23
Finished Oct 08 01:41:29 PM PDT 23
Peak memory 233016 kb
Host smart-99d26946-db42-432b-bae6-2f28c141cd25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232857415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.232857415
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1396063688
Short name T303
Test name
Test status
Simulation time 21877685 ps
CPU time 0.85 seconds
Started Oct 08 01:45:04 PM PDT 23
Finished Oct 08 01:45:05 PM PDT 23
Peak memory 204568 kb
Host smart-1d91b62c-fb33-409d-9739-1146854eac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396063688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1396063688
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3142180433
Short name T461
Test name
Test status
Simulation time 340245914 ps
CPU time 1.5 seconds
Started Oct 08 01:45:48 PM PDT 23
Finished Oct 08 01:45:50 PM PDT 23
Peak memory 205608 kb
Host smart-63262066-8e89-4f6e-a687-14fe295654eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142180433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3142180433
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.274471196
Short name T604
Test name
Test status
Simulation time 132154686599 ps
CPU time 791.34 seconds
Started Oct 08 01:41:32 PM PDT 23
Finished Oct 08 01:54:44 PM PDT 23
Peak memory 215232 kb
Host smart-5c5e071a-078c-4e29-81ed-168224fe32f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274471196 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.274471196
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2959255111
Short name T294
Test name
Test status
Simulation time 19710795 ps
CPU time 0.97 seconds
Started Oct 08 01:44:38 PM PDT 23
Finished Oct 08 01:44:39 PM PDT 23
Peak memory 205092 kb
Host smart-b1d9d36e-a499-42c9-b456-4f58c8cb50b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959255111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2959255111
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2728218333
Short name T45
Test name
Test status
Simulation time 24663919 ps
CPU time 0.85 seconds
Started Oct 08 01:44:34 PM PDT 23
Finished Oct 08 01:44:35 PM PDT 23
Peak memory 205364 kb
Host smart-267acaf0-c79b-4271-87ef-938d1d19cb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728218333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2728218333
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.39851403
Short name T713
Test name
Test status
Simulation time 18782836 ps
CPU time 0.85 seconds
Started Oct 08 01:44:37 PM PDT 23
Finished Oct 08 01:44:38 PM PDT 23
Peak memory 214404 kb
Host smart-d3fc639f-6376-4910-a5f3-334a60031fc2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39851403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.39851403
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.567924540
Short name T178
Test name
Test status
Simulation time 50670860 ps
CPU time 1.12 seconds
Started Oct 08 01:48:36 PM PDT 23
Finished Oct 08 01:48:37 PM PDT 23
Peak memory 214632 kb
Host smart-3ab92565-2150-4973-9de7-13ac4726f755
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567924540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.567924540
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3662918807
Short name T201
Test name
Test status
Simulation time 28925235 ps
CPU time 0.86 seconds
Started Oct 08 01:55:26 PM PDT 23
Finished Oct 08 01:55:27 PM PDT 23
Peak memory 215504 kb
Host smart-d6f43a98-e761-4a32-b615-a75cd4b2f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662918807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3662918807
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_smoke.3670095124
Short name T318
Test name
Test status
Simulation time 16038086 ps
CPU time 0.95 seconds
Started Oct 08 01:48:35 PM PDT 23
Finished Oct 08 01:48:36 PM PDT 23
Peak memory 204952 kb
Host smart-768c2a15-dc4f-4fd7-aae5-842e542690e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670095124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3670095124
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1942485111
Short name T159
Test name
Test status
Simulation time 610730317 ps
CPU time 2.24 seconds
Started Oct 08 01:42:51 PM PDT 23
Finished Oct 08 01:42:54 PM PDT 23
Peak memory 205648 kb
Host smart-8d5fef0b-2b0a-4c5e-b526-a244a69abe58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942485111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1942485111
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.4191050746
Short name T25
Test name
Test status
Simulation time 29926664509 ps
CPU time 387.08 seconds
Started Oct 08 01:44:52 PM PDT 23
Finished Oct 08 01:51:19 PM PDT 23
Peak memory 215240 kb
Host smart-07948a93-37fa-435f-973d-e083c4dbca14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191050746 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4191050746
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.edn_alert.3196181997
Short name T549
Test name
Test status
Simulation time 94191836 ps
CPU time 0.95 seconds
Started Oct 08 01:44:13 PM PDT 23
Finished Oct 08 01:44:14 PM PDT 23
Peak memory 205124 kb
Host smart-d78ab117-17d9-4813-84a3-544d6ae643d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196181997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3196181997
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2064606117
Short name T645
Test name
Test status
Simulation time 31064650 ps
CPU time 0.86 seconds
Started Oct 08 01:43:34 PM PDT 23
Finished Oct 08 01:43:35 PM PDT 23
Peak memory 204576 kb
Host smart-3b167a46-328a-4be2-b4b1-551514a1d2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064606117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2064606117
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2607942777
Short name T66
Test name
Test status
Simulation time 27330998 ps
CPU time 0.89 seconds
Started Oct 08 01:44:16 PM PDT 23
Finished Oct 08 01:44:17 PM PDT 23
Peak memory 214460 kb
Host smart-c0255455-34dd-40d7-ad1b-ebfc2ba79fea
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607942777 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2607942777
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2401193341
Short name T242
Test name
Test status
Simulation time 24277406 ps
CPU time 0.98 seconds
Started Oct 08 01:43:29 PM PDT 23
Finished Oct 08 01:43:30 PM PDT 23
Peak memory 214640 kb
Host smart-5cee1d7c-d3a7-4078-a613-2f45f4713937
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401193341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2401193341
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3602973473
Short name T50
Test name
Test status
Simulation time 30480129 ps
CPU time 1.35 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:47 PM PDT 23
Peak memory 220608 kb
Host smart-133ddf8d-f1f1-40cb-bd56-35df48e79858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602973473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3602973473
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_intr.2938231750
Short name T27
Test name
Test status
Simulation time 20897408 ps
CPU time 1.03 seconds
Started Oct 08 01:43:49 PM PDT 23
Finished Oct 08 01:43:50 PM PDT 23
Peak memory 214448 kb
Host smart-99a21c48-3dcb-4290-9ff9-f5f0e34311f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938231750 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2938231750
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.927429244
Short name T96
Test name
Test status
Simulation time 50338493 ps
CPU time 0.89 seconds
Started Oct 08 01:44:32 PM PDT 23
Finished Oct 08 01:44:33 PM PDT 23
Peak memory 204748 kb
Host smart-727f97aa-f2eb-4ba5-9dae-15297200627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927429244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.927429244
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.982737642
Short name T155
Test name
Test status
Simulation time 1163186590 ps
CPU time 4.05 seconds
Started Oct 08 01:44:14 PM PDT 23
Finished Oct 08 01:44:19 PM PDT 23
Peak memory 206172 kb
Host smart-ddb7747a-3c43-40f6-baaa-9440042c0193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982737642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.982737642
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2240847706
Short name T459
Test name
Test status
Simulation time 10358512546 ps
CPU time 236.46 seconds
Started Oct 08 01:44:32 PM PDT 23
Finished Oct 08 01:48:29 PM PDT 23
Peak memory 215156 kb
Host smart-4178e150-943a-40e6-b3c3-d12aee725f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240847706 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2240847706
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.edn_alert.4288833593
Short name T68
Test name
Test status
Simulation time 143136380 ps
CPU time 0.91 seconds
Started Oct 08 01:48:48 PM PDT 23
Finished Oct 08 01:48:49 PM PDT 23
Peak memory 205180 kb
Host smart-10bf673d-e3d9-40b9-b036-983f5eb4b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288833593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4288833593
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1021472245
Short name T123
Test name
Test status
Simulation time 25513690 ps
CPU time 0.82 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:44 PM PDT 23
Peak memory 204556 kb
Host smart-1723e52f-df38-426b-83f9-77e52303a85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021472245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1021472245
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2079857484
Short name T67
Test name
Test status
Simulation time 32990438 ps
CPU time 0.84 seconds
Started Oct 08 01:51:04 PM PDT 23
Finished Oct 08 01:51:05 PM PDT 23
Peak memory 214524 kb
Host smart-55c026fe-785d-4f6c-89ed-6814b052da00
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079857484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2079857484
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2113558170
Short name T30
Test name
Test status
Simulation time 87949342 ps
CPU time 1.1 seconds
Started Oct 08 01:55:24 PM PDT 23
Finished Oct 08 01:55:25 PM PDT 23
Peak memory 214668 kb
Host smart-71e503ac-a08b-49e2-91dd-334021fde56b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113558170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2113558170
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3028807371
Short name T647
Test name
Test status
Simulation time 94860860 ps
CPU time 0.78 seconds
Started Oct 08 01:43:52 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 214184 kb
Host smart-cc183d44-393e-4d25-ab0c-d816990da58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028807371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3028807371
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.4095907116
Short name T492
Test name
Test status
Simulation time 68697209 ps
CPU time 1.2 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:47 PM PDT 23
Peak memory 213096 kb
Host smart-ead01188-845c-4d2b-b01b-1d8dbb86822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095907116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4095907116
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3595677794
Short name T720
Test name
Test status
Simulation time 20092214 ps
CPU time 0.99 seconds
Started Oct 08 01:55:14 PM PDT 23
Finished Oct 08 01:55:15 PM PDT 23
Peak memory 214512 kb
Host smart-a11fd456-5a17-43f5-ad66-401a3364ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595677794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3595677794
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3166439906
Short name T323
Test name
Test status
Simulation time 16429066 ps
CPU time 0.93 seconds
Started Oct 08 01:44:14 PM PDT 23
Finished Oct 08 01:44:16 PM PDT 23
Peak memory 204656 kb
Host smart-ffbb0d2f-97bb-4aba-a899-4ee3b5215dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166439906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3166439906
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.181965691
Short name T682
Test name
Test status
Simulation time 107414519 ps
CPU time 1.82 seconds
Started Oct 08 01:48:50 PM PDT 23
Finished Oct 08 01:48:52 PM PDT 23
Peak memory 205896 kb
Host smart-6a21ceea-6fc1-4e29-bee6-93b80916dbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181965691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.181965691
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.492210442
Short name T584
Test name
Test status
Simulation time 36609539452 ps
CPU time 767.46 seconds
Started Oct 08 01:55:42 PM PDT 23
Finished Oct 08 02:08:30 PM PDT 23
Peak memory 214772 kb
Host smart-4a9deaaa-133b-48bf-80b6-ff5d6691b172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492210442 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.492210442
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.edn_alert_test.763582178
Short name T297
Test name
Test status
Simulation time 20938217 ps
CPU time 0.9 seconds
Started Oct 08 01:44:22 PM PDT 23
Finished Oct 08 01:44:23 PM PDT 23
Peak memory 204772 kb
Host smart-f587ca66-72eb-4ebe-a3c9-1b42cef636ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763582178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.763582178
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3705789474
Short name T692
Test name
Test status
Simulation time 76516390 ps
CPU time 0.96 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 213124 kb
Host smart-90de5e6c-072b-4331-94e4-4ced9412df2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705789474 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3705789474
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.949268759
Short name T48
Test name
Test status
Simulation time 49408105 ps
CPU time 0.97 seconds
Started Oct 08 01:51:28 PM PDT 23
Finished Oct 08 01:51:29 PM PDT 23
Peak memory 221652 kb
Host smart-de3101d6-0156-4a8b-919e-5e532588f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949268759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.949268759
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3264217227
Short name T690
Test name
Test status
Simulation time 23793570 ps
CPU time 1.35 seconds
Started Oct 08 01:48:48 PM PDT 23
Finished Oct 08 01:48:49 PM PDT 23
Peak memory 205652 kb
Host smart-da614f00-e35b-4d92-a3a4-478942b354c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264217227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3264217227
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.839989494
Short name T456
Test name
Test status
Simulation time 55325315 ps
CPU time 0.81 seconds
Started Oct 08 01:43:39 PM PDT 23
Finished Oct 08 01:43:40 PM PDT 23
Peak memory 204688 kb
Host smart-0db6afe7-5d2a-46c5-bcfd-438624985646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839989494 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.839989494
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.820914884
Short name T117
Test name
Test status
Simulation time 115283121 ps
CPU time 1.66 seconds
Started Oct 08 01:42:37 PM PDT 23
Finished Oct 08 01:42:40 PM PDT 23
Peak memory 206096 kb
Host smart-6ff921c2-c2f5-4396-9aea-983ff63f2e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820914884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.820914884
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1165475846
Short name T533
Test name
Test status
Simulation time 36854888174 ps
CPU time 905.87 seconds
Started Oct 08 01:45:09 PM PDT 23
Finished Oct 08 02:00:15 PM PDT 23
Peak memory 215836 kb
Host smart-e159333d-22d1-4513-8aec-f0e5c9fc395c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165475846 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1165475846
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.edn_alert.907271996
Short name T325
Test name
Test status
Simulation time 27047814 ps
CPU time 0.95 seconds
Started Oct 08 01:44:56 PM PDT 23
Finished Oct 08 01:44:57 PM PDT 23
Peak memory 206108 kb
Host smart-85ee7e76-cf55-4bbf-bcab-23eaf99f3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907271996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.907271996
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2407826304
Short name T312
Test name
Test status
Simulation time 16502564 ps
CPU time 0.95 seconds
Started Oct 08 01:49:06 PM PDT 23
Finished Oct 08 01:49:09 PM PDT 23
Peak memory 204576 kb
Host smart-5567e8a3-1a69-409d-bf10-dfd9a7bbc63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407826304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2407826304
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2413548983
Short name T74
Test name
Test status
Simulation time 11004101 ps
CPU time 0.83 seconds
Started Oct 08 01:43:52 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 214312 kb
Host smart-01ff6972-f316-4faa-8fab-7895d7916d04
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413548983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2413548983
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1052526647
Short name T517
Test name
Test status
Simulation time 201036071 ps
CPU time 1.15 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:47 PM PDT 23
Peak memory 212868 kb
Host smart-dc23e4be-88f5-43f1-8ae5-a7148ae01c5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052526647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1052526647
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.737784771
Short name T573
Test name
Test status
Simulation time 23663813 ps
CPU time 1.09 seconds
Started Oct 08 01:43:39 PM PDT 23
Finished Oct 08 01:43:40 PM PDT 23
Peak memory 214452 kb
Host smart-a48b61c0-13c0-4194-9b36-14780e42ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737784771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.737784771
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1171589822
Short name T715
Test name
Test status
Simulation time 72137641 ps
CPU time 1.17 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 203372 kb
Host smart-dfe93e8b-924a-4354-ba73-46b6d2ca3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171589822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1171589822
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.640714120
Short name T1
Test name
Test status
Simulation time 20338755 ps
CPU time 1 seconds
Started Oct 08 01:44:21 PM PDT 23
Finished Oct 08 01:44:23 PM PDT 23
Peak memory 214548 kb
Host smart-ba71c988-57e9-4811-9bd0-7b0a582ffa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640714120 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.640714120
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.618982415
Short name T19
Test name
Test status
Simulation time 11884981 ps
CPU time 0.92 seconds
Started Oct 08 01:43:38 PM PDT 23
Finished Oct 08 01:43:39 PM PDT 23
Peak memory 204824 kb
Host smart-6e5e62d9-d7ae-4a7d-a838-0d8de1582d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618982415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.618982415
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.651588207
Short name T705
Test name
Test status
Simulation time 826401553 ps
CPU time 2.53 seconds
Started Oct 08 01:49:07 PM PDT 23
Finished Oct 08 01:49:11 PM PDT 23
Peak memory 205844 kb
Host smart-f11fe962-5c44-4426-a125-b8dfa8a64f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651588207 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.651588207
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3522236106
Short name T326
Test name
Test status
Simulation time 167284173017 ps
CPU time 2095.37 seconds
Started Oct 08 01:55:42 PM PDT 23
Finished Oct 08 02:30:38 PM PDT 23
Peak memory 224476 kb
Host smart-665ee90d-2fe1-4577-8b1d-657ee94bf718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522236106 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3522236106
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.edn_alert_test.3065016030
Short name T555
Test name
Test status
Simulation time 14886538 ps
CPU time 0.9 seconds
Started Oct 08 01:48:55 PM PDT 23
Finished Oct 08 01:48:56 PM PDT 23
Peak memory 204752 kb
Host smart-a924dddf-6933-4733-9bf1-68ede7b7895e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065016030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3065016030
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.550682325
Short name T75
Test name
Test status
Simulation time 13460817 ps
CPU time 0.88 seconds
Started Oct 08 01:44:23 PM PDT 23
Finished Oct 08 01:44:24 PM PDT 23
Peak memory 214540 kb
Host smart-1b940075-2bbd-480e-929b-690061ffa7b1
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550682325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.550682325
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1454606208
Short name T700
Test name
Test status
Simulation time 24767064 ps
CPU time 1.02 seconds
Started Oct 08 01:44:33 PM PDT 23
Finished Oct 08 01:44:34 PM PDT 23
Peak memory 214728 kb
Host smart-feb93d21-2335-459b-8808-690b6eeb98cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454606208 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1454606208
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3409415965
Short name T729
Test name
Test status
Simulation time 20852054 ps
CPU time 0.92 seconds
Started Oct 08 01:44:25 PM PDT 23
Finished Oct 08 01:44:26 PM PDT 23
Peak memory 215556 kb
Host smart-6a25c74d-56f5-4ed3-bc23-867942336ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409415965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3409415965
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1049320472
Short name T285
Test name
Test status
Simulation time 135496461 ps
CPU time 0.95 seconds
Started Oct 08 01:52:14 PM PDT 23
Finished Oct 08 01:52:15 PM PDT 23
Peak memory 204992 kb
Host smart-5bd7fe69-5f75-4bda-9418-6de6905f279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049320472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1049320472
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1161268327
Short name T467
Test name
Test status
Simulation time 22460144 ps
CPU time 1.08 seconds
Started Oct 08 01:46:19 PM PDT 23
Finished Oct 08 01:46:20 PM PDT 23
Peak memory 214408 kb
Host smart-a9bb474a-4766-4604-ac39-ac873b5ff3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161268327 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1161268327
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.632195585
Short name T507
Test name
Test status
Simulation time 13193142 ps
CPU time 0.98 seconds
Started Oct 08 01:52:13 PM PDT 23
Finished Oct 08 01:52:14 PM PDT 23
Peak memory 205000 kb
Host smart-f5a6aab2-4ebc-4d2d-8775-cbab45af5d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632195585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.632195585
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.308220291
Short name T704
Test name
Test status
Simulation time 31781187 ps
CPU time 1.32 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:45 PM PDT 23
Peak memory 205288 kb
Host smart-e2b7af94-2e70-4f1c-9042-acec15f2a612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308220291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.308220291
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3801765757
Short name T566
Test name
Test status
Simulation time 172021754578 ps
CPU time 427.42 seconds
Started Oct 08 01:52:16 PM PDT 23
Finished Oct 08 01:59:24 PM PDT 23
Peak memory 215500 kb
Host smart-57fc0018-25a1-4e8a-946e-09d2cc0f8b1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801765757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3801765757
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_alert.3931344363
Short name T592
Test name
Test status
Simulation time 20541693 ps
CPU time 1 seconds
Started Oct 08 01:49:42 PM PDT 23
Finished Oct 08 01:49:44 PM PDT 23
Peak memory 206324 kb
Host smart-92162234-da0a-47fb-91fd-0dcaf6ba319f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931344363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3931344363
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.14478738
Short name T465
Test name
Test status
Simulation time 53761894 ps
CPU time 0.88 seconds
Started Oct 08 01:45:23 PM PDT 23
Finished Oct 08 01:45:25 PM PDT 23
Peak memory 205220 kb
Host smart-a84739e7-a049-4471-bdce-2ad7644b2ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.14478738
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3065615592
Short name T617
Test name
Test status
Simulation time 86757399 ps
CPU time 1.11 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:45 PM PDT 23
Peak memory 214560 kb
Host smart-0cd078c9-0357-4c6f-9cea-075ca4b28501
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065615592 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3065615592
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.482757365
Short name T49
Test name
Test status
Simulation time 113728139 ps
CPU time 1.11 seconds
Started Oct 08 01:53:00 PM PDT 23
Finished Oct 08 01:53:02 PM PDT 23
Peak memory 221804 kb
Host smart-4e28a3b1-b31c-4f3c-821b-dca66ed51114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482757365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.482757365
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1360869305
Short name T601
Test name
Test status
Simulation time 45761140 ps
CPU time 0.88 seconds
Started Oct 08 01:45:19 PM PDT 23
Finished Oct 08 01:45:20 PM PDT 23
Peak memory 204788 kb
Host smart-fda41a4a-80b2-4c61-b36f-ea25ea95e1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360869305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1360869305
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2222067942
Short name T113
Test name
Test status
Simulation time 27432366 ps
CPU time 0.87 seconds
Started Oct 08 01:51:25 PM PDT 23
Finished Oct 08 01:51:26 PM PDT 23
Peak memory 214644 kb
Host smart-a23af78a-47de-44d0-b5b0-6ff1510c670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222067942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2222067942
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3136142680
Short name T209
Test name
Test status
Simulation time 97970909 ps
CPU time 0.9 seconds
Started Oct 08 01:45:17 PM PDT 23
Finished Oct 08 01:45:18 PM PDT 23
Peak memory 204660 kb
Host smart-be9f446a-877e-478c-a822-825fa11ee856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136142680 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3136142680
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.474611850
Short name T259
Test name
Test status
Simulation time 164798519 ps
CPU time 2.13 seconds
Started Oct 08 01:50:33 PM PDT 23
Finished Oct 08 01:50:35 PM PDT 23
Peak memory 205724 kb
Host smart-75e1927c-0a28-458d-a8bf-27e42b563649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474611850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.474611850
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3831892321
Short name T640
Test name
Test status
Simulation time 81171909121 ps
CPU time 1720.9 seconds
Started Oct 08 01:50:28 PM PDT 23
Finished Oct 08 02:19:11 PM PDT 23
Peak memory 219432 kb
Host smart-af460731-6b82-413d-9ea7-f3b283f0f107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831892321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3831892321
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.edn_alert.2476205021
Short name T637
Test name
Test status
Simulation time 32153773 ps
CPU time 0.98 seconds
Started Oct 08 01:54:28 PM PDT 23
Finished Oct 08 01:54:30 PM PDT 23
Peak memory 206244 kb
Host smart-c44651d8-e25a-45a7-9b79-6e69d530ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476205021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2476205021
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2223719508
Short name T600
Test name
Test status
Simulation time 59492070 ps
CPU time 0.91 seconds
Started Oct 08 01:54:28 PM PDT 23
Finished Oct 08 01:54:29 PM PDT 23
Peak memory 204716 kb
Host smart-4afee8d1-274b-44aa-bab7-4aaeb7a95575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223719508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2223719508
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3660090135
Short name T33
Test name
Test status
Simulation time 13919744 ps
CPU time 0.94 seconds
Started Oct 08 01:44:33 PM PDT 23
Finished Oct 08 01:44:34 PM PDT 23
Peak memory 214572 kb
Host smart-69401659-9d21-4bdb-8525-b5fd937831fc
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660090135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3660090135
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1628606098
Short name T711
Test name
Test status
Simulation time 127629431 ps
CPU time 1.03 seconds
Started Oct 08 01:46:11 PM PDT 23
Finished Oct 08 01:46:13 PM PDT 23
Peak memory 214724 kb
Host smart-20e864d1-8448-4859-81a7-38a235f2acee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628606098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1628606098
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.2619954972
Short name T70
Test name
Test status
Simulation time 58421861 ps
CPU time 0.94 seconds
Started Oct 08 01:54:28 PM PDT 23
Finished Oct 08 01:54:29 PM PDT 23
Peak memory 205244 kb
Host smart-2dd9cb09-cc1b-4892-9592-9317303ff540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619954972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2619954972
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1774415451
Short name T657
Test name
Test status
Simulation time 45830389 ps
CPU time 0.81 seconds
Started Oct 08 01:45:53 PM PDT 23
Finished Oct 08 01:45:54 PM PDT 23
Peak memory 214388 kb
Host smart-c555f56d-5a92-4028-85ff-cd8ec5523241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774415451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1774415451
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1979964834
Short name T525
Test name
Test status
Simulation time 13758674 ps
CPU time 0.87 seconds
Started Oct 08 01:51:11 PM PDT 23
Finished Oct 08 01:51:12 PM PDT 23
Peak memory 204988 kb
Host smart-ee30878a-1492-4e4c-ade3-13e37536b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979964834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1979964834
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.969534306
Short name T627
Test name
Test status
Simulation time 149082035 ps
CPU time 1.96 seconds
Started Oct 08 01:53:00 PM PDT 23
Finished Oct 08 01:53:02 PM PDT 23
Peak memory 205400 kb
Host smart-b03e7510-e736-4e59-a1ec-b93eb909d09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969534306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.969534306
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2656851922
Short name T650
Test name
Test status
Simulation time 108801603151 ps
CPU time 1170.86 seconds
Started Oct 08 01:42:45 PM PDT 23
Finished Oct 08 02:02:16 PM PDT 23
Peak memory 215876 kb
Host smart-48e3bbce-9d21-4497-8146-a2bf687a20ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656851922 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2656851922
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.106480013
Short name T80
Test name
Test status
Simulation time 27640430 ps
CPU time 0.97 seconds
Started Oct 08 01:48:25 PM PDT 23
Finished Oct 08 01:48:26 PM PDT 23
Peak memory 205248 kb
Host smart-918bce8c-8b13-4548-b4f5-ac3b4dd506d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106480013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.106480013
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4082219524
Short name T665
Test name
Test status
Simulation time 18946789 ps
CPU time 0.78 seconds
Started Oct 08 01:44:08 PM PDT 23
Finished Oct 08 01:44:09 PM PDT 23
Peak memory 204256 kb
Host smart-3f645b56-dde3-4294-9e7e-a3191ec6edf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082219524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4082219524
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.459552651
Short name T691
Test name
Test status
Simulation time 50416879 ps
CPU time 0.84 seconds
Started Oct 08 01:48:27 PM PDT 23
Finished Oct 08 01:48:28 PM PDT 23
Peak memory 214460 kb
Host smart-e649b201-e6cf-485a-b09b-e5fc84817c91
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459552651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.459552651
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.363211758
Short name T31
Test name
Test status
Simulation time 35907495 ps
CPU time 1.11 seconds
Started Oct 08 01:48:27 PM PDT 23
Finished Oct 08 01:48:29 PM PDT 23
Peak memory 214588 kb
Host smart-4f85c5ad-164c-4b8e-a092-82a147a1b2a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363211758 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.363211758
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3562658472
Short name T543
Test name
Test status
Simulation time 20638849 ps
CPU time 1.08 seconds
Started Oct 08 01:44:58 PM PDT 23
Finished Oct 08 01:44:59 PM PDT 23
Peak memory 221592 kb
Host smart-0c7ef379-009c-4cba-8fe2-7aa833bd44ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562658472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3562658472
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1196971016
Short name T282
Test name
Test status
Simulation time 17373306 ps
CPU time 1.11 seconds
Started Oct 08 01:49:18 PM PDT 23
Finished Oct 08 01:49:20 PM PDT 23
Peak memory 214488 kb
Host smart-c272afb8-d58c-49dc-bc49-8462925b8d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196971016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1196971016
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2548727619
Short name T322
Test name
Test status
Simulation time 19013949 ps
CPU time 1.09 seconds
Started Oct 08 01:44:46 PM PDT 23
Finished Oct 08 01:44:47 PM PDT 23
Peak memory 221496 kb
Host smart-8f4be108-df92-4251-9429-71072a27d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548727619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2548727619
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2559791871
Short name T513
Test name
Test status
Simulation time 12931902 ps
CPU time 0.85 seconds
Started Oct 08 01:46:31 PM PDT 23
Finished Oct 08 01:46:32 PM PDT 23
Peak memory 204664 kb
Host smart-e238aa6c-680a-4a03-bb6a-82b4896e30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559791871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2559791871
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3215452696
Short name T478
Test name
Test status
Simulation time 563529204 ps
CPU time 3.27 seconds
Started Oct 08 01:51:24 PM PDT 23
Finished Oct 08 01:51:28 PM PDT 23
Peak memory 205856 kb
Host smart-2d88f66e-9a33-478a-b02a-30c46c26d302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215452696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3215452696
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3090499210
Short name T458
Test name
Test status
Simulation time 80479072359 ps
CPU time 870.81 seconds
Started Oct 08 01:47:02 PM PDT 23
Finished Oct 08 02:01:33 PM PDT 23
Peak memory 215964 kb
Host smart-63f18217-c84e-401d-a9c5-63e756d59647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090499210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3090499210
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.1042200512
Short name T702
Test name
Test status
Simulation time 26779225 ps
CPU time 0.9 seconds
Started Oct 08 01:45:19 PM PDT 23
Finished Oct 08 01:45:20 PM PDT 23
Peak memory 206140 kb
Host smart-6930cba8-b7e3-49a4-af7d-6f7951d0ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042200512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1042200512
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.655309657
Short name T611
Test name
Test status
Simulation time 68135207 ps
CPU time 0.93 seconds
Started Oct 08 01:45:17 PM PDT 23
Finished Oct 08 01:45:18 PM PDT 23
Peak memory 205300 kb
Host smart-76a393b4-6861-4e27-bdb5-3b774d3eb89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655309657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.655309657
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2552978094
Short name T673
Test name
Test status
Simulation time 12727890 ps
CPU time 0.88 seconds
Started Oct 08 01:46:24 PM PDT 23
Finished Oct 08 01:46:25 PM PDT 23
Peak memory 214700 kb
Host smart-725754f2-5533-4bfc-81b4-8c936a245ffd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552978094 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2552978094
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.3797943861
Short name T188
Test name
Test status
Simulation time 231172869 ps
CPU time 1 seconds
Started Oct 08 01:47:25 PM PDT 23
Finished Oct 08 01:47:26 PM PDT 23
Peak memory 217060 kb
Host smart-696ed886-f449-4aa2-b4f1-0e72c53a6075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797943861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3797943861
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_intr.3344830619
Short name T106
Test name
Test status
Simulation time 92927850 ps
CPU time 0.79 seconds
Started Oct 08 01:45:00 PM PDT 23
Finished Oct 08 01:45:01 PM PDT 23
Peak memory 214572 kb
Host smart-627cf0b9-b6b1-4950-b3e4-eb12e05889a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344830619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3344830619
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.951099193
Short name T529
Test name
Test status
Simulation time 19140292 ps
CPU time 0.88 seconds
Started Oct 08 01:48:02 PM PDT 23
Finished Oct 08 01:48:03 PM PDT 23
Peak memory 204688 kb
Host smart-c77f1b20-aaa0-4e20-8f03-b26384a428e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951099193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.951099193
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2117885518
Short name T676
Test name
Test status
Simulation time 38779978 ps
CPU time 1.25 seconds
Started Oct 08 01:42:54 PM PDT 23
Finished Oct 08 01:42:55 PM PDT 23
Peak memory 205256 kb
Host smart-7a978cd5-e9d1-4b88-858f-bc2d59fd4e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117885518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2117885518
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2232714200
Short name T683
Test name
Test status
Simulation time 65357302197 ps
CPU time 706.06 seconds
Started Oct 08 01:47:25 PM PDT 23
Finished Oct 08 01:59:12 PM PDT 23
Peak memory 216064 kb
Host smart-255eb8f8-77d4-4bf3-a306-6176824e5864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232714200 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2232714200
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_alert.3401117040
Short name T255
Test name
Test status
Simulation time 135333090 ps
CPU time 0.99 seconds
Started Oct 08 01:47:03 PM PDT 23
Finished Oct 08 01:47:05 PM PDT 23
Peak memory 205228 kb
Host smart-82fa9ee0-ee55-463f-b9c6-83082503b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401117040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3401117040
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1028188282
Short name T473
Test name
Test status
Simulation time 21591814 ps
CPU time 0.79 seconds
Started Oct 08 01:43:52 PM PDT 23
Finished Oct 08 01:43:53 PM PDT 23
Peak memory 204928 kb
Host smart-d1926121-d521-48d9-839f-a2c6c5aeabd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028188282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1028188282
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.402621281
Short name T196
Test name
Test status
Simulation time 13338933 ps
CPU time 0.89 seconds
Started Oct 08 01:43:34 PM PDT 23
Finished Oct 08 01:43:35 PM PDT 23
Peak memory 214496 kb
Host smart-eca5b178-0ec1-4941-bb48-3285c276e1ee
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402621281 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.402621281
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1182115925
Short name T639
Test name
Test status
Simulation time 29271637 ps
CPU time 1.13 seconds
Started Oct 08 01:41:07 PM PDT 23
Finished Oct 08 01:41:08 PM PDT 23
Peak memory 214596 kb
Host smart-308af23e-8752-47fe-a162-d78951a351f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182115925 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1182115925
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1409555746
Short name T663
Test name
Test status
Simulation time 19386484 ps
CPU time 1.11 seconds
Started Oct 08 01:43:13 PM PDT 23
Finished Oct 08 01:43:14 PM PDT 23
Peak memory 215576 kb
Host smart-cc5ca684-172d-47ca-804a-d037120d43e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409555746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1409555746
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3199983312
Short name T12
Test name
Test status
Simulation time 21451164 ps
CPU time 1.12 seconds
Started Oct 08 01:48:23 PM PDT 23
Finished Oct 08 01:48:25 PM PDT 23
Peak memory 214452 kb
Host smart-c778943d-52ec-4079-94d8-1a12938049dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199983312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3199983312
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2621158270
Short name T599
Test name
Test status
Simulation time 18609691 ps
CPU time 1.05 seconds
Started Oct 08 01:42:50 PM PDT 23
Finished Oct 08 01:42:53 PM PDT 23
Peak memory 214828 kb
Host smart-dadba8e0-1481-49fd-ba50-773ea8f8655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621158270 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2621158270
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.491185476
Short name T636
Test name
Test status
Simulation time 17259507 ps
CPU time 0.84 seconds
Started Oct 08 01:49:10 PM PDT 23
Finished Oct 08 01:49:11 PM PDT 23
Peak memory 204884 kb
Host smart-9241aef2-584c-4368-9a57-0d894ea99862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491185476 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.491185476
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3813382535
Short name T484
Test name
Test status
Simulation time 388143706 ps
CPU time 1.41 seconds
Started Oct 08 01:53:48 PM PDT 23
Finished Oct 08 01:53:49 PM PDT 23
Peak memory 205592 kb
Host smart-264f5d3c-a0e4-43df-946d-0316780d0267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813382535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3813382535
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2405001799
Short name T469
Test name
Test status
Simulation time 41350653464 ps
CPU time 902.98 seconds
Started Oct 08 01:45:33 PM PDT 23
Finished Oct 08 02:00:37 PM PDT 23
Peak memory 215924 kb
Host smart-f75c0e16-1d95-483f-9133-0e8753ba08b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405001799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2405001799
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1594263839
Short name T29
Test name
Test status
Simulation time 34551309 ps
CPU time 0.98 seconds
Started Oct 08 01:47:29 PM PDT 23
Finished Oct 08 01:47:30 PM PDT 23
Peak memory 205340 kb
Host smart-06956236-03ac-4add-ab0e-df7a22b63066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594263839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1594263839
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.516695361
Short name T662
Test name
Test status
Simulation time 31952508 ps
CPU time 0.78 seconds
Started Oct 08 01:48:28 PM PDT 23
Finished Oct 08 01:48:29 PM PDT 23
Peak memory 204324 kb
Host smart-0de98e37-5883-4fe0-9c7a-748ca3aabfa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516695361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.516695361
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3638123749
Short name T207
Test name
Test status
Simulation time 20603597 ps
CPU time 0.81 seconds
Started Oct 08 01:43:26 PM PDT 23
Finished Oct 08 01:43:27 PM PDT 23
Peak memory 214364 kb
Host smart-a06c9d44-5803-44dd-a92c-d011be9995ba
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638123749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3638123749
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2581500722
Short name T276
Test name
Test status
Simulation time 159131670 ps
CPU time 0.98 seconds
Started Oct 08 01:48:26 PM PDT 23
Finished Oct 08 01:48:27 PM PDT 23
Peak memory 214648 kb
Host smart-d5a7be71-e546-428f-a58c-dcf44797547b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581500722 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2581500722
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2100894394
Short name T608
Test name
Test status
Simulation time 52533352 ps
CPU time 0.93 seconds
Started Oct 08 01:43:02 PM PDT 23
Finished Oct 08 01:43:03 PM PDT 23
Peak memory 221296 kb
Host smart-69923a39-8d50-4441-9ed8-895d26f34b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100894394 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2100894394
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3683768763
Short name T695
Test name
Test status
Simulation time 54151330 ps
CPU time 0.94 seconds
Started Oct 08 01:47:25 PM PDT 23
Finished Oct 08 01:47:26 PM PDT 23
Peak memory 204992 kb
Host smart-f22fd9e8-fcaf-40dc-a5ba-d8ad464462be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683768763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3683768763
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3297354933
Short name T487
Test name
Test status
Simulation time 23156731 ps
CPU time 0.93 seconds
Started Oct 08 01:47:11 PM PDT 23
Finished Oct 08 01:47:12 PM PDT 23
Peak memory 214612 kb
Host smart-cc671722-11bf-46f3-9bae-25bdb04a9af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297354933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3297354933
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3469352288
Short name T300
Test name
Test status
Simulation time 21959879 ps
CPU time 0.85 seconds
Started Oct 08 01:50:35 PM PDT 23
Finished Oct 08 01:50:36 PM PDT 23
Peak memory 204928 kb
Host smart-9ca8913a-3c0b-4591-b439-c9109eb24c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469352288 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3469352288
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1196869273
Short name T495
Test name
Test status
Simulation time 838131138 ps
CPU time 1.85 seconds
Started Oct 08 01:50:59 PM PDT 23
Finished Oct 08 01:51:01 PM PDT 23
Peak memory 206112 kb
Host smart-076e3ecd-4f15-4cd5-9700-6b8886bd141e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196869273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1196869273
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2638873840
Short name T477
Test name
Test status
Simulation time 190668035197 ps
CPU time 516.8 seconds
Started Oct 08 01:53:48 PM PDT 23
Finished Oct 08 02:02:25 PM PDT 23
Peak memory 214680 kb
Host smart-4816c21d-ee43-4198-9d0b-28b8add64c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638873840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2638873840
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.1664826430
Short name T541
Test name
Test status
Simulation time 19200558 ps
CPU time 0.8 seconds
Started Oct 08 01:43:05 PM PDT 23
Finished Oct 08 01:43:06 PM PDT 23
Peak memory 204368 kb
Host smart-74c44128-4bae-47f4-b362-bf0c7d4be7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664826430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1664826430
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4200027586
Short name T722
Test name
Test status
Simulation time 103875347 ps
CPU time 1.01 seconds
Started Oct 08 01:45:15 PM PDT 23
Finished Oct 08 01:45:16 PM PDT 23
Peak memory 214808 kb
Host smart-102b669e-59fe-430e-b12a-b5ff6558acdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200027586 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4200027586
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1097719165
Short name T193
Test name
Test status
Simulation time 35629978 ps
CPU time 0.85 seconds
Started Oct 08 01:43:04 PM PDT 23
Finished Oct 08 01:43:05 PM PDT 23
Peak memory 215252 kb
Host smart-c70bef39-e8da-481b-9bf7-0ec1028dcb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097719165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1097719165
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4196486253
Short name T270
Test name
Test status
Simulation time 319700600 ps
CPU time 1.22 seconds
Started Oct 08 01:45:56 PM PDT 23
Finished Oct 08 01:45:58 PM PDT 23
Peak memory 214396 kb
Host smart-0f7e3da5-1b6f-4b1d-8694-a9631ef005df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196486253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4196486253
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3672739507
Short name T545
Test name
Test status
Simulation time 18942355 ps
CPU time 1.14 seconds
Started Oct 08 01:50:10 PM PDT 23
Finished Oct 08 01:50:11 PM PDT 23
Peak memory 221624 kb
Host smart-4516e537-61a8-485b-a66e-3750e695aa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672739507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3672739507
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.4245653878
Short name T698
Test name
Test status
Simulation time 14515244 ps
CPU time 0.91 seconds
Started Oct 08 01:50:34 PM PDT 23
Finished Oct 08 01:50:35 PM PDT 23
Peak memory 204944 kb
Host smart-43e1bfa2-d096-48c3-969f-1ac4189afec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245653878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.4245653878
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2294915378
Short name T508
Test name
Test status
Simulation time 38246597 ps
CPU time 1.29 seconds
Started Oct 08 01:44:20 PM PDT 23
Finished Oct 08 01:44:22 PM PDT 23
Peak memory 205496 kb
Host smart-fdc6925b-1236-49e4-a9fe-9303936842bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294915378 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2294915378
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2483688745
Short name T115
Test name
Test status
Simulation time 418748324874 ps
CPU time 735.49 seconds
Started Oct 08 01:43:02 PM PDT 23
Finished Oct 08 01:55:18 PM PDT 23
Peak memory 214656 kb
Host smart-953aa683-cc27-4032-824d-7d7dadfee288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483688745 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2483688745
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.333412063
Short name T557
Test name
Test status
Simulation time 54852451 ps
CPU time 0.92 seconds
Started Oct 08 01:48:09 PM PDT 23
Finished Oct 08 01:48:10 PM PDT 23
Peak memory 205132 kb
Host smart-5ef69892-a46e-494f-9cc7-d82c9dfe634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333412063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.333412063
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.577429155
Short name T587
Test name
Test status
Simulation time 13268347 ps
CPU time 0.83 seconds
Started Oct 08 01:49:09 PM PDT 23
Finished Oct 08 01:49:10 PM PDT 23
Peak memory 204472 kb
Host smart-f7da64e2-9442-4d09-90f0-49a51bb8bb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577429155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.577429155
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.729827780
Short name T102
Test name
Test status
Simulation time 37034221 ps
CPU time 0.81 seconds
Started Oct 08 01:44:25 PM PDT 23
Finished Oct 08 01:44:26 PM PDT 23
Peak memory 214288 kb
Host smart-9ea9c490-ac82-4727-ab7d-07c8513cf34f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729827780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.729827780
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1951864053
Short name T688
Test name
Test status
Simulation time 22178701 ps
CPU time 0.96 seconds
Started Oct 08 01:47:30 PM PDT 23
Finished Oct 08 01:47:31 PM PDT 23
Peak memory 214772 kb
Host smart-5e426afa-92b4-4b11-8608-b880e1559fc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951864053 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1951864053
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4107454407
Short name T550
Test name
Test status
Simulation time 19397501 ps
CPU time 1.41 seconds
Started Oct 08 01:55:56 PM PDT 23
Finished Oct 08 01:55:57 PM PDT 23
Peak memory 216116 kb
Host smart-f52e5329-37fd-4eda-b6b0-c0f9792cf03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107454407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4107454407
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3437187925
Short name T121
Test name
Test status
Simulation time 124271019 ps
CPU time 1.05 seconds
Started Oct 08 01:44:49 PM PDT 23
Finished Oct 08 01:44:51 PM PDT 23
Peak memory 205048 kb
Host smart-9383cda9-c56c-43f0-8762-bd2ad4c6a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437187925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3437187925
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3693532660
Short name T697
Test name
Test status
Simulation time 36243607 ps
CPU time 0.98 seconds
Started Oct 08 01:43:16 PM PDT 23
Finished Oct 08 01:43:17 PM PDT 23
Peak memory 221432 kb
Host smart-d703b3be-40a2-4bb0-8d2d-910a98c535c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693532660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3693532660
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1767654633
Short name T696
Test name
Test status
Simulation time 29507299 ps
CPU time 0.86 seconds
Started Oct 08 01:50:25 PM PDT 23
Finished Oct 08 01:50:31 PM PDT 23
Peak memory 204632 kb
Host smart-799fb7f5-9ade-43c3-96dc-427470097d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767654633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1767654633
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1691782437
Short name T591
Test name
Test status
Simulation time 144805998 ps
CPU time 1.19 seconds
Started Oct 08 01:46:44 PM PDT 23
Finished Oct 08 01:46:45 PM PDT 23
Peak memory 205320 kb
Host smart-08340f6f-54f8-491f-861c-1e277c9bfcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691782437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1691782437
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2358411793
Short name T122
Test name
Test status
Simulation time 43853461211 ps
CPU time 1095.4 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 02:04:00 PM PDT 23
Peak memory 215444 kb
Host smart-2148abda-9480-4f29-9b47-77ece9e0bc84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358411793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2358411793
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2785365503
Short name T615
Test name
Test status
Simulation time 17037930 ps
CPU time 0.99 seconds
Started Oct 08 01:55:54 PM PDT 23
Finished Oct 08 01:55:55 PM PDT 23
Peak memory 206180 kb
Host smart-4a0bdc8d-35ef-4b15-af9f-ee46a340bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785365503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2785365503
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2397497392
Short name T505
Test name
Test status
Simulation time 20862886 ps
CPU time 0.94 seconds
Started Oct 08 01:45:25 PM PDT 23
Finished Oct 08 01:45:26 PM PDT 23
Peak memory 204596 kb
Host smart-c8582585-0bbc-4067-8089-50b880f5c571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397497392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2397497392
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.1973660861
Short name T232
Test name
Test status
Simulation time 42902327 ps
CPU time 0.93 seconds
Started Oct 08 01:52:11 PM PDT 23
Finished Oct 08 01:52:12 PM PDT 23
Peak memory 214524 kb
Host smart-cdb89e69-f830-4247-8a26-43c8d2d26b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973660861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1973660861
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2153099625
Short name T38
Test name
Test status
Simulation time 14390664 ps
CPU time 0.97 seconds
Started Oct 08 01:45:43 PM PDT 23
Finished Oct 08 01:45:44 PM PDT 23
Peak memory 205168 kb
Host smart-c1719781-d5b9-42da-898e-0c324aa944b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153099625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2153099625
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1645601842
Short name T110
Test name
Test status
Simulation time 68984458 ps
CPU time 0.91 seconds
Started Oct 08 01:52:10 PM PDT 23
Finished Oct 08 01:52:11 PM PDT 23
Peak memory 224596 kb
Host smart-477f099b-f36e-488d-ac09-7d7032938846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645601842 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1645601842
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1983747279
Short name T559
Test name
Test status
Simulation time 22126427 ps
CPU time 0.84 seconds
Started Oct 08 01:53:03 PM PDT 23
Finished Oct 08 01:53:04 PM PDT 23
Peak memory 204640 kb
Host smart-f0b85d0d-5347-407c-abbd-41a54ed3c729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983747279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1983747279
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2772693185
Short name T316
Test name
Test status
Simulation time 63659569 ps
CPU time 1.89 seconds
Started Oct 08 01:49:11 PM PDT 23
Finished Oct 08 01:49:13 PM PDT 23
Peak memory 206132 kb
Host smart-4258baa3-da6f-4167-8f1a-e6ff4449aeea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772693185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2772693185
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2987520270
Short name T656
Test name
Test status
Simulation time 70069390967 ps
CPU time 822.9 seconds
Started Oct 08 01:45:42 PM PDT 23
Finished Oct 08 01:59:25 PM PDT 23
Peak memory 215192 kb
Host smart-3d8dd7a2-b2db-41d7-8f1a-56a74a112bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987520270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2987520270
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2102897317
Short name T664
Test name
Test status
Simulation time 67259773 ps
CPU time 0.98 seconds
Started Oct 08 01:46:43 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 205248 kb
Host smart-f85798f6-53a1-4d60-9b81-7f5bf69f1bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102897317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2102897317
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2815601176
Short name T583
Test name
Test status
Simulation time 44244773 ps
CPU time 0.85 seconds
Started Oct 08 01:44:23 PM PDT 23
Finished Oct 08 01:44:24 PM PDT 23
Peak memory 204556 kb
Host smart-21c77cc3-8361-416c-9c67-4f0a6212040f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815601176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2815601176
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1884505794
Short name T134
Test name
Test status
Simulation time 21787626 ps
CPU time 0.89 seconds
Started Oct 08 01:52:37 PM PDT 23
Finished Oct 08 01:52:38 PM PDT 23
Peak memory 214564 kb
Host smart-d363c697-5204-45b5-b18a-78010b87a39c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884505794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1884505794
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1294121584
Short name T716
Test name
Test status
Simulation time 118868520 ps
CPU time 1.03 seconds
Started Oct 08 01:49:19 PM PDT 23
Finished Oct 08 01:49:20 PM PDT 23
Peak memory 214712 kb
Host smart-160ae13a-b843-4bd8-ae10-79ae6b8d635b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294121584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1294121584
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.845184455
Short name T5
Test name
Test status
Simulation time 26035419 ps
CPU time 1.01 seconds
Started Oct 08 01:45:14 PM PDT 23
Finished Oct 08 01:45:15 PM PDT 23
Peak memory 214584 kb
Host smart-45612c69-ddf3-4d35-877c-fa1560dcd5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845184455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.845184455
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1471735148
Short name T660
Test name
Test status
Simulation time 80123425 ps
CPU time 1.04 seconds
Started Oct 08 01:45:27 PM PDT 23
Finished Oct 08 01:45:29 PM PDT 23
Peak memory 214296 kb
Host smart-12ba865d-c5d0-4cda-be83-63e7eedc710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471735148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1471735148
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1895038806
Short name T462
Test name
Test status
Simulation time 39227657 ps
CPU time 0.85 seconds
Started Oct 08 01:44:18 PM PDT 23
Finished Oct 08 01:44:19 PM PDT 23
Peak memory 214296 kb
Host smart-1eeb7dd3-19fc-43bc-b2df-19f128967dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895038806 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1895038806
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3471165715
Short name T554
Test name
Test status
Simulation time 41740683 ps
CPU time 0.86 seconds
Started Oct 08 01:44:21 PM PDT 23
Finished Oct 08 01:44:22 PM PDT 23
Peak memory 204636 kb
Host smart-a953d1e9-4bae-4ed8-9048-ebd03400ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471165715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3471165715
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4041424867
Short name T612
Test name
Test status
Simulation time 322080615 ps
CPU time 3.65 seconds
Started Oct 08 01:52:28 PM PDT 23
Finished Oct 08 01:52:31 PM PDT 23
Peak memory 205904 kb
Host smart-9332e044-2f5f-43a3-9b61-17818078d2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041424867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4041424867
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.124900281
Short name T141
Test name
Test status
Simulation time 37060627342 ps
CPU time 307.19 seconds
Started Oct 08 01:45:28 PM PDT 23
Finished Oct 08 01:50:35 PM PDT 23
Peak memory 214636 kb
Host smart-13246c51-ecd9-4801-a069-51ea70f1c7c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124900281 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.124900281
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.106030247
Short name T684
Test name
Test status
Simulation time 66732815 ps
CPU time 0.97 seconds
Started Oct 08 01:44:21 PM PDT 23
Finished Oct 08 01:44:23 PM PDT 23
Peak memory 205016 kb
Host smart-e624a08c-f56a-4d72-980e-1fd999bc9875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106030247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.106030247
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.934045945
Short name T654
Test name
Test status
Simulation time 27916409 ps
CPU time 0.91 seconds
Started Oct 08 01:52:43 PM PDT 23
Finished Oct 08 01:52:44 PM PDT 23
Peak memory 205316 kb
Host smart-c3240084-12da-406b-a99c-bba10eadb35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934045945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.934045945
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2259326757
Short name T133
Test name
Test status
Simulation time 14432434 ps
CPU time 0.81 seconds
Started Oct 08 03:13:36 PM PDT 23
Finished Oct 08 03:13:37 PM PDT 23
Peak memory 214400 kb
Host smart-0e656ad8-5622-48f6-8e9c-b80322132f10
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259326757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2259326757
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1451357065
Short name T175
Test name
Test status
Simulation time 73792732 ps
CPU time 0.99 seconds
Started Oct 08 01:52:44 PM PDT 23
Finished Oct 08 01:52:45 PM PDT 23
Peak memory 214764 kb
Host smart-4afb5118-f3ff-4b92-a124-eee4f390369d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451357065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1451357065
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1856590257
Short name T126
Test name
Test status
Simulation time 91339046 ps
CPU time 1.15 seconds
Started Oct 08 01:43:53 PM PDT 23
Finished Oct 08 01:43:55 PM PDT 23
Peak memory 214724 kb
Host smart-3d227d1d-50a8-42a3-8148-a33a27b2a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856590257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1856590257
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.834528142
Short name T44
Test name
Test status
Simulation time 39323402 ps
CPU time 1.13 seconds
Started Oct 08 01:45:00 PM PDT 23
Finished Oct 08 01:45:01 PM PDT 23
Peak memory 205468 kb
Host smart-5cf6a522-d837-4944-a5b3-54a75e2f2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834528142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.834528142
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1265445917
Short name T324
Test name
Test status
Simulation time 30201803 ps
CPU time 0.86 seconds
Started Oct 08 01:45:01 PM PDT 23
Finished Oct 08 01:45:02 PM PDT 23
Peak memory 214516 kb
Host smart-694d1bee-858c-4d38-a8e2-bff2976fa49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265445917 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1265445917
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3528530719
Short name T302
Test name
Test status
Simulation time 14342241 ps
CPU time 0.93 seconds
Started Oct 08 01:45:25 PM PDT 23
Finished Oct 08 01:45:26 PM PDT 23
Peak memory 204616 kb
Host smart-fa340725-0340-48cf-afaa-2e282f27e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528530719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3528530719
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.737878249
Short name T571
Test name
Test status
Simulation time 60813545 ps
CPU time 1.15 seconds
Started Oct 08 01:49:03 PM PDT 23
Finished Oct 08 01:49:05 PM PDT 23
Peak memory 204980 kb
Host smart-716b035e-a6ab-49be-9214-e7f9aca01ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737878249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.737878249
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1466318766
Short name T143
Test name
Test status
Simulation time 147063242415 ps
CPU time 1622.2 seconds
Started Oct 08 01:45:54 PM PDT 23
Finished Oct 08 02:12:57 PM PDT 23
Peak memory 218396 kb
Host smart-dd2355e5-a76a-4f6a-902e-d7d715058c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466318766 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1466318766
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4196521133
Short name T471
Test name
Test status
Simulation time 39633288 ps
CPU time 0.99 seconds
Started Oct 08 01:44:32 PM PDT 23
Finished Oct 08 01:44:33 PM PDT 23
Peak memory 205148 kb
Host smart-71de432a-1873-4dc4-90a6-baf15ae4e857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196521133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4196521133
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1104989063
Short name T298
Test name
Test status
Simulation time 18849220 ps
CPU time 0.78 seconds
Started Oct 08 01:50:12 PM PDT 23
Finished Oct 08 01:50:13 PM PDT 23
Peak memory 204368 kb
Host smart-0eff0534-0409-4843-9969-b76fdf02dc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104989063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1104989063
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3270585040
Short name T644
Test name
Test status
Simulation time 18556747 ps
CPU time 0.81 seconds
Started Oct 08 02:46:11 PM PDT 23
Finished Oct 08 02:46:12 PM PDT 23
Peak memory 214516 kb
Host smart-d249547b-7110-4d79-a8d7-9b0164c057f3
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270585040 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3270585040
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2343466928
Short name T631
Test name
Test status
Simulation time 44581070 ps
CPU time 0.97 seconds
Started Oct 08 02:07:55 PM PDT 23
Finished Oct 08 02:07:56 PM PDT 23
Peak memory 214640 kb
Host smart-49dd3f32-3508-47e5-8cc5-5b34f464e5e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343466928 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2343466928
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3581099272
Short name T179
Test name
Test status
Simulation time 35597569 ps
CPU time 0.93 seconds
Started Oct 08 01:43:25 PM PDT 23
Finished Oct 08 01:43:26 PM PDT 23
Peak memory 214516 kb
Host smart-65e88092-4713-4c51-8e8c-11e991d8dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581099272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3581099272
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3383558722
Short name T94
Test name
Test status
Simulation time 89756375 ps
CPU time 1.25 seconds
Started Oct 08 01:44:36 PM PDT 23
Finished Oct 08 01:44:37 PM PDT 23
Peak memory 214412 kb
Host smart-1febb59c-bfff-46ad-8fb4-eae0fa2f3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383558722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3383558722
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2979453184
Short name T579
Test name
Test status
Simulation time 24219330 ps
CPU time 0.93 seconds
Started Oct 08 01:43:18 PM PDT 23
Finished Oct 08 01:43:19 PM PDT 23
Peak memory 214764 kb
Host smart-a96d29f9-5bcb-49a9-84c5-c1744ff847bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979453184 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2979453184
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.462254053
Short name T305
Test name
Test status
Simulation time 13243799 ps
CPU time 0.99 seconds
Started Oct 08 03:53:47 PM PDT 23
Finished Oct 08 03:53:48 PM PDT 23
Peak memory 204736 kb
Host smart-7adf538e-2461-4573-bd8c-4121699477aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462254053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.462254053
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.604253555
Short name T269
Test name
Test status
Simulation time 2341257278 ps
CPU time 3.95 seconds
Started Oct 08 02:19:16 PM PDT 23
Finished Oct 08 02:19:20 PM PDT 23
Peak memory 206280 kb
Host smart-cdeac8fb-f98e-407d-80b3-992e86b9a7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604253555 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.604253555
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3851087986
Short name T139
Test name
Test status
Simulation time 157252314605 ps
CPU time 1025.07 seconds
Started Oct 08 02:29:18 PM PDT 23
Finished Oct 08 02:46:23 PM PDT 23
Peak memory 217504 kb
Host smart-5dccd24c-e676-4174-9c89-94efc582677f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851087986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3851087986
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1821946800
Short name T293
Test name
Test status
Simulation time 20819084 ps
CPU time 0.99 seconds
Started Oct 08 01:45:22 PM PDT 23
Finished Oct 08 01:45:23 PM PDT 23
Peak memory 205224 kb
Host smart-9ff216dc-0ad6-4894-9ea4-2c11f64126c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821946800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1821946800
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3942707653
Short name T522
Test name
Test status
Simulation time 56232030 ps
CPU time 0.93 seconds
Started Oct 08 01:56:20 PM PDT 23
Finished Oct 08 01:56:21 PM PDT 23
Peak memory 204656 kb
Host smart-1ba76621-e12c-49b1-bd74-2b455354219f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942707653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3942707653
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2502509731
Short name T187
Test name
Test status
Simulation time 16495948 ps
CPU time 0.81 seconds
Started Oct 08 01:48:51 PM PDT 23
Finished Oct 08 01:48:52 PM PDT 23
Peak memory 214472 kb
Host smart-6484249a-a342-495f-87f2-ed375ed9ec64
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502509731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2502509731
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3599744438
Short name T609
Test name
Test status
Simulation time 36946225 ps
CPU time 1.03 seconds
Started Oct 08 03:14:36 PM PDT 23
Finished Oct 08 03:14:38 PM PDT 23
Peak memory 214800 kb
Host smart-ffd95c71-9679-4ced-9bdc-321a9bd78998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599744438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3599744438
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1011477040
Short name T171
Test name
Test status
Simulation time 57121383 ps
CPU time 0.98 seconds
Started Oct 08 01:50:12 PM PDT 23
Finished Oct 08 01:50:13 PM PDT 23
Peak memory 214572 kb
Host smart-733a4c9b-83e2-463f-8942-6e7ca81d8188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011477040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1011477040
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2930560000
Short name T65
Test name
Test status
Simulation time 23608876 ps
CPU time 1.2 seconds
Started Oct 08 01:48:52 PM PDT 23
Finished Oct 08 01:48:53 PM PDT 23
Peak memory 214516 kb
Host smart-a4ceebe1-df7b-41df-841c-edcd1af16785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930560000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2930560000
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3305675528
Short name T496
Test name
Test status
Simulation time 19737271 ps
CPU time 1.02 seconds
Started Oct 08 02:50:33 PM PDT 23
Finished Oct 08 02:50:34 PM PDT 23
Peak memory 214420 kb
Host smart-4989cd28-55c9-4974-95e9-529021f5d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305675528 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3305675528
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.708510475
Short name T208
Test name
Test status
Simulation time 16458380 ps
CPU time 0.92 seconds
Started Oct 08 02:23:54 PM PDT 23
Finished Oct 08 02:23:55 PM PDT 23
Peak memory 205236 kb
Host smart-57ca05d0-651b-432f-b2e7-f7a39f51b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708510475 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.708510475
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3002363217
Short name T521
Test name
Test status
Simulation time 114362467 ps
CPU time 1.8 seconds
Started Oct 08 01:45:17 PM PDT 23
Finished Oct 08 01:45:19 PM PDT 23
Peak memory 205664 kb
Host smart-b330b6c5-c361-4821-906c-2aa4bbeee278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002363217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3002363217
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2159996725
Short name T649
Test name
Test status
Simulation time 69536399989 ps
CPU time 1590.17 seconds
Started Oct 08 01:50:00 PM PDT 23
Finished Oct 08 02:16:31 PM PDT 23
Peak memory 218120 kb
Host smart-475af9aa-7cfd-4053-9ce2-f80ad886503e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159996725 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2159996725
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3833576861
Short name T562
Test name
Test status
Simulation time 44178634 ps
CPU time 0.97 seconds
Started Oct 08 01:44:31 PM PDT 23
Finished Oct 08 01:44:32 PM PDT 23
Peak memory 205268 kb
Host smart-b9805bad-9ef8-4b41-81f7-f4b454777578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833576861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3833576861
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.82057897
Short name T572
Test name
Test status
Simulation time 21885867 ps
CPU time 0.86 seconds
Started Oct 08 01:44:19 PM PDT 23
Finished Oct 08 01:44:20 PM PDT 23
Peak memory 205244 kb
Host smart-768b157e-aa61-4801-8a3c-8736344c3ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82057897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.82057897
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4290735525
Short name T186
Test name
Test status
Simulation time 19713451 ps
CPU time 0.82 seconds
Started Oct 08 01:45:52 PM PDT 23
Finished Oct 08 01:45:53 PM PDT 23
Peak memory 214444 kb
Host smart-f8de8f76-1847-468f-84fe-5b2fc07e3b6c
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290735525 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4290735525
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1242186153
Short name T669
Test name
Test status
Simulation time 26631029 ps
CPU time 1.16 seconds
Started Oct 08 01:44:20 PM PDT 23
Finished Oct 08 01:44:22 PM PDT 23
Peak memory 214700 kb
Host smart-e3b38d9d-8558-4f72-94b1-89fb1be4765b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242186153 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1242186153
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.568251937
Short name T169
Test name
Test status
Simulation time 19204078 ps
CPU time 1.1 seconds
Started Oct 08 02:17:09 PM PDT 23
Finished Oct 08 02:17:10 PM PDT 23
Peak memory 214620 kb
Host smart-495212f0-3e0d-45a5-b7dd-fbc27d31708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568251937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.568251937
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.141615702
Short name T40
Test name
Test status
Simulation time 66741628 ps
CPU time 1.24 seconds
Started Oct 08 02:24:23 PM PDT 23
Finished Oct 08 02:24:27 PM PDT 23
Peak memory 204224 kb
Host smart-90067c2d-00f4-4e94-9b07-184111112824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141615702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.141615702
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1141012828
Short name T667
Test name
Test status
Simulation time 93022502 ps
CPU time 0.93 seconds
Started Oct 08 01:44:18 PM PDT 23
Finished Oct 08 01:44:19 PM PDT 23
Peak memory 221484 kb
Host smart-a3028f80-f008-4931-8681-4d40cac2b581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141012828 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1141012828
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3734475933
Short name T98
Test name
Test status
Simulation time 29397063 ps
CPU time 0.94 seconds
Started Oct 08 03:03:08 PM PDT 23
Finished Oct 08 03:03:09 PM PDT 23
Peak memory 205128 kb
Host smart-bcd84dd2-5ee7-4e19-925b-7a349f89106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734475933 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3734475933
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.49449338
Short name T475
Test name
Test status
Simulation time 712137146 ps
CPU time 4.07 seconds
Started Oct 08 03:07:21 PM PDT 23
Finished Oct 08 03:07:26 PM PDT 23
Peak memory 206132 kb
Host smart-bc2f9e3a-53c6-4c05-b157-da858582b375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49449338 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.49449338
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.407023012
Short name T598
Test name
Test status
Simulation time 383189187199 ps
CPU time 2078.42 seconds
Started Oct 08 01:48:10 PM PDT 23
Finished Oct 08 02:22:49 PM PDT 23
Peak memory 220592 kb
Host smart-18402c5f-6f61-4a16-a40e-f4ab0e8d37e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407023012 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.407023012
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4215026202
Short name T34
Test name
Test status
Simulation time 63499860 ps
CPU time 0.97 seconds
Started Oct 08 03:28:22 PM PDT 23
Finished Oct 08 03:28:23 PM PDT 23
Peak memory 206156 kb
Host smart-27bcc5e1-afa3-4cfa-be8d-90e55b547db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215026202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4215026202
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3471365565
Short name T151
Test name
Test status
Simulation time 58202108 ps
CPU time 0.9 seconds
Started Oct 08 03:20:08 PM PDT 23
Finished Oct 08 03:20:09 PM PDT 23
Peak memory 205336 kb
Host smart-6828e21a-8c3b-4c56-94e6-0fbf9b9c5a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471365565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3471365565
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.139533530
Short name T95
Test name
Test status
Simulation time 39192773 ps
CPU time 0.83 seconds
Started Oct 08 01:46:52 PM PDT 23
Finished Oct 08 01:46:53 PM PDT 23
Peak memory 214468 kb
Host smart-f63e5974-f97a-4d6a-9f92-a5e37ffb9dab
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139533530 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.139533530
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2165356647
Short name T83
Test name
Test status
Simulation time 134690714 ps
CPU time 0.97 seconds
Started Oct 08 02:45:28 PM PDT 23
Finished Oct 08 02:45:29 PM PDT 23
Peak memory 214688 kb
Host smart-2db3fa6b-5d3e-4b2f-8b62-730f7b56af9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165356647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2165356647
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.356353548
Short name T167
Test name
Test status
Simulation time 92343473 ps
CPU time 1.01 seconds
Started Oct 08 01:47:35 PM PDT 23
Finished Oct 08 01:47:36 PM PDT 23
Peak memory 214524 kb
Host smart-28d7f75f-19d7-4aab-bb2c-0a2d7a0d5580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356353548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.356353548
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3137757690
Short name T537
Test name
Test status
Simulation time 59440550 ps
CPU time 0.93 seconds
Started Oct 08 02:47:13 PM PDT 23
Finished Oct 08 02:47:14 PM PDT 23
Peak memory 205072 kb
Host smart-a36c09c9-a3c6-433f-960f-f3ee5eba7687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137757690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3137757690
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.727621865
Short name T534
Test name
Test status
Simulation time 19354552 ps
CPU time 1.04 seconds
Started Oct 08 02:41:43 PM PDT 23
Finished Oct 08 02:41:45 PM PDT 23
Peak memory 214776 kb
Host smart-8492978d-e722-44d4-83b5-497052e89ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727621865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.727621865
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1261179393
Short name T306
Test name
Test status
Simulation time 43151881 ps
CPU time 0.82 seconds
Started Oct 08 01:48:09 PM PDT 23
Finished Oct 08 01:48:10 PM PDT 23
Peak memory 204660 kb
Host smart-78e8f89b-0eaf-4f01-b84f-60cd0f9150ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261179393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1261179393
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1793248693
Short name T528
Test name
Test status
Simulation time 154968828 ps
CPU time 2.77 seconds
Started Oct 08 03:05:38 PM PDT 23
Finished Oct 08 03:05:41 PM PDT 23
Peak memory 205868 kb
Host smart-595d3947-6ea9-4431-b727-a44a1f1948b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793248693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1793248693
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.940404022
Short name T140
Test name
Test status
Simulation time 50551707321 ps
CPU time 650.44 seconds
Started Oct 08 01:43:28 PM PDT 23
Finished Oct 08 01:54:19 PM PDT 23
Peak memory 214804 kb
Host smart-2ac99e73-e1d6-4f6d-8788-6d5a0bbb5255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940404022 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.940404022
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.169895126
Short name T63
Test name
Test status
Simulation time 61398787 ps
CPU time 0.94 seconds
Started Oct 08 01:45:29 PM PDT 23
Finished Oct 08 01:45:31 PM PDT 23
Peak memory 205184 kb
Host smart-1c4a8cdf-8d67-491c-b75c-33327285bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169895126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.169895126
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3083689223
Short name T595
Test name
Test status
Simulation time 16936990 ps
CPU time 0.93 seconds
Started Oct 08 01:45:35 PM PDT 23
Finished Oct 08 01:45:37 PM PDT 23
Peak memory 205276 kb
Host smart-fc804c15-9694-4fae-8387-d74774a36478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083689223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3083689223
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.4139569253
Short name T679
Test name
Test status
Simulation time 22932104 ps
CPU time 0.86 seconds
Started Oct 08 01:55:42 PM PDT 23
Finished Oct 08 01:55:43 PM PDT 23
Peak memory 214492 kb
Host smart-4a1f128d-6627-4882-9cca-15f53fc64405
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139569253 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4139569253
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3004604383
Short name T275
Test name
Test status
Simulation time 23140803 ps
CPU time 0.95 seconds
Started Oct 08 01:45:30 PM PDT 23
Finished Oct 08 01:45:31 PM PDT 23
Peak memory 214668 kb
Host smart-ec651ba0-d09c-413a-8e7e-5baf63359cf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004604383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3004604383
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4177230404
Short name T251
Test name
Test status
Simulation time 41739116 ps
CPU time 1.05 seconds
Started Oct 08 01:42:23 PM PDT 23
Finished Oct 08 01:42:24 PM PDT 23
Peak memory 216768 kb
Host smart-47c1c9a0-5fe2-4096-81b6-8272aad4a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177230404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4177230404
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1370586819
Short name T13
Test name
Test status
Simulation time 16959989 ps
CPU time 1.09 seconds
Started Oct 08 01:43:05 PM PDT 23
Finished Oct 08 01:43:06 PM PDT 23
Peak memory 214448 kb
Host smart-5f0d367f-2659-42dd-ac6b-24c4a3992d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370586819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1370586819
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3578597860
Short name T84
Test name
Test status
Simulation time 29859581 ps
CPU time 0.87 seconds
Started Oct 08 01:42:56 PM PDT 23
Finished Oct 08 01:42:57 PM PDT 23
Peak memory 214592 kb
Host smart-a6a75a07-9f89-4ec0-b71a-d6b60eb7fb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578597860 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3578597860
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2298543830
Short name T706
Test name
Test status
Simulation time 12859525 ps
CPU time 0.87 seconds
Started Oct 08 01:43:27 PM PDT 23
Finished Oct 08 01:43:28 PM PDT 23
Peak memory 204984 kb
Host smart-e2ed5cf1-5de6-4c3f-8970-8969d1229df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298543830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2298543830
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2116194613
Short name T24
Test name
Test status
Simulation time 253426218 ps
CPU time 4.08 seconds
Started Oct 08 01:50:09 PM PDT 23
Finished Oct 08 01:50:13 PM PDT 23
Peak memory 233332 kb
Host smart-38b2686e-15bc-490c-aec9-23942951a058
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116194613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2116194613
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.918848061
Short name T55
Test name
Test status
Simulation time 46707876 ps
CPU time 0.91 seconds
Started Oct 08 01:41:13 PM PDT 23
Finished Oct 08 01:41:14 PM PDT 23
Peak memory 204976 kb
Host smart-9aacc80c-adbe-4f3a-b1d6-dfe394420e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918848061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.918848061
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3400734148
Short name T120
Test name
Test status
Simulation time 312822752 ps
CPU time 3.62 seconds
Started Oct 08 01:43:05 PM PDT 23
Finished Oct 08 01:43:09 PM PDT 23
Peak memory 205956 kb
Host smart-6a3a9aec-5f89-4e14-ac84-d04113784ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400734148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3400734148
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4179020796
Short name T577
Test name
Test status
Simulation time 34877533857 ps
CPU time 636.65 seconds
Started Oct 08 01:55:38 PM PDT 23
Finished Oct 08 02:06:15 PM PDT 23
Peak memory 215216 kb
Host smart-cf7d9c0d-095b-465b-adb5-26bcb83f894e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179020796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4179020796
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1478680776
Short name T310
Test name
Test status
Simulation time 61571269 ps
CPU time 0.94 seconds
Started Oct 08 01:47:51 PM PDT 23
Finished Oct 08 01:47:52 PM PDT 23
Peak memory 205048 kb
Host smart-3943d91a-af78-4bf1-8374-c7adfb270ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478680776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1478680776
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1206682252
Short name T641
Test name
Test status
Simulation time 17561796 ps
CPU time 0.87 seconds
Started Oct 08 01:56:08 PM PDT 23
Finished Oct 08 01:56:09 PM PDT 23
Peak memory 204616 kb
Host smart-4b95fdba-9154-4141-80b8-a2b659618705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206682252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1206682252
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2804315356
Short name T69
Test name
Test status
Simulation time 94407269 ps
CPU time 0.8 seconds
Started Oct 08 01:46:47 PM PDT 23
Finished Oct 08 01:46:48 PM PDT 23
Peak memory 214352 kb
Host smart-57d5abfc-af89-4a06-b075-ed7cda3e1766
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804315356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2804315356
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1330523687
Short name T64
Test name
Test status
Simulation time 58927967 ps
CPU time 1.06 seconds
Started Oct 08 02:36:54 PM PDT 23
Finished Oct 08 02:36:55 PM PDT 23
Peak memory 214568 kb
Host smart-47e05bea-bbb6-4e92-90f4-74d17a2873ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330523687 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1330523687
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.379281134
Short name T244
Test name
Test status
Simulation time 43358499 ps
CPU time 1.02 seconds
Started Oct 08 01:47:50 PM PDT 23
Finished Oct 08 01:47:52 PM PDT 23
Peak memory 216908 kb
Host smart-e14cd5fd-a972-4713-a2c6-c6c0b6fc1c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379281134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.379281134
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2522133329
Short name T43
Test name
Test status
Simulation time 74638420 ps
CPU time 1.34 seconds
Started Oct 08 01:50:36 PM PDT 23
Finished Oct 08 01:50:38 PM PDT 23
Peak memory 205344 kb
Host smart-d537c6a6-003d-4e9e-821f-4507c5cce70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522133329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2522133329
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1344117055
Short name T111
Test name
Test status
Simulation time 24356750 ps
CPU time 0.95 seconds
Started Oct 08 01:51:48 PM PDT 23
Finished Oct 08 01:51:50 PM PDT 23
Peak memory 225704 kb
Host smart-a1559189-e800-4731-b4ce-9c251f627868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344117055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1344117055
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1335651653
Short name T499
Test name
Test status
Simulation time 24196452 ps
CPU time 0.9 seconds
Started Oct 08 01:44:37 PM PDT 23
Finished Oct 08 01:44:38 PM PDT 23
Peak memory 204684 kb
Host smart-9246162d-cec1-4c07-a790-72c1defe480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335651653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1335651653
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2589388754
Short name T158
Test name
Test status
Simulation time 181473885 ps
CPU time 3.09 seconds
Started Oct 08 01:44:40 PM PDT 23
Finished Oct 08 01:44:43 PM PDT 23
Peak memory 206212 kb
Host smart-cc4e3e2b-245e-4123-ab97-ad28aa36bc44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589388754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2589388754
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2740158894
Short name T518
Test name
Test status
Simulation time 22761247282 ps
CPU time 483.63 seconds
Started Oct 08 01:52:40 PM PDT 23
Finished Oct 08 02:00:44 PM PDT 23
Peak memory 216080 kb
Host smart-c0dfce86-10d6-44f9-a389-fcedb13e1e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740158894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2740158894
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.811159767
Short name T89
Test name
Test status
Simulation time 43064493 ps
CPU time 0.86 seconds
Started Oct 08 02:25:30 PM PDT 23
Finished Oct 08 02:25:31 PM PDT 23
Peak memory 205252 kb
Host smart-5a3372ca-5047-48d3-9a48-2d4ffa9131bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811159767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.811159767
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1172068524
Short name T635
Test name
Test status
Simulation time 20236335 ps
CPU time 0.84 seconds
Started Oct 08 01:46:33 PM PDT 23
Finished Oct 08 01:46:34 PM PDT 23
Peak memory 204256 kb
Host smart-fc5582d0-9728-4151-a8aa-f28d58b74ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172068524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1172068524
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3208830839
Short name T619
Test name
Test status
Simulation time 10764211 ps
CPU time 0.84 seconds
Started Oct 08 02:07:39 PM PDT 23
Finished Oct 08 02:07:40 PM PDT 23
Peak memory 214492 kb
Host smart-8b3cf4e5-c767-4c6e-aa3e-493573559c46
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208830839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3208830839
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1379863117
Short name T593
Test name
Test status
Simulation time 80122965 ps
CPU time 0.97 seconds
Started Oct 08 02:41:37 PM PDT 23
Finished Oct 08 02:41:38 PM PDT 23
Peak memory 214628 kb
Host smart-8721cb0b-23d7-4f80-bd85-1c2897668879
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379863117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1379863117
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3511811392
Short name T588
Test name
Test status
Simulation time 21686258 ps
CPU time 1 seconds
Started Oct 08 03:24:04 PM PDT 23
Finished Oct 08 03:24:06 PM PDT 23
Peak memory 214612 kb
Host smart-b4be8e23-c8b4-4c65-b123-8b71c5b985df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511811392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3511811392
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_intr.4100527769
Short name T642
Test name
Test status
Simulation time 20104873 ps
CPU time 0.93 seconds
Started Oct 08 03:29:27 PM PDT 23
Finished Oct 08 03:29:28 PM PDT 23
Peak memory 214796 kb
Host smart-03364a99-e427-4e7e-9b21-dff7fead3a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100527769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4100527769
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.278944405
Short name T500
Test name
Test status
Simulation time 30078235 ps
CPU time 0.81 seconds
Started Oct 08 03:39:41 PM PDT 23
Finished Oct 08 03:39:42 PM PDT 23
Peak memory 204684 kb
Host smart-6a62be24-b260-4899-9a8e-0dd754f740ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278944405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.278944405
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4023921511
Short name T578
Test name
Test status
Simulation time 115224371 ps
CPU time 2.69 seconds
Started Oct 08 02:44:12 PM PDT 23
Finished Oct 08 02:44:15 PM PDT 23
Peak memory 206040 kb
Host smart-e7c9c811-6ac7-4ddf-8131-02775e1d4c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023921511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4023921511
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4186835670
Short name T498
Test name
Test status
Simulation time 267682025581 ps
CPU time 1586.28 seconds
Started Oct 08 02:09:16 PM PDT 23
Finished Oct 08 02:35:43 PM PDT 23
Peak memory 221408 kb
Host smart-d7dfe580-aac0-4f58-a519-15a59ab7a6d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186835670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4186835670
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.969447346
Short name T661
Test name
Test status
Simulation time 20028673 ps
CPU time 1.01 seconds
Started Oct 08 01:47:09 PM PDT 23
Finished Oct 08 01:47:10 PM PDT 23
Peak memory 205176 kb
Host smart-0ecc066a-e691-4184-8f99-90c6acb1ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969447346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.969447346
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.4175495133
Short name T315
Test name
Test status
Simulation time 15657382 ps
CPU time 0.92 seconds
Started Oct 08 01:47:04 PM PDT 23
Finished Oct 08 01:47:05 PM PDT 23
Peak memory 205428 kb
Host smart-aa2ef66b-baa4-4e77-b507-4a48af5d95e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175495133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4175495133
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2065971807
Short name T81
Test name
Test status
Simulation time 86762971 ps
CPU time 1.07 seconds
Started Oct 08 01:45:13 PM PDT 23
Finished Oct 08 01:45:15 PM PDT 23
Peak memory 214652 kb
Host smart-296750cb-45a9-4648-aa9f-64095789bf88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065971807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2065971807
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.132622047
Short name T243
Test name
Test status
Simulation time 89166549 ps
CPU time 1.06 seconds
Started Oct 08 01:46:02 PM PDT 23
Finished Oct 08 01:46:03 PM PDT 23
Peak memory 217032 kb
Host smart-08106e8d-46ba-461e-ba56-2fdb95a0a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132622047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.132622047
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1039774630
Short name T268
Test name
Test status
Simulation time 50333211 ps
CPU time 1.05 seconds
Started Oct 08 01:43:44 PM PDT 23
Finished Oct 08 01:43:45 PM PDT 23
Peak memory 205536 kb
Host smart-c3b7768a-53f5-4379-984a-c9bf51936071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039774630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1039774630
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3067531850
Short name T551
Test name
Test status
Simulation time 37121557 ps
CPU time 0.86 seconds
Started Oct 08 01:47:05 PM PDT 23
Finished Oct 08 01:47:06 PM PDT 23
Peak memory 214364 kb
Host smart-26bf0044-3fa0-4343-bda0-7d56768a480a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067531850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3067531850
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3345744591
Short name T670
Test name
Test status
Simulation time 27948604 ps
CPU time 0.8 seconds
Started Oct 08 01:46:28 PM PDT 23
Finished Oct 08 01:46:29 PM PDT 23
Peak memory 204924 kb
Host smart-7b461b66-3eab-4bc5-8552-eff2df878640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345744591 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3345744591
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2887672566
Short name T463
Test name
Test status
Simulation time 1909307939 ps
CPU time 4.26 seconds
Started Oct 08 01:45:08 PM PDT 23
Finished Oct 08 01:45:12 PM PDT 23
Peak memory 205932 kb
Host smart-abcaf1f2-8a24-40ef-9855-06bb69487f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887672566 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2887672566
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.1892560401
Short name T605
Test name
Test status
Simulation time 45599322 ps
CPU time 0.96 seconds
Started Oct 08 03:12:15 PM PDT 23
Finished Oct 08 03:12:16 PM PDT 23
Peak memory 205304 kb
Host smart-c88cfed6-092f-40b3-a314-d9ebde111ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892560401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1892560401
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.407346410
Short name T97
Test name
Test status
Simulation time 15537691 ps
CPU time 0.91 seconds
Started Oct 08 01:45:00 PM PDT 23
Finished Oct 08 01:45:01 PM PDT 23
Peak memory 204668 kb
Host smart-4a9f7137-776e-4c9a-a68b-ccbde4d28f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407346410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.407346410
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.747461680
Short name T181
Test name
Test status
Simulation time 80457336 ps
CPU time 1 seconds
Started Oct 08 01:53:48 PM PDT 23
Finished Oct 08 01:53:49 PM PDT 23
Peak memory 214732 kb
Host smart-a34cc939-dcb4-4940-980d-050bff872571
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747461680 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.747461680
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2359573224
Short name T14
Test name
Test status
Simulation time 30623736 ps
CPU time 1.3 seconds
Started Oct 08 02:29:16 PM PDT 23
Finished Oct 08 02:29:17 PM PDT 23
Peak memory 222048 kb
Host smart-793d57a2-0dba-44c1-a7bf-cd98606d32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359573224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2359573224
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1420561103
Short name T287
Test name
Test status
Simulation time 55610839 ps
CPU time 0.95 seconds
Started Oct 08 02:51:32 PM PDT 23
Finished Oct 08 02:51:33 PM PDT 23
Peak memory 204956 kb
Host smart-685d28c0-ebe8-4212-9207-e9089e8db4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420561103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1420561103
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2007169709
Short name T470
Test name
Test status
Simulation time 55072295 ps
CPU time 0.92 seconds
Started Oct 08 01:51:54 PM PDT 23
Finished Oct 08 01:51:55 PM PDT 23
Peak memory 221416 kb
Host smart-afe25066-9ad0-4a33-a8d5-2ba69a9b8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007169709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2007169709
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3955533735
Short name T480
Test name
Test status
Simulation time 21895990 ps
CPU time 0.82 seconds
Started Oct 08 01:45:55 PM PDT 23
Finished Oct 08 01:45:56 PM PDT 23
Peak memory 204768 kb
Host smart-37ea5de4-7fdb-4642-bdb6-f350059fd4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955533735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3955533735
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1404733173
Short name T514
Test name
Test status
Simulation time 58457385 ps
CPU time 0.9 seconds
Started Oct 08 02:55:25 PM PDT 23
Finished Oct 08 02:55:26 PM PDT 23
Peak memory 204120 kb
Host smart-9b32434a-e6cb-4a6a-b242-d1288ee6618f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404733173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1404733173
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1020728215
Short name T468
Test name
Test status
Simulation time 64205036677 ps
CPU time 929.59 seconds
Started Oct 08 04:41:16 PM PDT 23
Finished Oct 08 04:56:46 PM PDT 23
Peak memory 215116 kb
Host smart-030bf9a9-50b0-4448-8e0b-c305ea7a31e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020728215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1020728215
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.3347365208
Short name T548
Test name
Test status
Simulation time 32979580 ps
CPU time 0.84 seconds
Started Oct 08 01:43:47 PM PDT 23
Finished Oct 08 01:43:49 PM PDT 23
Peak memory 204472 kb
Host smart-10a0daf6-b979-4d32-98fc-96b124cc47ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347365208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3347365208
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3892803480
Short name T62
Test name
Test status
Simulation time 11668374 ps
CPU time 0.9 seconds
Started Oct 08 03:22:39 PM PDT 23
Finished Oct 08 03:22:40 PM PDT 23
Peak memory 214480 kb
Host smart-b9b9edf9-7070-456f-8b34-af61fd4f393d
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892803480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3892803480
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4137124319
Short name T699
Test name
Test status
Simulation time 59167707 ps
CPU time 1.07 seconds
Started Oct 08 01:50:57 PM PDT 23
Finished Oct 08 01:50:58 PM PDT 23
Peak memory 214756 kb
Host smart-6c2bbd2b-971b-46d1-af78-b2c0b77908d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137124319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4137124319
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4023693927
Short name T248
Test name
Test status
Simulation time 66851504 ps
CPU time 1.03 seconds
Started Oct 08 02:09:27 PM PDT 23
Finished Oct 08 02:09:28 PM PDT 23
Peak memory 216848 kb
Host smart-61ac93f4-b43f-4f9c-9b2e-651ed336596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023693927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4023693927
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_intr.1271314532
Short name T103
Test name
Test status
Simulation time 25991177 ps
CPU time 0.94 seconds
Started Oct 08 01:48:04 PM PDT 23
Finished Oct 08 01:48:05 PM PDT 23
Peak memory 214496 kb
Host smart-6805e1cc-e3f9-4074-baeb-62e12ff47d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271314532 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1271314532
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1077915348
Short name T596
Test name
Test status
Simulation time 15324785 ps
CPU time 0.89 seconds
Started Oct 08 01:53:48 PM PDT 23
Finished Oct 08 01:53:49 PM PDT 23
Peak memory 204920 kb
Host smart-e39f32f8-32d1-4d6b-8122-5cb0512391a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077915348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1077915348
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3233414593
Short name T629
Test name
Test status
Simulation time 123635492 ps
CPU time 2.72 seconds
Started Oct 08 01:53:00 PM PDT 23
Finished Oct 08 01:53:03 PM PDT 23
Peak memory 206188 kb
Host smart-08d48ae7-544c-4138-a153-dab231f7859e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233414593 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3233414593
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2360902275
Short name T516
Test name
Test status
Simulation time 38700712766 ps
CPU time 845.68 seconds
Started Oct 08 01:46:35 PM PDT 23
Finished Oct 08 02:00:41 PM PDT 23
Peak memory 215184 kb
Host smart-d44d243b-45b3-4a3b-9ca8-d9662558d228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360902275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2360902275
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1200813472
Short name T295
Test name
Test status
Simulation time 101146017 ps
CPU time 0.93 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 206068 kb
Host smart-42ad869b-b306-456f-8320-a98e301a05e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200813472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1200813472
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2942187184
Short name T632
Test name
Test status
Simulation time 16186451 ps
CPU time 0.93 seconds
Started Oct 08 02:35:48 PM PDT 23
Finished Oct 08 02:35:49 PM PDT 23
Peak memory 204564 kb
Host smart-ef31f321-e848-46a3-8331-2606c968880b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942187184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2942187184
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4280273194
Short name T194
Test name
Test status
Simulation time 11477056 ps
CPU time 0.94 seconds
Started Oct 08 01:45:31 PM PDT 23
Finished Oct 08 01:45:32 PM PDT 23
Peak memory 214472 kb
Host smart-4ddfd6fa-b443-47ff-9b6e-8859bf06b183
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280273194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4280273194
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3303031786
Short name T138
Test name
Test status
Simulation time 61293107 ps
CPU time 0.98 seconds
Started Oct 08 01:44:09 PM PDT 23
Finished Oct 08 01:44:10 PM PDT 23
Peak memory 214708 kb
Host smart-ca5b8160-a215-4585-9990-1665d7994bda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303031786 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3303031786
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3837907567
Short name T191
Test name
Test status
Simulation time 27343578 ps
CPU time 0.97 seconds
Started Oct 08 02:31:48 PM PDT 23
Finished Oct 08 02:31:49 PM PDT 23
Peak memory 221368 kb
Host smart-5e3b905f-c56a-4492-8108-66afe1cd78c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837907567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3837907567
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_intr.2502675393
Short name T59
Test name
Test status
Simulation time 47984084 ps
CPU time 0.85 seconds
Started Oct 08 01:50:54 PM PDT 23
Finished Oct 08 01:50:55 PM PDT 23
Peak memory 214460 kb
Host smart-cfc4a468-12d7-4b6a-b23d-d1a3654054e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502675393 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2502675393
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1442318836
Short name T501
Test name
Test status
Simulation time 88099142 ps
CPU time 0.86 seconds
Started Oct 08 01:49:49 PM PDT 23
Finished Oct 08 01:49:50 PM PDT 23
Peak memory 204896 kb
Host smart-72aad119-dfd1-4016-96b2-99c74c015043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442318836 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1442318836
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2837428660
Short name T638
Test name
Test status
Simulation time 28340830 ps
CPU time 0.97 seconds
Started Oct 08 01:48:01 PM PDT 23
Finished Oct 08 01:48:02 PM PDT 23
Peak memory 204788 kb
Host smart-34771bb2-bcab-4f87-96a9-ddcadcd7c1f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837428660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2837428660
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.4052281141
Short name T476
Test name
Test status
Simulation time 33585406 ps
CPU time 0.98 seconds
Started Oct 08 01:43:59 PM PDT 23
Finished Oct 08 01:44:00 PM PDT 23
Peak memory 205220 kb
Host smart-0d060804-f0a9-42c6-8fe8-b3a48362e745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052281141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.4052281141
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4162110304
Short name T296
Test name
Test status
Simulation time 94728435 ps
CPU time 0.91 seconds
Started Oct 08 01:46:31 PM PDT 23
Finished Oct 08 01:46:32 PM PDT 23
Peak memory 205584 kb
Host smart-80850dff-a0d4-43ca-8dc8-31cea4c618a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162110304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4162110304
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3123981718
Short name T708
Test name
Test status
Simulation time 24501438 ps
CPU time 0.87 seconds
Started Oct 08 01:49:59 PM PDT 23
Finished Oct 08 01:50:00 PM PDT 23
Peak memory 214484 kb
Host smart-114e04ed-9384-4b1d-83ca-7e223bd3f3e2
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123981718 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3123981718
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.393503908
Short name T78
Test name
Test status
Simulation time 26044683 ps
CPU time 1.04 seconds
Started Oct 08 01:47:53 PM PDT 23
Finished Oct 08 01:47:55 PM PDT 23
Peak memory 214640 kb
Host smart-74b6d55c-f871-4b40-a1c4-01030e75ebad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393503908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.393503908
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2899732754
Short name T7
Test name
Test status
Simulation time 39306997 ps
CPU time 1.01 seconds
Started Oct 08 01:56:32 PM PDT 23
Finished Oct 08 01:56:33 PM PDT 23
Peak memory 221988 kb
Host smart-c3b964db-1466-4a59-bbab-9d45a2955e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899732754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2899732754
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1391751267
Short name T610
Test name
Test status
Simulation time 30940933 ps
CPU time 1.06 seconds
Started Oct 08 01:43:54 PM PDT 23
Finished Oct 08 01:43:55 PM PDT 23
Peak memory 214380 kb
Host smart-491b8183-46d2-47fb-9814-46c2b0bc99c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391751267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1391751267
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1575073067
Short name T530
Test name
Test status
Simulation time 18397845 ps
CPU time 1.01 seconds
Started Oct 08 01:43:57 PM PDT 23
Finished Oct 08 01:43:58 PM PDT 23
Peak memory 214768 kb
Host smart-d323545c-e4d1-43cb-b0e3-fecf6c4c816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575073067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1575073067
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.159729364
Short name T464
Test name
Test status
Simulation time 24503106 ps
CPU time 0.83 seconds
Started Oct 08 01:56:13 PM PDT 23
Finished Oct 08 01:56:14 PM PDT 23
Peak memory 204716 kb
Host smart-017f87a8-7591-454e-aa0e-565c770383c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159729364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.159729364
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.515724843
Short name T267
Test name
Test status
Simulation time 118098579 ps
CPU time 2.77 seconds
Started Oct 08 01:50:34 PM PDT 23
Finished Oct 08 01:50:37 PM PDT 23
Peak memory 205632 kb
Host smart-3d3e7b41-8124-4021-b631-07e8a49d764a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515724843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.515724843
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4005963610
Short name T712
Test name
Test status
Simulation time 40494019573 ps
CPU time 245.35 seconds
Started Oct 08 01:50:33 PM PDT 23
Finished Oct 08 01:54:38 PM PDT 23
Peak memory 215368 kb
Host smart-5690ee6f-fe03-4105-92bd-7fd6bcdd6a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005963610 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4005963610
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2326694063
Short name T114
Test name
Test status
Simulation time 18195825 ps
CPU time 0.99 seconds
Started Oct 08 03:24:09 PM PDT 23
Finished Oct 08 03:24:10 PM PDT 23
Peak memory 206260 kb
Host smart-344cfeac-c7f0-46ce-8c4d-4f392c9a7c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326694063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2326694063
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2657595358
Short name T538
Test name
Test status
Simulation time 42691875 ps
CPU time 0.94 seconds
Started Oct 08 02:28:16 PM PDT 23
Finished Oct 08 02:28:18 PM PDT 23
Peak memory 202924 kb
Host smart-88bf9b3e-b2f0-47ca-8f0e-758e0ab8bd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657595358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2657595358
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.280267226
Short name T61
Test name
Test status
Simulation time 13606811 ps
CPU time 0.88 seconds
Started Oct 08 02:58:22 PM PDT 23
Finished Oct 08 02:58:23 PM PDT 23
Peak memory 214564 kb
Host smart-6db16f9b-cf23-4c8d-a6f9-71ddc07b3ba8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280267226 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.280267226
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3367454019
Short name T625
Test name
Test status
Simulation time 23452208 ps
CPU time 1 seconds
Started Oct 08 02:56:29 PM PDT 23
Finished Oct 08 02:56:30 PM PDT 23
Peak memory 214644 kb
Host smart-30c6183b-0acb-4b6c-8612-78266756ec33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367454019 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3367454019
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2927650362
Short name T247
Test name
Test status
Simulation time 19593932 ps
CPU time 1.38 seconds
Started Oct 08 01:45:23 PM PDT 23
Finished Oct 08 01:45:26 PM PDT 23
Peak memory 214560 kb
Host smart-8b7372fa-1213-49ad-84c2-eab0c97c42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927650362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2927650362
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.4009263319
Short name T503
Test name
Test status
Simulation time 30684511 ps
CPU time 1.19 seconds
Started Oct 08 01:46:26 PM PDT 23
Finished Oct 08 01:46:28 PM PDT 23
Peak memory 214360 kb
Host smart-6893c04c-f59c-4e6c-889e-9707b4311bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009263319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.4009263319
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1015839376
Short name T112
Test name
Test status
Simulation time 23569886 ps
CPU time 0.88 seconds
Started Oct 08 02:48:21 PM PDT 23
Finished Oct 08 02:48:22 PM PDT 23
Peak memory 214780 kb
Host smart-e8c08f21-1cf1-4829-953f-7a8085e9b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015839376 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1015839376
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1250765757
Short name T626
Test name
Test status
Simulation time 40071876 ps
CPU time 0.88 seconds
Started Oct 08 01:47:56 PM PDT 23
Finished Oct 08 01:47:57 PM PDT 23
Peak memory 204872 kb
Host smart-5aa79da6-45ef-4fa3-bcef-7b44b87d824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250765757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1250765757
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3322260126
Short name T233
Test name
Test status
Simulation time 136801562 ps
CPU time 1.79 seconds
Started Oct 08 01:48:02 PM PDT 23
Finished Oct 08 01:48:04 PM PDT 23
Peak memory 205468 kb
Host smart-522b1acc-1410-45ca-a26b-b7e6e016afe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322260126 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3322260126
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3930954964
Short name T116
Test name
Test status
Simulation time 122403910575 ps
CPU time 662.71 seconds
Started Oct 08 01:49:59 PM PDT 23
Finished Oct 08 02:01:02 PM PDT 23
Peak memory 215656 kb
Host smart-179a01bd-28c9-48c8-802c-d65774abc9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930954964 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3930954964
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.547968410
Short name T718
Test name
Test status
Simulation time 19024307 ps
CPU time 0.94 seconds
Started Oct 08 01:48:23 PM PDT 23
Finished Oct 08 01:48:25 PM PDT 23
Peak memory 206132 kb
Host smart-01c51826-bf12-4c83-82d3-ad8e8b64ebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547968410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.547968410
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.314780427
Short name T728
Test name
Test status
Simulation time 93491302 ps
CPU time 0.97 seconds
Started Oct 08 02:43:36 PM PDT 23
Finished Oct 08 02:43:37 PM PDT 23
Peak memory 204680 kb
Host smart-5c01758f-d1fc-4688-b50e-82ce2a602f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314780427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.314780427
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.508913464
Short name T199
Test name
Test status
Simulation time 30944039 ps
CPU time 0.8 seconds
Started Oct 08 02:29:08 PM PDT 23
Finished Oct 08 02:29:09 PM PDT 23
Peak memory 214492 kb
Host smart-7c6cb4e6-f0fa-4e19-9d80-f3570b9f7cdd
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508913464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.508913464
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1123951870
Short name T725
Test name
Test status
Simulation time 33703939 ps
CPU time 0.9 seconds
Started Oct 08 01:52:55 PM PDT 23
Finished Oct 08 01:52:56 PM PDT 23
Peak memory 214728 kb
Host smart-efc76444-44b4-41fe-ae0f-d096a80493ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123951870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1123951870
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2563588223
Short name T643
Test name
Test status
Simulation time 29667273 ps
CPU time 1.26 seconds
Started Oct 08 01:46:12 PM PDT 23
Finished Oct 08 01:46:13 PM PDT 23
Peak memory 214548 kb
Host smart-62de44e7-01de-46ad-ad81-1e0ac285da18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563588223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2563588223
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1376533276
Short name T72
Test name
Test status
Simulation time 23183177 ps
CPU time 1.12 seconds
Started Oct 08 01:50:27 PM PDT 23
Finished Oct 08 01:50:28 PM PDT 23
Peak memory 205204 kb
Host smart-f583f7c4-d05f-472c-a004-9b5444473dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376533276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1376533276
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.243719344
Short name T104
Test name
Test status
Simulation time 32351085 ps
CPU time 0.83 seconds
Started Oct 08 01:45:25 PM PDT 23
Finished Oct 08 01:45:26 PM PDT 23
Peak memory 214600 kb
Host smart-f12e784a-b982-48fe-a2e6-485db77b6cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243719344 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.243719344
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4049454795
Short name T542
Test name
Test status
Simulation time 73844396 ps
CPU time 0.86 seconds
Started Oct 08 02:30:14 PM PDT 23
Finished Oct 08 02:30:15 PM PDT 23
Peak memory 204868 kb
Host smart-917f7022-78db-4fef-b7aa-1b7204cd7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049454795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4049454795
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.802660248
Short name T157
Test name
Test status
Simulation time 93957974 ps
CPU time 1.54 seconds
Started Oct 08 03:26:05 PM PDT 23
Finished Oct 08 03:26:07 PM PDT 23
Peak memory 205464 kb
Host smart-6b9a46c6-6807-42f3-ac72-4d2d17d18de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802660248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.802660248
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4198703766
Short name T727
Test name
Test status
Simulation time 113883088808 ps
CPU time 1213.01 seconds
Started Oct 08 01:48:20 PM PDT 23
Finished Oct 08 02:08:34 PM PDT 23
Peak memory 216332 kb
Host smart-d52de3da-7027-42b0-b9ea-7711ea49fae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198703766 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4198703766
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2575128786
Short name T100
Test name
Test status
Simulation time 56613343 ps
CPU time 0.95 seconds
Started Oct 08 01:54:54 PM PDT 23
Finished Oct 08 01:54:56 PM PDT 23
Peak memory 206188 kb
Host smart-ee49a9de-e477-4bfe-9f04-9aa6f4abea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575128786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2575128786
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.752537097
Short name T628
Test name
Test status
Simulation time 84141908 ps
CPU time 0.8 seconds
Started Oct 08 01:55:12 PM PDT 23
Finished Oct 08 01:55:13 PM PDT 23
Peak memory 205080 kb
Host smart-3fb54a56-8ec9-4fac-9512-4fa51005130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752537097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.752537097
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2126139192
Short name T132
Test name
Test status
Simulation time 20543448 ps
CPU time 0.84 seconds
Started Oct 08 01:48:31 PM PDT 23
Finished Oct 08 01:48:32 PM PDT 23
Peak memory 214504 kb
Host smart-29891780-a5e0-4a34-be13-05ccad0dd028
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126139192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2126139192
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.280904712
Short name T457
Test name
Test status
Simulation time 19921508 ps
CPU time 1.26 seconds
Started Oct 08 01:44:21 PM PDT 23
Finished Oct 08 01:44:23 PM PDT 23
Peak memory 215620 kb
Host smart-91513264-9390-48c8-ac06-3561c567b8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280904712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.280904712
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3043404111
Short name T37
Test name
Test status
Simulation time 58722156 ps
CPU time 1.03 seconds
Started Oct 08 01:52:59 PM PDT 23
Finished Oct 08 01:53:00 PM PDT 23
Peak memory 205472 kb
Host smart-b4fae6e3-b315-4049-9460-f23f6a04bcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043404111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3043404111
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3895147094
Short name T560
Test name
Test status
Simulation time 28357444 ps
CPU time 0.83 seconds
Started Oct 08 01:46:30 PM PDT 23
Finished Oct 08 01:46:31 PM PDT 23
Peak memory 214676 kb
Host smart-4d942886-dab4-4a29-b4d3-e5166ce8597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895147094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3895147094
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1201630689
Short name T526
Test name
Test status
Simulation time 12880758 ps
CPU time 0.9 seconds
Started Oct 08 01:46:52 PM PDT 23
Finished Oct 08 01:46:53 PM PDT 23
Peak memory 205184 kb
Host smart-78e0abf7-e205-4e20-a16b-c8f4deaa9edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201630689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1201630689
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3949254605
Short name T85
Test name
Test status
Simulation time 43828781 ps
CPU time 0.95 seconds
Started Oct 08 01:45:17 PM PDT 23
Finished Oct 08 01:45:19 PM PDT 23
Peak memory 204684 kb
Host smart-ec2529cd-08d6-41ae-ac77-66523c30a23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949254605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3949254605
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3008186071
Short name T613
Test name
Test status
Simulation time 82053284730 ps
CPU time 892.98 seconds
Started Oct 08 01:46:29 PM PDT 23
Finished Oct 08 02:01:22 PM PDT 23
Peak memory 215604 kb
Host smart-4503b01e-610a-4135-af8f-34813d6b2efe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008186071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3008186071
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3383968683
Short name T710
Test name
Test status
Simulation time 56168421 ps
CPU time 0.95 seconds
Started Oct 08 01:46:12 PM PDT 23
Finished Oct 08 01:46:13 PM PDT 23
Peak memory 206208 kb
Host smart-7c4948ce-0a2b-4102-8f1e-05d17ecb7dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383968683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3383968683
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1362697252
Short name T515
Test name
Test status
Simulation time 61327251 ps
CPU time 0.8 seconds
Started Oct 08 01:50:49 PM PDT 23
Finished Oct 08 01:50:50 PM PDT 23
Peak memory 204364 kb
Host smart-d76d5df8-c32f-4f8e-bfcc-b94720bef307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362697252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1362697252
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1168235502
Short name T680
Test name
Test status
Simulation time 46052908 ps
CPU time 0.87 seconds
Started Oct 08 01:46:13 PM PDT 23
Finished Oct 08 01:46:14 PM PDT 23
Peak memory 214396 kb
Host smart-2a53d60e-309c-4b9f-b9bf-88ec9e2653e8
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168235502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1168235502
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3587488150
Short name T580
Test name
Test status
Simulation time 26986548 ps
CPU time 1.08 seconds
Started Oct 08 01:47:11 PM PDT 23
Finished Oct 08 01:47:12 PM PDT 23
Peak memory 214648 kb
Host smart-96c99319-59a0-4665-9e03-db6b30702f12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587488150 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3587488150
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2570282460
Short name T206
Test name
Test status
Simulation time 21829888 ps
CPU time 0.87 seconds
Started Oct 08 01:45:45 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 215592 kb
Host smart-f5657195-0830-4a0d-858e-88433c45a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570282460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2570282460
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2511393466
Short name T564
Test name
Test status
Simulation time 61668543 ps
CPU time 1.25 seconds
Started Oct 08 01:42:30 PM PDT 23
Finished Oct 08 01:42:31 PM PDT 23
Peak memory 205408 kb
Host smart-af24ea9b-7839-4e7f-ab64-3bfe8e3d31b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511393466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2511393466
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3963182296
Short name T490
Test name
Test status
Simulation time 19175128 ps
CPU time 1.12 seconds
Started Oct 08 01:44:39 PM PDT 23
Finished Oct 08 01:44:40 PM PDT 23
Peak memory 221640 kb
Host smart-dbc70384-b01f-46af-bcb5-1ecfb66f1271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963182296 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3963182296
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2315754412
Short name T125
Test name
Test status
Simulation time 28980191 ps
CPU time 0.82 seconds
Started Oct 08 01:41:14 PM PDT 23
Finished Oct 08 01:41:15 PM PDT 23
Peak memory 204644 kb
Host smart-926d00e4-5eea-4eaa-8b2f-651d7a2062b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315754412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2315754412
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.983352424
Short name T668
Test name
Test status
Simulation time 33122586 ps
CPU time 0.86 seconds
Started Oct 08 01:43:14 PM PDT 23
Finished Oct 08 01:43:15 PM PDT 23
Peak memory 204652 kb
Host smart-6c89d3bf-cc46-4ee8-8b90-1de3afb14e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983352424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.983352424
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.556974259
Short name T314
Test name
Test status
Simulation time 109629713 ps
CPU time 1.75 seconds
Started Oct 08 01:44:37 PM PDT 23
Finished Oct 08 01:44:39 PM PDT 23
Peak memory 206016 kb
Host smart-440e057e-2c49-4963-b4d7-88c583fdcec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556974259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.556974259
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2967144375
Short name T264
Test name
Test status
Simulation time 121869506078 ps
CPU time 1298.75 seconds
Started Oct 08 01:46:08 PM PDT 23
Finished Oct 08 02:07:47 PM PDT 23
Peak memory 215792 kb
Host smart-b92ba676-01e2-41ce-a98d-a82db180bdbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967144375 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2967144375
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3130002768
Short name T176
Test name
Test status
Simulation time 40800086 ps
CPU time 1.08 seconds
Started Oct 08 01:47:09 PM PDT 23
Finished Oct 08 01:47:10 PM PDT 23
Peak memory 228756 kb
Host smart-b060c478-4438-44aa-8901-f07f25d74a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130002768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3130002768
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/51.edn_err.3284823340
Short name T575
Test name
Test status
Simulation time 24745106 ps
CPU time 1.08 seconds
Started Oct 08 01:52:44 PM PDT 23
Finished Oct 08 01:52:45 PM PDT 23
Peak memory 215724 kb
Host smart-69005d1c-8b40-4002-ad72-9387170b54c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284823340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3284823340
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.2567991893
Short name T479
Test name
Test status
Simulation time 46437641 ps
CPU time 0.92 seconds
Started Oct 08 01:55:12 PM PDT 23
Finished Oct 08 01:55:13 PM PDT 23
Peak memory 215532 kb
Host smart-4b8b3993-b6cc-44c0-8f06-7900da001d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567991893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2567991893
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.3187829360
Short name T258
Test name
Test status
Simulation time 26655586 ps
CPU time 1.23 seconds
Started Oct 08 01:56:19 PM PDT 23
Finished Oct 08 01:56:20 PM PDT 23
Peak memory 215840 kb
Host smart-8695395c-0d35-4be5-982f-b73332f093f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187829360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3187829360
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_err.2600474803
Short name T6
Test name
Test status
Simulation time 22965321 ps
CPU time 1.23 seconds
Started Oct 08 01:44:16 PM PDT 23
Finished Oct 08 01:44:18 PM PDT 23
Peak memory 228956 kb
Host smart-a9d49778-b05f-47c6-ae41-33b79b4ce259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600474803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2600474803
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/55.edn_err.4054469079
Short name T630
Test name
Test status
Simulation time 31780168 ps
CPU time 0.89 seconds
Started Oct 08 01:45:52 PM PDT 23
Finished Oct 08 01:45:53 PM PDT 23
Peak memory 215516 kb
Host smart-7ab3c814-0f85-445c-9fad-af791dccbd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054469079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4054469079
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/56.edn_err.148376060
Short name T165
Test name
Test status
Simulation time 19798394 ps
CPU time 1.19 seconds
Started Oct 08 01:56:19 PM PDT 23
Finished Oct 08 01:56:20 PM PDT 23
Peak memory 228844 kb
Host smart-0742eb55-1a0d-4a55-aeb1-9d05148160f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148376060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.148376060
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.2784889279
Short name T531
Test name
Test status
Simulation time 68288203 ps
CPU time 1.05 seconds
Started Oct 08 01:50:02 PM PDT 23
Finished Oct 08 01:50:03 PM PDT 23
Peak memory 216860 kb
Host smart-c2c69ebf-e89c-4b4b-a3ba-c09a157e262c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784889279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2784889279
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/58.edn_err.2175056967
Short name T623
Test name
Test status
Simulation time 29313263 ps
CPU time 1.31 seconds
Started Oct 08 01:44:37 PM PDT 23
Finished Oct 08 01:44:39 PM PDT 23
Peak memory 222216 kb
Host smart-227dd889-03a0-4d06-a444-261a59671849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175056967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2175056967
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.1770588425
Short name T252
Test name
Test status
Simulation time 103389576 ps
CPU time 1.11 seconds
Started Oct 08 01:45:54 PM PDT 23
Finished Oct 08 01:45:55 PM PDT 23
Peak memory 222012 kb
Host smart-895eaad0-432a-44d3-8601-8ef90d0d0192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770588425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1770588425
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.842755695
Short name T532
Test name
Test status
Simulation time 232896361 ps
CPU time 0.99 seconds
Started Oct 08 01:48:19 PM PDT 23
Finished Oct 08 01:48:20 PM PDT 23
Peak memory 205268 kb
Host smart-69c824d5-286c-4b80-8f0c-3c2da8ce6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842755695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.842755695
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3456486509
Short name T491
Test name
Test status
Simulation time 47642346 ps
CPU time 0.83 seconds
Started Oct 08 01:50:13 PM PDT 23
Finished Oct 08 01:50:14 PM PDT 23
Peak memory 205236 kb
Host smart-87eb500d-2ce6-4546-a71a-e2a7a4fbcd04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456486509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3456486509
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_err.4268922467
Short name T686
Test name
Test status
Simulation time 19027028 ps
CPU time 1.15 seconds
Started Oct 08 01:42:43 PM PDT 23
Finished Oct 08 01:42:44 PM PDT 23
Peak memory 221692 kb
Host smart-47420596-c310-49f1-811a-c0fe92dea06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268922467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4268922467
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.369548260
Short name T553
Test name
Test status
Simulation time 16482969 ps
CPU time 0.96 seconds
Started Oct 08 01:56:10 PM PDT 23
Finished Oct 08 01:56:11 PM PDT 23
Peak memory 205656 kb
Host smart-3e4779cc-7727-4717-88a3-7cad83680e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369548260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.369548260
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2452415900
Short name T648
Test name
Test status
Simulation time 23105237 ps
CPU time 0.88 seconds
Started Oct 08 01:42:55 PM PDT 23
Finished Oct 08 01:42:57 PM PDT 23
Peak memory 214668 kb
Host smart-187c3bfb-472f-4174-a2a3-34720a9c9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452415900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2452415900
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3280165285
Short name T677
Test name
Test status
Simulation time 37617912 ps
CPU time 0.88 seconds
Started Oct 08 01:49:04 PM PDT 23
Finished Oct 08 01:49:05 PM PDT 23
Peak memory 204876 kb
Host smart-f583aa1b-0a79-4c5e-9f87-31dfc8773d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280165285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3280165285
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2770945715
Short name T726
Test name
Test status
Simulation time 490749571 ps
CPU time 2.35 seconds
Started Oct 08 01:44:57 PM PDT 23
Finished Oct 08 01:45:00 PM PDT 23
Peak memory 205776 kb
Host smart-f8e820f9-bbc0-4c04-947e-45e9450226f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770945715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2770945715
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1470713537
Short name T558
Test name
Test status
Simulation time 40352213585 ps
CPU time 512.69 seconds
Started Oct 08 01:46:10 PM PDT 23
Finished Oct 08 01:54:43 PM PDT 23
Peak memory 215024 kb
Host smart-dc1cf6f5-2b06-443f-94c0-2c8cfa55d503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470713537 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1470713537
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.185224374
Short name T60
Test name
Test status
Simulation time 29272067 ps
CPU time 1.22 seconds
Started Oct 08 01:45:52 PM PDT 23
Finished Oct 08 01:45:53 PM PDT 23
Peak memory 216892 kb
Host smart-d47db82b-303b-45ff-8ad3-081aeaab1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185224374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.185224374
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/61.edn_err.1018055807
Short name T184
Test name
Test status
Simulation time 31183452 ps
CPU time 0.87 seconds
Started Oct 08 03:13:24 PM PDT 23
Finished Oct 08 03:13:26 PM PDT 23
Peak memory 215392 kb
Host smart-93bd65b2-96a1-487d-8fc3-f8c9811dec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018055807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1018055807
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/62.edn_err.1068316676
Short name T681
Test name
Test status
Simulation time 42992744 ps
CPU time 0.99 seconds
Started Oct 08 01:47:33 PM PDT 23
Finished Oct 08 01:47:35 PM PDT 23
Peak memory 215668 kb
Host smart-1e1ae852-783a-4766-97a7-2def3deb04fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068316676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1068316676
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_err.3719723343
Short name T658
Test name
Test status
Simulation time 33354065 ps
CPU time 0.82 seconds
Started Oct 08 01:46:27 PM PDT 23
Finished Oct 08 01:46:28 PM PDT 23
Peak memory 215572 kb
Host smart-1a941ac9-8ec2-48bf-a75c-fe86f4fd6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719723343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3719723343
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/64.edn_err.1429447850
Short name T552
Test name
Test status
Simulation time 89845152 ps
CPU time 0.95 seconds
Started Oct 08 03:10:02 PM PDT 23
Finished Oct 08 03:10:03 PM PDT 23
Peak memory 214652 kb
Host smart-6e49ebfd-2f84-4411-8503-ca6bb9e43573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429447850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1429447850
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.3419347378
Short name T245
Test name
Test status
Simulation time 29706476 ps
CPU time 1.29 seconds
Started Oct 08 02:29:55 PM PDT 23
Finished Oct 08 02:29:57 PM PDT 23
Peak memory 222112 kb
Host smart-b4256b9e-50b1-44b0-985e-343b40c1e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419347378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3419347378
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.450635627
Short name T238
Test name
Test status
Simulation time 19900462 ps
CPU time 1.08 seconds
Started Oct 08 02:29:27 PM PDT 23
Finished Oct 08 02:29:28 PM PDT 23
Peak memory 214600 kb
Host smart-9004279a-de5b-4326-bea2-0d89814195ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450635627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.450635627
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.1273298030
Short name T235
Test name
Test status
Simulation time 59730879 ps
CPU time 0.9 seconds
Started Oct 08 02:29:25 PM PDT 23
Finished Oct 08 02:29:26 PM PDT 23
Peak memory 221284 kb
Host smart-24c26d63-e218-4203-aa63-d2f447c0f25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273298030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1273298030
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.2979960528
Short name T170
Test name
Test status
Simulation time 33643282 ps
CPU time 0.86 seconds
Started Oct 08 02:07:31 PM PDT 23
Finished Oct 08 02:07:32 PM PDT 23
Peak memory 214448 kb
Host smart-a38bdae8-1470-41ec-b8fc-8101f4cbdc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979960528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2979960528
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.1666802080
Short name T172
Test name
Test status
Simulation time 19355939 ps
CPU time 1.33 seconds
Started Oct 08 01:53:53 PM PDT 23
Finished Oct 08 01:53:55 PM PDT 23
Peak memory 215348 kb
Host smart-440033fe-5f98-40f6-ac34-bb7491b2a9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666802080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1666802080
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.2792433370
Short name T536
Test name
Test status
Simulation time 50383121 ps
CPU time 0.97 seconds
Started Oct 08 01:45:24 PM PDT 23
Finished Oct 08 01:45:26 PM PDT 23
Peak memory 206040 kb
Host smart-6b494745-ddc0-42eb-8c22-3a11e78da3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792433370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2792433370
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4083268199
Short name T150
Test name
Test status
Simulation time 19403598 ps
CPU time 1 seconds
Started Oct 08 01:42:33 PM PDT 23
Finished Oct 08 01:42:34 PM PDT 23
Peak memory 204672 kb
Host smart-0772c4e0-24ae-4fd5-a923-a8f8ea040e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083268199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4083268199
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1064840264
Short name T568
Test name
Test status
Simulation time 25386451 ps
CPU time 0.83 seconds
Started Oct 08 01:45:27 PM PDT 23
Finished Oct 08 01:45:28 PM PDT 23
Peak memory 214432 kb
Host smart-6eb9db09-9496-433a-8fcb-30207012bdfa
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064840264 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1064840264
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2047693510
Short name T466
Test name
Test status
Simulation time 134589505 ps
CPU time 0.99 seconds
Started Oct 08 01:42:49 PM PDT 23
Finished Oct 08 01:42:51 PM PDT 23
Peak memory 214588 kb
Host smart-651aef88-c7a7-455d-8510-381b5e88651e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047693510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2047693510
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3633494267
Short name T195
Test name
Test status
Simulation time 18131892 ps
CPU time 1 seconds
Started Oct 08 01:42:46 PM PDT 23
Finished Oct 08 01:42:47 PM PDT 23
Peak memory 215500 kb
Host smart-2d9d4487-43e4-44bd-b55d-bb44923901a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633494267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3633494267
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.3376184964
Short name T582
Test name
Test status
Simulation time 31330212 ps
CPU time 0.9 seconds
Started Oct 08 01:50:30 PM PDT 23
Finished Oct 08 01:50:31 PM PDT 23
Peak memory 214628 kb
Host smart-a889a9d0-7086-4244-8a69-4b6e1f012ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376184964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3376184964
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.304471000
Short name T292
Test name
Test status
Simulation time 24533629 ps
CPU time 0.89 seconds
Started Oct 08 01:42:49 PM PDT 23
Finished Oct 08 01:42:51 PM PDT 23
Peak memory 204872 kb
Host smart-dd831c9a-fb95-4083-a702-e21da7cd8ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304471000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.304471000
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.952791152
Short name T618
Test name
Test status
Simulation time 68570228 ps
CPU time 0.9 seconds
Started Oct 08 01:43:36 PM PDT 23
Finished Oct 08 01:43:37 PM PDT 23
Peak memory 204932 kb
Host smart-7d4ef9c9-edb3-4ece-abb5-e629dc491aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952791152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.952791152
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1342564230
Short name T709
Test name
Test status
Simulation time 451469110 ps
CPU time 3.66 seconds
Started Oct 08 01:56:24 PM PDT 23
Finished Oct 08 01:56:27 PM PDT 23
Peak memory 205636 kb
Host smart-8db1cf6c-8583-497a-9741-157168a94c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342564230 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1342564230
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2316855559
Short name T485
Test name
Test status
Simulation time 68300533627 ps
CPU time 877.01 seconds
Started Oct 08 01:41:48 PM PDT 23
Finished Oct 08 01:56:26 PM PDT 23
Peak memory 215516 kb
Host smart-34568a2e-69f0-4ed8-a26e-5eea504fcd73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316855559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2316855559
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2136367506
Short name T714
Test name
Test status
Simulation time 38069025 ps
CPU time 1.11 seconds
Started Oct 08 01:53:50 PM PDT 23
Finished Oct 08 01:53:52 PM PDT 23
Peak memory 221628 kb
Host smart-7f4d5c3a-1b9f-456b-9a66-37f307568cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136367506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2136367506
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/71.edn_err.2302679061
Short name T202
Test name
Test status
Simulation time 31063728 ps
CPU time 0.84 seconds
Started Oct 08 01:44:24 PM PDT 23
Finished Oct 08 01:44:25 PM PDT 23
Peak memory 215412 kb
Host smart-4cbd6268-1b36-42a9-8c4f-fa4673389dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302679061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2302679061
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/72.edn_err.447476840
Short name T520
Test name
Test status
Simulation time 21155081 ps
CPU time 1.22 seconds
Started Oct 08 01:53:53 PM PDT 23
Finished Oct 08 01:53:54 PM PDT 23
Peak memory 222112 kb
Host smart-16d71dbd-965b-4c18-9914-d833dcef2405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447476840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.447476840
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_err.1681225389
Short name T693
Test name
Test status
Simulation time 20952436 ps
CPU time 1.09 seconds
Started Oct 08 01:53:50 PM PDT 23
Finished Oct 08 01:53:51 PM PDT 23
Peak memory 214540 kb
Host smart-cf873cff-282a-4e30-a8a0-72f5cdb6fb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681225389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1681225389
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_err.1024350331
Short name T56
Test name
Test status
Simulation time 22738194 ps
CPU time 0.87 seconds
Started Oct 08 01:53:53 PM PDT 23
Finished Oct 08 01:53:54 PM PDT 23
Peak memory 214056 kb
Host smart-2e30ba63-7b8a-44cb-b417-0bdcb7d2db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024350331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1024350331
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.1154314876
Short name T246
Test name
Test status
Simulation time 93282823 ps
CPU time 0.89 seconds
Started Oct 08 01:46:04 PM PDT 23
Finished Oct 08 01:46:05 PM PDT 23
Peak memory 214500 kb
Host smart-b5d05852-9a6a-4098-808c-a9af49cdb8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154314876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1154314876
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/76.edn_err.2095744397
Short name T182
Test name
Test status
Simulation time 23624627 ps
CPU time 1.04 seconds
Started Oct 08 01:53:53 PM PDT 23
Finished Oct 08 01:53:55 PM PDT 23
Peak memory 222152 kb
Host smart-d239f73d-c0a1-4eac-8f02-fbe4f0642eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095744397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2095744397
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.4108947204
Short name T204
Test name
Test status
Simulation time 39435454 ps
CPU time 0.83 seconds
Started Oct 08 01:53:51 PM PDT 23
Finished Oct 08 01:53:53 PM PDT 23
Peak memory 215656 kb
Host smart-943d0344-4fb8-4d6d-b9ea-531508eea5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108947204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4108947204
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.2977376714
Short name T47
Test name
Test status
Simulation time 21250716 ps
CPU time 1.09 seconds
Started Oct 08 01:53:53 PM PDT 23
Finished Oct 08 01:53:55 PM PDT 23
Peak memory 222136 kb
Host smart-c9128440-7e0d-47ba-bb42-7ba695faf6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977376714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2977376714
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/79.edn_err.4204601705
Short name T183
Test name
Test status
Simulation time 20252134 ps
CPU time 1.02 seconds
Started Oct 08 01:44:27 PM PDT 23
Finished Oct 08 01:44:29 PM PDT 23
Peak memory 215620 kb
Host smart-f40df18e-9b49-4925-8ef6-7f31ab8b0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204601705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4204601705
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.581478216
Short name T57
Test name
Test status
Simulation time 73539727 ps
CPU time 0.9 seconds
Started Oct 08 01:46:26 PM PDT 23
Finished Oct 08 01:46:27 PM PDT 23
Peak memory 206004 kb
Host smart-ac394462-2b62-4e77-941a-a2430deb9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581478216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.581478216
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2782683174
Short name T569
Test name
Test status
Simulation time 31436297 ps
CPU time 0.91 seconds
Started Oct 08 01:42:55 PM PDT 23
Finished Oct 08 01:42:57 PM PDT 23
Peak memory 205144 kb
Host smart-6b718d34-b1ca-4f87-ad15-985ad4fcfbee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782683174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2782683174
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1051012854
Short name T135
Test name
Test status
Simulation time 27104863 ps
CPU time 0.82 seconds
Started Oct 08 01:48:52 PM PDT 23
Finished Oct 08 01:48:53 PM PDT 23
Peak memory 214480 kb
Host smart-01595f4d-65f2-47c8-bc0b-72451d768f2f
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051012854 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1051012854
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2277058949
Short name T180
Test name
Test status
Simulation time 24292753 ps
CPU time 1.05 seconds
Started Oct 08 01:41:41 PM PDT 23
Finished Oct 08 01:41:46 PM PDT 23
Peak memory 214548 kb
Host smart-afe1846b-b394-4d1b-a12a-d8c7d7d4b120
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277058949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2277058949
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3287545383
Short name T192
Test name
Test status
Simulation time 22585076 ps
CPU time 1 seconds
Started Oct 08 01:42:25 PM PDT 23
Finished Oct 08 01:42:26 PM PDT 23
Peak memory 221664 kb
Host smart-f073fbeb-7b82-48a2-96d1-ae7971a5aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287545383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3287545383
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2273610968
Short name T279
Test name
Test status
Simulation time 16207365 ps
CPU time 0.98 seconds
Started Oct 08 01:47:28 PM PDT 23
Finished Oct 08 01:47:29 PM PDT 23
Peak memory 205276 kb
Host smart-daf24e41-54e4-4189-99d5-4889b2f2cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273610968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2273610968
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4258363823
Short name T474
Test name
Test status
Simulation time 25642897 ps
CPU time 1 seconds
Started Oct 08 01:44:01 PM PDT 23
Finished Oct 08 01:44:02 PM PDT 23
Peak memory 221580 kb
Host smart-7703e040-da11-4f93-864a-3c8e2dfb794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258363823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4258363823
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1362621353
Short name T20
Test name
Test status
Simulation time 36660453 ps
CPU time 0.88 seconds
Started Oct 08 01:47:28 PM PDT 23
Finished Oct 08 01:47:30 PM PDT 23
Peak memory 204728 kb
Host smart-5397af1b-319b-4dc5-868f-f3552ead1174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362621353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1362621353
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2999664984
Short name T210
Test name
Test status
Simulation time 15424612 ps
CPU time 0.89 seconds
Started Oct 08 01:42:35 PM PDT 23
Finished Oct 08 01:42:36 PM PDT 23
Peak memory 204676 kb
Host smart-2dfe8bf7-adfd-4441-a92d-7ff83cc8fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999664984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2999664984
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.806846437
Short name T651
Test name
Test status
Simulation time 600445846 ps
CPU time 3.45 seconds
Started Oct 08 01:42:30 PM PDT 23
Finished Oct 08 01:42:34 PM PDT 23
Peak memory 205800 kb
Host smart-a4f41f6f-48b0-4883-91f2-75e9698a889f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806846437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.806846437
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_err.2538537290
Short name T177
Test name
Test status
Simulation time 24247887 ps
CPU time 1.08 seconds
Started Oct 08 01:44:28 PM PDT 23
Finished Oct 08 01:44:30 PM PDT 23
Peak memory 228536 kb
Host smart-37068550-3abd-4ef7-aa68-b4a7d329e039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538537290 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2538537290
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/81.edn_err.3434559493
Short name T46
Test name
Test status
Simulation time 102267043 ps
CPU time 0.9 seconds
Started Oct 08 01:51:40 PM PDT 23
Finished Oct 08 01:51:41 PM PDT 23
Peak memory 220568 kb
Host smart-6b90a5c3-c6b2-437c-b871-2fa8b1687bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434559493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3434559493
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.2476895084
Short name T523
Test name
Test status
Simulation time 18946559 ps
CPU time 1.02 seconds
Started Oct 08 01:50:41 PM PDT 23
Finished Oct 08 01:50:42 PM PDT 23
Peak memory 215576 kb
Host smart-b7cd8f2e-804f-4c55-8fd2-413810e7a779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476895084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2476895084
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.3119376206
Short name T472
Test name
Test status
Simulation time 18373864 ps
CPU time 1.01 seconds
Started Oct 08 01:45:44 PM PDT 23
Finished Oct 08 01:45:46 PM PDT 23
Peak memory 215504 kb
Host smart-a07cd9fe-a378-414d-bf16-7df4b0c2bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119376206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3119376206
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.2163779921
Short name T164
Test name
Test status
Simulation time 46836730 ps
CPU time 0.99 seconds
Started Oct 08 01:45:44 PM PDT 23
Finished Oct 08 01:45:45 PM PDT 23
Peak memory 228760 kb
Host smart-24df5a37-4721-43a6-80e0-52ca52a0fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163779921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2163779921
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.3052968747
Short name T634
Test name
Test status
Simulation time 45373947 ps
CPU time 1.07 seconds
Started Oct 08 01:53:43 PM PDT 23
Finished Oct 08 01:53:44 PM PDT 23
Peak memory 216852 kb
Host smart-a44770db-5497-4742-a8dd-a8d2c85fca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052968747 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3052968747
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.1375496108
Short name T205
Test name
Test status
Simulation time 21349000 ps
CPU time 0.89 seconds
Started Oct 08 03:34:12 PM PDT 23
Finished Oct 08 03:34:13 PM PDT 23
Peak memory 215836 kb
Host smart-61743649-949b-4a57-b006-5d61eafc5d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375496108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1375496108
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/87.edn_err.2113093556
Short name T163
Test name
Test status
Simulation time 56624583 ps
CPU time 1.55 seconds
Started Oct 08 01:45:49 PM PDT 23
Finished Oct 08 01:45:51 PM PDT 23
Peak memory 227660 kb
Host smart-f5a5541d-9553-432a-8aa3-7120ea567abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113093556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2113093556
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/88.edn_err.1850308316
Short name T494
Test name
Test status
Simulation time 18841687 ps
CPU time 1.02 seconds
Started Oct 08 01:45:48 PM PDT 23
Finished Oct 08 01:45:49 PM PDT 23
Peak memory 214472 kb
Host smart-588e99f6-5498-419f-8e28-9bf52ff7feee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850308316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1850308316
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.3132424723
Short name T616
Test name
Test status
Simulation time 45954437 ps
CPU time 0.97 seconds
Started Oct 08 01:44:42 PM PDT 23
Finished Oct 08 01:44:43 PM PDT 23
Peak memory 215700 kb
Host smart-5772e8fd-f9b1-45cd-b8e3-0b839e5785e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132424723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3132424723
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.3711734845
Short name T653
Test name
Test status
Simulation time 16322798 ps
CPU time 0.92 seconds
Started Oct 08 01:46:42 PM PDT 23
Finished Oct 08 01:46:44 PM PDT 23
Peak memory 205128 kb
Host smart-740f9e37-1d42-47ab-9c19-566351310230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711734845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3711734845
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4094873587
Short name T574
Test name
Test status
Simulation time 14105773 ps
CPU time 0.86 seconds
Started Oct 08 01:49:41 PM PDT 23
Finished Oct 08 01:49:42 PM PDT 23
Peak memory 205232 kb
Host smart-64c8d854-b421-41f7-be09-b57041cfac63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094873587 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4094873587
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2554665151
Short name T590
Test name
Test status
Simulation time 27661794 ps
CPU time 0.77 seconds
Started Oct 08 01:46:32 PM PDT 23
Finished Oct 08 01:46:33 PM PDT 23
Peak memory 214432 kb
Host smart-d242d5f4-e47a-498e-b987-d7661999c9ff
User root
Command /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554665151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2554665151
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1964569400
Short name T603
Test name
Test status
Simulation time 31046572 ps
CPU time 1.05 seconds
Started Oct 08 01:43:09 PM PDT 23
Finished Oct 08 01:43:10 PM PDT 23
Peak memory 214820 kb
Host smart-d00ca17c-77d8-4853-b57b-874acf3ec4ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964569400 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1964569400
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2153124354
Short name T666
Test name
Test status
Simulation time 19151533 ps
CPU time 1.08 seconds
Started Oct 08 01:43:54 PM PDT 23
Finished Oct 08 01:43:56 PM PDT 23
Peak memory 215628 kb
Host smart-c6ae544e-a5ed-4370-b1c6-3c3fdc054291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153124354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2153124354
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_intr.1248434372
Short name T87
Test name
Test status
Simulation time 22566140 ps
CPU time 0.87 seconds
Started Oct 08 01:43:51 PM PDT 23
Finished Oct 08 01:43:52 PM PDT 23
Peak memory 214672 kb
Host smart-196df32f-b338-4891-9ee7-a00caca4e066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248434372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1248434372
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.239405897
Short name T290
Test name
Test status
Simulation time 31285217 ps
CPU time 0.84 seconds
Started Oct 08 01:47:43 PM PDT 23
Finished Oct 08 01:47:44 PM PDT 23
Peak memory 204888 kb
Host smart-3e20518d-eebb-446d-8138-7940ca5b54e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239405897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.239405897
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.873388653
Short name T707
Test name
Test status
Simulation time 41408552 ps
CPU time 0.8 seconds
Started Oct 08 01:48:52 PM PDT 23
Finished Oct 08 01:48:53 PM PDT 23
Peak memory 204812 kb
Host smart-f4781f53-6e49-44d0-8017-da24a14407cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873388653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.873388653
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1629361202
Short name T539
Test name
Test status
Simulation time 334100035 ps
CPU time 1.78 seconds
Started Oct 08 01:43:12 PM PDT 23
Finished Oct 08 01:43:14 PM PDT 23
Peak memory 206020 kb
Host smart-ffb7220e-2e6c-4d56-969f-7e34fb76a282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629361202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1629361202
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.428917286
Short name T546
Test name
Test status
Simulation time 83542540992 ps
CPU time 465.56 seconds
Started Oct 08 01:43:54 PM PDT 23
Finished Oct 08 01:51:40 PM PDT 23
Peak memory 215068 kb
Host smart-407d85b9-7fb8-4f91-97f6-871c4f89d5ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428917286 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.428917286
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.4073869931
Short name T86
Test name
Test status
Simulation time 21444244 ps
CPU time 1 seconds
Started Oct 08 01:45:53 PM PDT 23
Finished Oct 08 01:45:54 PM PDT 23
Peak memory 214644 kb
Host smart-4fdabbe6-6951-46a6-898a-06d37417eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073869931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4073869931
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.2733630678
Short name T189
Test name
Test status
Simulation time 28183886 ps
CPU time 0.9 seconds
Started Oct 08 01:54:39 PM PDT 23
Finished Oct 08 01:54:40 PM PDT 23
Peak memory 215836 kb
Host smart-c1abc6ed-8c27-4c9c-a297-0684c03749bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733630678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2733630678
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.2925288363
Short name T540
Test name
Test status
Simulation time 26234715 ps
CPU time 0.9 seconds
Started Oct 08 01:46:24 PM PDT 23
Finished Oct 08 01:46:25 PM PDT 23
Peak memory 214540 kb
Host smart-83a99995-dd60-4841-8050-3943a492e4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925288363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2925288363
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/93.edn_err.3833315786
Short name T701
Test name
Test status
Simulation time 32957965 ps
CPU time 0.97 seconds
Started Oct 08 01:44:45 PM PDT 23
Finished Oct 08 01:44:46 PM PDT 23
Peak memory 221236 kb
Host smart-941f56e9-9554-43bc-856a-54b1856da23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833315786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3833315786
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/94.edn_err.3142772415
Short name T203
Test name
Test status
Simulation time 20445071 ps
CPU time 1.13 seconds
Started Oct 08 02:57:16 PM PDT 23
Finished Oct 08 02:57:17 PM PDT 23
Peak memory 222092 kb
Host smart-edf7d89b-8f90-4463-a7b0-5755b3b55167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142772415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3142772415
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.2165173231
Short name T234
Test name
Test status
Simulation time 28239847 ps
CPU time 1.2 seconds
Started Oct 08 01:47:34 PM PDT 23
Finished Oct 08 01:47:35 PM PDT 23
Peak memory 216940 kb
Host smart-b94656b3-b4f4-4ed6-890d-7301a7917872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165173231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2165173231
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/96.edn_err.213451778
Short name T565
Test name
Test status
Simulation time 29974754 ps
CPU time 1.37 seconds
Started Oct 08 01:49:14 PM PDT 23
Finished Oct 08 01:49:15 PM PDT 23
Peak memory 227864 kb
Host smart-7d7f73e5-d73f-475d-afc1-ac10908f6806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213451778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.213451778
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.622816800
Short name T190
Test name
Test status
Simulation time 19700225 ps
CPU time 1.01 seconds
Started Oct 08 01:50:18 PM PDT 23
Finished Oct 08 01:50:20 PM PDT 23
Peak memory 215700 kb
Host smart-e835d6e0-aae6-4821-ab14-33d7aa97482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622816800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.622816800
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.1809345309
Short name T481
Test name
Test status
Simulation time 31637096 ps
CPU time 0.96 seconds
Started Oct 08 03:00:48 PM PDT 23
Finished Oct 08 03:00:49 PM PDT 23
Peak memory 215648 kb
Host smart-231d5fde-1be1-4351-96cf-d25dae4ea349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809345309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1809345309
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.559478404
Short name T237
Test name
Test status
Simulation time 37024528 ps
CPU time 1.09 seconds
Started Oct 08 03:33:58 PM PDT 23
Finished Oct 08 03:34:00 PM PDT 23
Peak memory 214528 kb
Host smart-8ae17c12-af66-4ed4-9c49-2f7a3e422de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559478404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.559478404
Directory /workspace/99.edn_err/latest
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