Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
7647 |
1 |
|
|
T2 |
46 |
|
T17 |
246 |
|
T20 |
204 |
all_values[1] |
7647 |
1 |
|
|
T2 |
46 |
|
T17 |
246 |
|
T20 |
204 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7886 |
1 |
|
|
T2 |
50 |
|
T17 |
248 |
|
T20 |
200 |
auto[1] |
7408 |
1 |
|
|
T2 |
42 |
|
T17 |
244 |
|
T20 |
208 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5972 |
1 |
|
|
T2 |
42 |
|
T17 |
177 |
|
T20 |
175 |
auto[1] |
9322 |
1 |
|
|
T2 |
50 |
|
T17 |
315 |
|
T20 |
233 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8995 |
1 |
|
|
T2 |
54 |
|
T17 |
274 |
|
T20 |
250 |
auto[1] |
6299 |
1 |
|
|
T2 |
38 |
|
T17 |
218 |
|
T20 |
158 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
1565 |
1 |
|
|
T2 |
10 |
|
T17 |
59 |
|
T20 |
53 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
713 |
1 |
|
|
T2 |
4 |
|
T17 |
13 |
|
T20 |
16 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
1435 |
1 |
|
|
T2 |
10 |
|
T17 |
43 |
|
T20 |
41 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
813 |
1 |
|
|
T2 |
2 |
|
T17 |
26 |
|
T20 |
17 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
1639 |
1 |
|
|
T2 |
10 |
|
T17 |
57 |
|
T20 |
45 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
1482 |
1 |
|
|
T2 |
10 |
|
T17 |
48 |
|
T20 |
32 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
1567 |
1 |
|
|
T2 |
11 |
|
T17 |
28 |
|
T20 |
28 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
716 |
1 |
|
|
T2 |
3 |
|
T17 |
28 |
|
T20 |
22 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
1405 |
1 |
|
|
T2 |
11 |
|
T17 |
47 |
|
T20 |
53 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
781 |
1 |
|
|
T2 |
3 |
|
T17 |
30 |
|
T20 |
20 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T2 |
12 |
|
T17 |
63 |
|
T20 |
36 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
1492 |
1 |
|
|
T2 |
6 |
|
T17 |
50 |
|
T20 |
45 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |